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pl_refclk_p ] ;# PL_CLK_P +set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVPECL } [get_ports pl_sysref_p ] ;# PL_SYSREF_P + +set_property -dict {PACKAGE_PIN AW5 IOSTANDARD LVCMOS18} [get_ports lmk_spi_sck ] ;# LMK_SPI_CS_LS +set_property -dict {PACKAGE_PIN AW3 IOSTANDARD LVCMOS18} [get_ports lmk_spi_cs ] ;# LMK_SPI_SCK_LS +set_property -dict {PACKAGE_PIN AW6 IOSTANDARD LVCMOS18} [get_ports lmk_spi_mosi_sdio ] ;# LMK_SPI_SDI_LS +set_property -dict {PACKAGE_PIN AW4 IOSTANDARD LVCMOS18} [get_ports lmk_spi_miso ] ;# LMK_SPI_SDO_LS + +# Route HDGC clock through BUFG to adjacent CMT +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_system_bd_wrapper/system_bd_i/mts_clk_gen/util_ds_buf_pl_clk/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O] diff --git a/projects/rfsoc_eval/rfsoc_eval_demo/rfsoc_eval_demo.srcs/sim_1/new/tb_baseband.v b/projects/rfsoc_eval/rfsoc_eval_demo/rfsoc_eval_demo.srcs/sim_1/new/tb_baseband.v new file mode 100644 index 00000000..5aa72a4b --- /dev/null +++ b/projects/rfsoc_eval/rfsoc_eval_demo/rfsoc_eval_demo.srcs/sim_1/new/tb_baseband.v @@ -0,0 +1,56 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2022/03/23 20:39:14 +// Design Name: +// Module Name: tb_baseband_new +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_baseband(); + +reg clk = 'b0; +reg rst = 'b1; +wire [15:0] tx_data_i; +wire [15:0] tx_data_q; + +reg [ 1:0] waveform_sel = 2'b00; +reg sweep_on = 1'b0; +reg [31:0] freq_set = 32'd0; // 20 / 245.76 * 2^31 +reg [ 1:0] iq_sel = 2'b11; +reg [ 3:0] bb_rshift = 4'd0; + +baseband_tx u_baseband_tx +( + .clk (clk ), + .rst (rst ), + .tx_data_i (tx_data_i ), + .tx_data_q (tx_data_q ), + + .waveform_sel (waveform_sel ), + .sweep_on (sweep_on ), + .freq_set (freq_set ), + .iq_sel (iq_sel ), + .bb_rshift (bb_rshift ) +); + +initial begin + #101 rst = 1'b0; +end + +always #3 clk = ~clk; + +endmodule diff --git a/projects/rfsoc_eval/rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_auto_ds_0/system_bd_auto_ds_0.xci b/projects/rfsoc_eval/rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_auto_ds_0/system_bd_auto_ds_0.xci new file mode 100644 index 00000000..11d13ac0 --- /dev/null +++ b/projects/rfsoc_eval/rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_auto_ds_0/system_bd_auto_ds_0.xci @@ -0,0 +1,336 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_auto_ds_0", + "cell_name": "ps8_axi_periph/s00_couplers/auto_ds", + "component_reference": "xilinx.com:ip:axi_dwidth_converter:2.1", + "ip_revision": "31", + "gen_directory": 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"is_static_object": false } ], + "HAS_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "AWADDR": [ { "physical_name": "m_axi_awaddr" } ], + "AWPROT": [ { "physical_name": "m_axi_awprot" } ], + "AWVALID": [ { "physical_name": "m_axi_awvalid" } ], + "AWREADY": [ { "physical_name": "m_axi_awready" } ], + "WDATA": [ { "physical_name": "m_axi_wdata" } ], + "WSTRB": [ { "physical_name": "m_axi_wstrb" } ], + "WVALID": [ { "physical_name": "m_axi_wvalid" } ], + "WREADY": [ { "physical_name": "m_axi_wready" } ], + "BRESP": [ { "physical_name": "m_axi_bresp" } ], + "BVALID": [ { "physical_name": "m_axi_bvalid" } ], + "BREADY": [ { "physical_name": "m_axi_bready" } ], + "ARADDR": [ { "physical_name": "m_axi_araddr" } ], + "ARPROT": [ { "physical_name": "m_axi_arprot" } ], + "ARVALID": [ { "physical_name": "m_axi_arvalid" } ], + "ARREADY": [ { "physical_name": "m_axi_arready" } ], + "RDATA": [ { "physical_name": "m_axi_rdata" } ], + "RRESP": [ { "physical_name": "m_axi_rresp" } ], + "RVALID": [ { "physical_name": "m_axi_rvalid" } ], + "RREADY": [ { "physical_name": "m_axi_rready" } ] + } + }, + "CLK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "FREQ_HZ": [ { "value": "99999001", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "aclk" } ] + } + }, + "RST": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], + "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "aresetn" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/projects/rfsoc_eval/rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0.xci b/projects/rfsoc_eval/rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0.xci new file mode 100644 index 00000000..6ce66181 --- /dev/null +++ b/projects/rfsoc_eval/rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0.xci @@ -0,0 +1,286 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_axi_spi_engine_0", + "cell_name": "axi_spi_engine/axi_spi_engine", + "component_reference": "analog.com:user:axi_spi_engine:1.0", + "ip_revision": "1", + "gen_directory": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0", + "parameters": { + "component_parameters": { + "CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SYNC_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SDO_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ], + 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"xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "s_axi_aresetn" } ] + } + } + }, + "memory_maps": { + "s_axi": { + "address_blocks": { + "axi_lite": { + "base_address": "0", + "range": "65536" + } + } + } + } + } + } +} \ No newline at end of file diff --git a/projects/rfsoc_eval/rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_clk_wiz_pl_clk_0/system_bd_clk_wiz_pl_clk_0.xci b/projects/rfsoc_eval/rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_clk_wiz_pl_clk_0/system_bd_clk_wiz_pl_clk_0.xci new file mode 100644 index 00000000..f9735651 --- /dev/null +++ b/projects/rfsoc_eval/rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_clk_wiz_pl_clk_0/system_bd_clk_wiz_pl_clk_0.xci @@ -0,0 +1,658 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_clk_wiz_pl_clk_0", + "cell_name": "mts_clk_gen/clk_wiz_pl_clk", + "component_reference": "xilinx.com:ip:clk_wiz:6.0", + "ip_revision": "14", + "gen_directory": "../../../../../../rfsoc_eval_demo.gen/sources_1/bd/system_bd/ip/system_bd_clk_wiz_pl_clk_0", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "system_bd_clk_wiz_pl_clk_0", "resolve_type": "user", "usage": "all" } ], + "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ], + "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ], + "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ], + "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_PHASE_ALIGNMENT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ], + "PRIM_IN_FREQ": [ { "value": "245.76", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ], + "PHASESHIFT_MODE": [ { "value": "LATENCY", "resolve_type": "user", "usage": "all" } ], + "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ], + "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ], + "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "SECONDARY_IN_FREQ": [ { "value": "100.000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ], + "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], + "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ], + "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN1_JITTER_PS": [ { "value": "40.69", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_USED": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "NUM_OUT_CLKS": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ], + "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ], + "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ], + "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ], + "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ], + "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ], + "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ], + "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ], + "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ], + "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ], + "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ], + "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "245.76", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ], + "CLKOUT2_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ], + "CLKOUT3_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ], + "CLKOUT4_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ], + "CLKOUT5_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ], + "CLKOUT6_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ], + "CLKOUT7_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ], + "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ], + "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ], + "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ], + "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ], + "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ], + "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ], + "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ], + "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ], + "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ], + "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ], + "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ], + "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ], + "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKIN1_PERIOD": [ { "value": "4.069", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_COMPENSATION": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ], + "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_STARTUP_WAIT": [ { "value": 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], + "C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ], + "C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ], + "C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ], + "C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ], + "C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", 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"is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "peripheral_aresetn" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/projects/rfsoc_eval/rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0.xci b/projects/rfsoc_eval/rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0.xci new file mode 100644 index 00000000..4fd662e4 --- /dev/null +++ b/projects/rfsoc_eval/rfsoc_eval_demo/rfsoc_eval_demo.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0.xci @@ -0,0 +1,174 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_spi_engine_execution_0", + "cell_name": "axi_spi_engine/spi_engine_execution", + "component_reference": "analog.com:user:spi_engine_execution:1.0", + "ip_revision": "1", + "gen_directory": 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"usage": "all" } ], + "DAC0_Sampling_Rate": [ { "value": "4.9152", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "DAC0_Refclk_Freq": [ { "value": "245.760", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "DAC0_Outclk_Freq": [ { "value": "307.200", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "DAC0_Fabric_Freq": [ { "value": "245.760", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "DAC0_Link_Coupling": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DAC0_Multi_Tile_Sync": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "DAC0_Band": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "DAC0_VOP": [ { "value": "20.0", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + 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"format": "bitString", "usage": "all" } ], + "M01_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", 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], + "WSTRB": [ { "physical_name": "m_axi_wstrb", "physical_left": "3", "physical_right": "0" } ], + "WVALID": [ { "physical_name": "m_axi_wvalid", "physical_left": "0", "physical_right": "0" } ], + "WREADY": [ { "physical_name": "m_axi_wready", "physical_left": "0", "physical_right": "0" } ], + "BRESP": [ { "physical_name": "m_axi_bresp", "physical_left": "1", "physical_right": "0" } ], + "BVALID": [ { "physical_name": "m_axi_bvalid", "physical_left": "0", "physical_right": "0" } ], + "BREADY": [ { "physical_name": "m_axi_bready", "physical_left": "0", "physical_right": "0" } ], + "ARADDR": [ { "physical_name": "m_axi_araddr", "physical_left": "39", "physical_right": "0" } ], + "ARPROT": [ { "physical_name": "m_axi_arprot", "physical_left": "2", "physical_right": "0" } ], + "ARVALID": [ { "physical_name": "m_axi_arvalid", "physical_left": "0", "physical_right": "0" } ], + "ARREADY": [ { "physical_name": "m_axi_arready", "physical_left": "0", "physical_right": "0" } ], + "RDATA": [ { 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"resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": 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{ "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "AWADDR": [ { "physical_name": "m_axi_awaddr", "physical_left": "79", "physical_right": "40" } ], + "AWPROT": [ { "physical_name": "m_axi_awprot", "physical_left": "5", "physical_right": "3" } ], + "AWVALID": [ { "physical_name": "m_axi_awvalid", "physical_left": "1", "physical_right": "1" } ], + "AWREADY": [ { "physical_name": "m_axi_awready", "physical_left": "1", "physical_right": "1" } ], + "WDATA": [ { "physical_name": "m_axi_wdata", "physical_left": "63", "physical_right": "32" } ], + "WSTRB": [ { "physical_name": "m_axi_wstrb", "physical_left": "7", "physical_right": "4" } ], + "WVALID": [ { "physical_name": "m_axi_wvalid", "physical_left": "1", "physical_right": "1" } ], + "WREADY": [ { "physical_name": "m_axi_wready", "physical_left": "1", "physical_right": "1" } ], + "BRESP": [ { "physical_name": "m_axi_bresp", "physical_left": "3", "physical_right": "2" } ], + "BVALID": [ { "physical_name": "m_axi_bvalid", "physical_left": "1", "physical_right": "1" } ], + "BREADY": [ { "physical_name": "m_axi_bready", "physical_left": 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"resolve_type": "user", "usage": "all" } ], + "PSU__PCIE__INTX_PIN": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PSU__PCIE__MSIX_CAPABILITY": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PSU__PCIE__MSIX_TABLE_SIZE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PSU__PCIE__MSIX_TABLE_OFFSET": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PSU__PCIE__MSIX_BAR_INDICATOR": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PSU__PCIE__MSIX_PBA_OFFSET": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PSU__PCIE__MSIX_PBA_BAR_INDICATOR": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PSU__PCIE__BRIDGE_BAR_INDICATOR": [ { "value": "", "resolve_type": "user", "usage": "all" } ], + "PSU_MIO_TREE_PERIPHERALS": [ { "value": "Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#PMU GPI 0#PMU GPI 1#PMU GPI 2#PMU GPI 3#PMU GPI 4#PMU GPI 5#PMU GPO 0#PMU GPO 1#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PSU_MIO_TREE_SIGNALS": [ { "value": "sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#gpio0[6]#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#gpio0[24]#gpio0[25]#gpi[0]#gpi[1]#gpi[2]#gpi[3]#gpi[4]#gpi[5]#gpo[0]#gpo[1]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + 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"usage": "all" } ], + "PSU__CSU__CSU_TAMPER_11__RESPONSE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PSU__GEN_IPI_0__MASTER": [ { "value": "APU", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PSU__GEN_IPI_1__MASTER": [ { "value": "RPU0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PSU__GEN_IPI_2__MASTER": [ { "value": "RPU1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PSU__GEN_IPI_3__MASTER": [ { "value": "PMU", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PSU__GEN_IPI_4__MASTER": [ { "value": "PMU", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PSU__GEN_IPI_5__MASTER": [ { "value": "PMU", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PSU__GEN_IPI_6__MASTER": [ { "value": "PMU", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PSU__GEN_IPI_7__MASTER": [ { "value": "NONE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PSU__GEN_IPI_8__MASTER": [ { "value": "NONE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PSU__GEN_IPI_9__MASTER": [ { "value": "NONE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PSU__GEN_IPI_10__MASTER": [ { "value": "NONE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PSU__GEN_IPI__TRUSTZONE": [ { "value": "} \ + CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ + CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ + CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \ + CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \ + CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \ + CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \ + CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \ + CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \ + CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \ + CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \ + CONFIG.PSU__PCIE__LANE0__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE1__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE2__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE3__ENABLE {0} \ + CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \ + CONFIG.PSU__GT__LINK_SPEED {HBR} \ + CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ + CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ + CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \ + CONFIG.PSU__USB0__REF_CLK_FREQ {26} \ + CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \ + CONFIG.PSU__DP__REF_CLK_FREQ {27} \ + CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk3} \ + CONFIG.PSU__SATA__REF_CLK_FREQ {125} \ + CONFIG.PSU__DP__LANE_SEL {Dual Lower} \ + CONFIG.PSU__PCIE__BAR0_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR0_64BIT {0} \ + CONFIG.PSU__PCIE__BAR0_VAL {} \ + CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR1_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR1_64BIT {0} \ + CONFIG.PSU__PCIE__BAR1_VAL {} \ + CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR2_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR2_64BIT {0} \ + CONFIG.PSU__PCIE__BAR2_VAL {} \ + CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR3_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR3_64BIT {0} \ + CONFIG.PSU__PCIE__BAR3_VAL {} \ + CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR4_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR4_64BIT {0} \ + CONFIG.PSU__PCIE__BAR4_VAL {} \ + CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR5_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR5_64BIT {0} \ + CONFIG.PSU__PCIE__BAR5_VAL {} \ + CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__EROM_ENABLE {0} \ + CONFIG.PSU__PCIE__EROM_VAL {} \ + CONFIG.PSU__PCIE__VENDOR_ID {} \ + CONFIG.PSU__PCIE__DEVICE_ID {} \ + CONFIG.PSU__PCIE__REVISION_ID {} \ + CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \ + CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \ + CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \ + CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \ + CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \ + CONFIG.PSU__PCIE__CLASS_CODE_VALUE {} \ + CONFIG.PSU__PCIE__AER_CAPABILITY {0} \ + CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \ + CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \ + CONFIG.PSU__PCIE__RECEIVER_ERR {0} \ + CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \ + CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \ + CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \ + CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \ + CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \ + CONFIG.PSU__PCIE__ECRC_ERR {0} \ + CONFIG.PSU__PCIE__ACS_VIOLAION {0} \ + CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \ + CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \ + CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \ + CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \ + CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \ + CONFIG.PSU__PCIE__ACS_VIOLATION {0} \ + CONFIG.PSU__PCIE__MULTIHEADER {0} \ + CONFIG.PSU__PCIE__ECRC_CHECK {0} \ + CONFIG.PSU__PCIE__ECRC_GEN {0} \ + CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \ + CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \ + CONFIG.PSU__PCIE__INTX_GENERATION {0} \ + CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \ + CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \ + CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \ + CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \ + CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \ + CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \ + CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \ + CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \ + CONFIG.PSU_IMPORT_BOARD_PRESET {} \ + CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \ + CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure} \ + CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ + CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \ + CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \ + CONFIG.PSU__PROTECTION__DEBUG {0} \ + CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \ + CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \ + CONFIG.PSU__PROTECTION__ENABLE {0} \ + CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \ + CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \ + CONFIG.PSU__EP__IP {0} \ + CONFIG.PSU__ACTUAL__IP {1} \ + CONFIG.SUBPRESET1 {Custom} \ + CONFIG.SUBPRESET2 {Custom} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#PMU GPI 0#PMU GPI 1#PMU GPI 2#PMU GPI 3#PMU GPI 4#PMU GPI 5#PMU GPO 0#PMU GPO 1#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ + CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#gpio0[6]#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#gpio0[24]#gpio0[25]#gpi[0]#gpi[1]#gpi[2]#gpi[3]#gpi[4]#gpi[5]#gpo[0]#gpo[1]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \ + CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \ + CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \ + CONFIG.PSU__NAND__READY0_BUSY__ENABLE {0} \ + CONFIG.PSU__NAND__READY1_BUSY__ENABLE {0} \ + CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \ + CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \ + CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ + CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ + CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ + CONFIG.PSU__PMU__GPI0__ENABLE {1} \ + CONFIG.PSU__PMU__GPI1__ENABLE {1} \ + CONFIG.PSU__PMU__GPI2__ENABLE {1} \ + CONFIG.PSU__PMU__GPI3__ENABLE {1} \ + CONFIG.PSU__PMU__GPI4__ENABLE {1} \ + CONFIG.PSU__PMU__GPI5__ENABLE {1} \ + CONFIG.PSU__PMU__GPO0__ENABLE {1} \ + CONFIG.PSU__PMU__GPO1__ENABLE {1} \ + CONFIG.PSU__PMU__GPO2__ENABLE {0} \ + CONFIG.PSU__PMU__GPO3__ENABLE {0} \ + CONFIG.PSU__PMU__GPO4__ENABLE {0} \ + CONFIG.PSU__PMU__GPO5__ENABLE {0} \ + CONFIG.PSU__PMU__GPI0__IO {MIO 26} \ + CONFIG.PSU__PMU__GPI1__IO {MIO 27} \ + CONFIG.PSU__PMU__GPI2__IO {MIO 28} \ + CONFIG.PSU__PMU__GPI3__IO {MIO 29} \ + CONFIG.PSU__PMU__GPI4__IO {MIO 30} \ + CONFIG.PSU__PMU__GPI5__IO {MIO 31} \ + CONFIG.PSU__PMU__GPO0__IO {MIO 32} \ + CONFIG.PSU__PMU__GPO1__IO {MIO 33} \ + CONFIG.PSU__PMU__GPO2__IO {} \ + CONFIG.PSU__PMU__GPO4__IO {} \ + CONFIG.PSU__PMU__GPO2__POLARITY {} \ + CONFIG.PSU__PMU__GPO4__POLARITY {} \ + CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \ + CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \ + CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \ + CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \ + CONFIG.PSU__QSPI__GRP_FBCLK__IO {} \ + CONFIG.PSU__SPI0__GRP_SS0__ENABLE {0} \ + CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \ + CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \ + CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SPI1__GRP_SS0__ENABLE {0} \ + CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \ + CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \ + CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \ + CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT0__RESET__ENABLE {0} \ + CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \ + CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT1__RESET__ENABLE {0} \ + CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \ + CONFIG.PSU__UART0__BAUD_RATE {115200} \ + CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \ + CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \ + CONFIG.PSU__UART1__BAUD_RATE {115200} \ + CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ + CONFIG.PSU__DDRC__AL {0} \ + CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \ + CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ + CONFIG.PSU__DDRC__CL {15} \ + CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ + CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \ + CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ + CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ + CONFIG.PSU__DDRC__CWL {11} \ + CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \ + CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \ + CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \ + CONFIG.PSU__DDRC__ECC {Disabled} \ + CONFIG.PSU__DDRC__ECC_SCRUB {0} \ + CONFIG.PSU__DDRC__ENABLE {1} \ + CONFIG.PSU__DDRC__FREQ_MHZ {1} \ + CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ + CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \ + CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \ + CONFIG.PSU__DDRC__T_FAW {30.0} \ + CONFIG.PSU__DDRC__T_RAS_MIN {33} \ + CONFIG.PSU__DDRC__T_RC {46.5} \ + CONFIG.PSU__DDRC__T_RCD {15} \ + CONFIG.PSU__DDRC__T_RP {15} \ + CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ + CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ + CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ + CONFIG.PSU__DDRC__VREF {1} \ + CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \ + CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ + CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ + CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ + CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \ + CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__PLL_BYPASS {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ + CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ + CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ + CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \ + CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ + CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ + CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ + CONFIG.PSU__DDRC__FGRM {1X} \ + CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ + CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \ + CONFIG.PSU__DDRC__LP_ASR {manual normal} \ + CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ + CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ + CONFIG.PSU__DDRC__ADDR_MIRROR {0} \ + CONFIG.PSU__DDRC__EN_2ND_CLK {0} \ + CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \ + CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ + CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \ + CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ + CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ + CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \ + CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \ + CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ + CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ + CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ + CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ + CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ + CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ + CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ + CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ + CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ + CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ + CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ + CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ + CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ + CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ + CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ + CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ + CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ + CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ + CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ + CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ + CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ + CONFIG.PSU__DDR_QOS_ENABLE {0} \ + CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \ + CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \ + CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \ + CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {} \ + CONFIG.PSU__OVERRIDE_HPX_QOS {0} \ + CONFIG.PSU__FP__POWER__ON {1} \ + CONFIG.PSU__PL__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK0__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK1__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK2__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK3__POWER__ON {1} \ + CONFIG.PSU__TCM0A__POWER__ON {1} \ + CONFIG.PSU__TCM0B__POWER__ON {1} \ + CONFIG.PSU__TCM1A__POWER__ON {1} \ + CONFIG.PSU__TCM1B__POWER__ON {1} \ + CONFIG.PSU__RPU__POWER__ON {1} \ + CONFIG.PSU__L2_BANK0__POWER__ON {1} \ + CONFIG.PSU__GPU_PP0__POWER__ON {0} \ + CONFIG.PSU__GPU_PP1__POWER__ON {0} \ + CONFIG.PSU__ACPU0__POWER__ON {1} \ + CONFIG.PSU__ACPU1__POWER__ON {1} \ + CONFIG.PSU__ACPU2__POWER__ON {1} \ + CONFIG.PSU__ACPU3__POWER__ON {1} \ + CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \ + CONFIG.PSU__UART0__MODEM__ENABLE {0} \ + CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \ + CONFIG.PSU__UART1__MODEM__ENABLE {0} \ + CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \ + CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ + CONFIG.PSU__USB0__RESET__ENABLE {0} \ + CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ + CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ + CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__USB1__RESET__ENABLE {0} \ + CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ + CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \ + CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \ + CONFIG.PSU__USE__USB3_0_HUB {0} \ + CONFIG.PSU__USE__USB3_1_HUB {0} \ + CONFIG.PSU__USE__ADMA {0} \ + CONFIG.PSU__USE__M_AXI_GP0 {1} \ + CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \ + CONFIG.PSU__USE__M_AXI_GP1 {0} \ + CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \ + CONFIG.PSU__USE__M_AXI_GP2 {0} \ + CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ + CONFIG.PSU__USE__S_AXI_ACP {0} \ + CONFIG.PSU__USE__S_AXI_GP0 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP0 {0} \ + CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \ + CONFIG.PSU__USE__S_AXI_GP1 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP1 {0} \ + CONFIG.PSU__SAXIGP1__DATA_WIDTH {128} \ + CONFIG.PSU__USE__S_AXI_GP2 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP2 {0} \ + CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \ + CONFIG.PSU__USE__S_AXI_GP3 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP3 {0} \ + CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \ + CONFIG.PSU__USE__S_AXI_GP4 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP4 {0} \ + CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \ + CONFIG.PSU__USE__S_AXI_GP5 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP5 {0} \ + CONFIG.PSU__SAXIGP5__DATA_WIDTH {128} \ + CONFIG.PSU__USE__S_AXI_GP6 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP6 {0} \ + CONFIG.PSU__SAXIGP6__DATA_WIDTH {128} \ + CONFIG.PSU__USE__S_AXI_ACE {0} \ + CONFIG.PSU__TRACE_PIPELINE_WIDTH {8} \ + CONFIG.PSU__EN_EMIO_TRACE {0} \ + CONFIG.PSU__USE__AUDIO {0} \ + CONFIG.PSU__USE__VIDEO {0} \ + CONFIG.PSU__USE__PROC_EVENT_BUS {0} \ + CONFIG.PSU__USE__FTM {0} \ + CONFIG.PSU__USE__CROSS_TRIGGER {0} \ + CONFIG.PSU__FTM__CTI_IN_0 {0} \ + CONFIG.PSU__FTM__CTI_IN_1 {0} \ + CONFIG.PSU__FTM__CTI_IN_2 {0} \ + CONFIG.PSU__FTM__CTI_IN_3 {0} \ + CONFIG.PSU__FTM__CTI_OUT_0 {0} \ + CONFIG.PSU__FTM__CTI_OUT_1 {0} \ + CONFIG.PSU__FTM__CTI_OUT_2 {0} \ + CONFIG.PSU__FTM__CTI_OUT_3 {0} \ + CONFIG.PSU__FTM__GPO {0} \ + CONFIG.PSU__FTM__GPI {0} \ + CONFIG.PSU__USE__GDMA {0} \ + CONFIG.PSU__USE__IRQ {0} \ + CONFIG.PSU__USE__IRQ0 {1} \ + CONFIG.PSU__USE__IRQ1 {0} \ + CONFIG.PSU__USE__CLK0 {0} \ + CONFIG.PSU__USE__CLK1 {0} \ + CONFIG.PSU__USE__CLK2 {0} \ + CONFIG.PSU__USE__CLK3 {0} \ + CONFIG.PSU__USE__RST0 {0} \ + CONFIG.PSU__USE__RST1 {0} \ + CONFIG.PSU__USE__RST2 {0} \ + CONFIG.PSU__USE__RST3 {0} \ + CONFIG.PSU__USE__FABRIC__RST {1} \ + CONFIG.PSU__USE__RTC {0} \ + CONFIG.PSU__PRESET_APPLIED {1} \ + CONFIG.PSU__USE__EVENT_RPU {0} \ + CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \ + CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \ + CONFIG.PSU__USE__STM {0} \ + CONFIG.PSU__USE__DEBUG__TEST {0} \ + CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \ + CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ + CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \ + CONFIG.PSU__EXPAND__CORESIGHT {0} \ + CONFIG.PSU__EXPAND__GIC {0} \ + CONFIG.PSU__EXPAND__FPD_SLAVES {0} \ + CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \ + CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_0_POLARITY {Default} \ + CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_0_SLEW {fast} \ + CONFIG.PSU_MIO_0_DIRECTION {out} \ + CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_1_POLARITY {Default} \ + CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_1_SLEW {fast} \ + CONFIG.PSU_MIO_1_DIRECTION {inout} \ + CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_2_POLARITY {Default} \ + CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_2_SLEW {fast} \ + CONFIG.PSU_MIO_2_DIRECTION {inout} \ + CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_3_POLARITY {Default} \ + CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_3_SLEW {fast} \ + CONFIG.PSU_MIO_3_DIRECTION {inout} \ + CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_4_POLARITY {Default} \ + CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_4_SLEW {fast} \ + CONFIG.PSU_MIO_4_DIRECTION {inout} \ + CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_5_POLARITY {Default} \ + CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_5_SLEW {fast} \ + CONFIG.PSU_MIO_5_DIRECTION {out} \ + CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_6_POLARITY {Default} \ + CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_6_SLEW {fast} \ + CONFIG.PSU_MIO_6_DIRECTION {inout} \ + CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_7_POLARITY {Default} \ + CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_7_SLEW {fast} \ + CONFIG.PSU_MIO_7_DIRECTION {out} \ + CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_8_POLARITY {Default} \ + CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_8_SLEW {fast} \ + CONFIG.PSU_MIO_8_DIRECTION {inout} \ + CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_9_POLARITY {Default} \ + CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_9_SLEW {fast} \ + CONFIG.PSU_MIO_9_DIRECTION {inout} \ + CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_10_POLARITY {Default} \ + CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_10_SLEW {fast} \ + CONFIG.PSU_MIO_10_DIRECTION {inout} \ + CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_11_POLARITY {Default} \ + CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_11_SLEW {fast} \ + CONFIG.PSU_MIO_11_DIRECTION {inout} \ + CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_12_POLARITY {Default} \ + CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_12_SLEW {fast} \ + CONFIG.PSU_MIO_12_DIRECTION {out} \ + CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_13_POLARITY {Default} \ + CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_13_SLEW {fast} \ + CONFIG.PSU_MIO_13_DIRECTION {inout} \ + CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_14_POLARITY {Default} \ + CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_14_SLEW {fast} \ + CONFIG.PSU_MIO_14_DIRECTION {inout} \ + CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_15_POLARITY {Default} \ + CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_15_SLEW {fast} \ + CONFIG.PSU_MIO_15_DIRECTION {inout} \ + CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_16_POLARITY {Default} \ + CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_16_SLEW {fast} \ + CONFIG.PSU_MIO_16_DIRECTION {inout} \ + CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_17_POLARITY {Default} \ + CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_17_SLEW {fast} \ + CONFIG.PSU_MIO_17_DIRECTION {inout} \ + CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_18_POLARITY {Default} \ + CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_18_SLEW {fast} \ + CONFIG.PSU_MIO_18_DIRECTION {in} \ + CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_19_POLARITY {Default} \ + CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_19_SLEW {fast} \ + CONFIG.PSU_MIO_19_DIRECTION {out} \ + CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_20_POLARITY {Default} \ + CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_20_SLEW {fast} \ + CONFIG.PSU_MIO_20_DIRECTION {out} \ + CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_21_POLARITY {Default} \ + CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_21_SLEW {fast} \ + CONFIG.PSU_MIO_21_DIRECTION {in} \ + CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_22_POLARITY {Default} \ + CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_22_SLEW {fast} \ + CONFIG.PSU_MIO_22_DIRECTION {inout} \ + CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_23_POLARITY {Default} \ + CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_23_SLEW {fast} \ + CONFIG.PSU_MIO_23_DIRECTION {inout} \ + CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_24_POLARITY {Default} \ + CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_24_SLEW {fast} \ + CONFIG.PSU_MIO_24_DIRECTION {inout} \ + CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_25_POLARITY {Default} \ + CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_25_SLEW {fast} \ + CONFIG.PSU_MIO_25_DIRECTION {inout} \ + CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_26_POLARITY {Default} \ + CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_26_SLEW {fast} \ + CONFIG.PSU_MIO_26_DIRECTION {in} \ + CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_27_POLARITY {Default} \ + CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_27_SLEW {fast} \ + CONFIG.PSU_MIO_27_DIRECTION {in} \ + CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_28_POLARITY {Default} \ + CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_28_SLEW {fast} \ + CONFIG.PSU_MIO_28_DIRECTION {in} \ + CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_29_POLARITY {Default} \ + CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_29_SLEW {fast} \ + CONFIG.PSU_MIO_29_DIRECTION {in} \ + CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_30_POLARITY {Default} \ + CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_30_SLEW {fast} \ + CONFIG.PSU_MIO_30_DIRECTION {in} \ + CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_31_POLARITY {Default} \ + CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_31_SLEW {fast} \ + CONFIG.PSU_MIO_31_DIRECTION {in} \ + CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_32_POLARITY {Default} \ + CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_32_SLEW {fast} \ + CONFIG.PSU_MIO_32_DIRECTION {out} \ + CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_33_POLARITY {Default} \ + CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_33_SLEW {fast} \ + CONFIG.PSU_MIO_33_DIRECTION {out} \ + CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_34_POLARITY {Default} \ + CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_34_SLEW {fast} \ + CONFIG.PSU_MIO_34_DIRECTION {out} \ + CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_35_POLARITY {Default} \ + CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_35_SLEW {fast} \ + CONFIG.PSU_MIO_35_DIRECTION {in} \ + CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_36_POLARITY {Default} \ + CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_36_SLEW {fast} \ + CONFIG.PSU_MIO_36_DIRECTION {out} \ + CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_37_POLARITY {Default} \ + CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_37_SLEW {fast} \ + CONFIG.PSU_MIO_37_DIRECTION {in} \ + CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_38_POLARITY {Default} \ + CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_38_SLEW {fast} \ + CONFIG.PSU_MIO_38_DIRECTION {inout} \ + CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_39_POLARITY {Default} \ + CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_39_SLEW {fast} \ + CONFIG.PSU_MIO_39_DIRECTION {inout} \ + CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_40_POLARITY {Default} \ + CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_40_SLEW {fast} \ + CONFIG.PSU_MIO_40_DIRECTION {inout} \ + CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_41_POLARITY {Default} \ + CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_41_SLEW {fast} \ + CONFIG.PSU_MIO_41_DIRECTION {inout} \ + CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_42_POLARITY {Default} \ + CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_42_SLEW {fast} \ + CONFIG.PSU_MIO_42_DIRECTION {inout} \ + CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_43_POLARITY {Default} \ + CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_43_SLEW {fast} \ + CONFIG.PSU_MIO_43_DIRECTION {inout} \ + CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_44_POLARITY {Default} \ + CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_44_SLEW {fast} \ + CONFIG.PSU_MIO_44_DIRECTION {inout} \ + CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_45_POLARITY {Default} \ + CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_45_SLEW {fast} \ + CONFIG.PSU_MIO_45_DIRECTION {in} \ + CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_46_POLARITY {Default} \ + CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_46_SLEW {fast} \ + CONFIG.PSU_MIO_46_DIRECTION {inout} \ + CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_47_POLARITY {Default} \ + CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_47_SLEW {fast} \ + CONFIG.PSU_MIO_47_DIRECTION {inout} \ + CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_48_POLARITY {Default} \ + CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_48_SLEW {fast} \ + CONFIG.PSU_MIO_48_DIRECTION {inout} \ + CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_49_POLARITY {Default} \ + CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_49_SLEW {fast} \ + CONFIG.PSU_MIO_49_DIRECTION {inout} \ + CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_50_POLARITY {Default} \ + CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_50_SLEW {fast} \ + CONFIG.PSU_MIO_50_DIRECTION {inout} \ + CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_51_POLARITY {Default} \ + CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_51_SLEW {fast} \ + CONFIG.PSU_MIO_51_DIRECTION {out} \ + CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_52_POLARITY {Default} \ + CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_52_SLEW {fast} \ + CONFIG.PSU_MIO_52_DIRECTION {in} \ + CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_53_POLARITY {Default} \ + CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_53_SLEW {fast} \ + CONFIG.PSU_MIO_53_DIRECTION {in} \ + CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_54_POLARITY {Default} \ + CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_54_SLEW {fast} \ + CONFIG.PSU_MIO_54_DIRECTION {inout} \ + CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_55_POLARITY {Default} \ + CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_55_SLEW {fast} \ + CONFIG.PSU_MIO_55_DIRECTION {in} \ + CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_56_POLARITY {Default} \ + CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_56_SLEW {fast} \ + CONFIG.PSU_MIO_56_DIRECTION {inout} \ + CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_57_POLARITY {Default} \ + CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_57_SLEW {fast} \ + CONFIG.PSU_MIO_57_DIRECTION {inout} \ + CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_58_POLARITY {Default} \ + CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_58_SLEW {fast} \ + CONFIG.PSU_MIO_58_DIRECTION {out} \ + CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_59_POLARITY {Default} \ + CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_59_SLEW {fast} \ + CONFIG.PSU_MIO_59_DIRECTION {inout} \ + CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_60_POLARITY {Default} \ + CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_60_SLEW {fast} \ + CONFIG.PSU_MIO_60_DIRECTION {inout} \ + CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_61_POLARITY {Default} \ + CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_61_SLEW {fast} \ + CONFIG.PSU_MIO_61_DIRECTION {inout} \ + CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_62_POLARITY {Default} \ + CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_62_SLEW {fast} \ + CONFIG.PSU_MIO_62_DIRECTION {inout} \ + CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_63_POLARITY {Default} \ + CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_63_SLEW {fast} \ + CONFIG.PSU_MIO_63_DIRECTION {inout} \ + CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_64_POLARITY {Default} \ + CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_64_SLEW {fast} \ + CONFIG.PSU_MIO_64_DIRECTION {out} \ + CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_65_POLARITY {Default} \ + CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_65_SLEW {fast} \ + CONFIG.PSU_MIO_65_DIRECTION {out} \ + CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_66_POLARITY {Default} \ + CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_66_SLEW {fast} \ + CONFIG.PSU_MIO_66_DIRECTION {out} \ + CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_67_POLARITY {Default} \ + CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_67_SLEW {fast} \ + CONFIG.PSU_MIO_67_DIRECTION {out} \ + CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_68_POLARITY {Default} \ + CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_68_SLEW {fast} \ + CONFIG.PSU_MIO_68_DIRECTION {out} \ + CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_69_POLARITY {Default} \ + CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_69_SLEW {fast} \ + CONFIG.PSU_MIO_69_DIRECTION {out} \ + CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_70_POLARITY {Default} \ + CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_70_SLEW {fast} \ + CONFIG.PSU_MIO_70_DIRECTION {in} \ + CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_71_POLARITY {Default} \ + CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_71_SLEW {fast} \ + CONFIG.PSU_MIO_71_DIRECTION {in} \ + CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_72_POLARITY {Default} \ + CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_72_SLEW {fast} \ + CONFIG.PSU_MIO_72_DIRECTION {in} \ + CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_73_POLARITY {Default} \ + CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_73_SLEW {fast} \ + CONFIG.PSU_MIO_73_DIRECTION {in} \ + CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_74_POLARITY {Default} \ + CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_74_SLEW {fast} \ + CONFIG.PSU_MIO_74_DIRECTION {in} \ + CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_75_POLARITY {Default} \ + CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_75_SLEW {fast} \ + CONFIG.PSU_MIO_75_DIRECTION {in} \ + CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_76_POLARITY {Default} \ + CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_76_SLEW {fast} \ + CONFIG.PSU_MIO_76_DIRECTION {out} \ + CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_77_POLARITY {Default} \ + CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_77_SLEW {fast} \ + CONFIG.PSU_MIO_77_DIRECTION {inout} \ + CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {63} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \ + CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ + CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ + CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \ + CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SATA__LANE0__ENABLE {0} \ + CONFIG.PSU__SATA__LANE1__ENABLE {1} \ + CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ + CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ + CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__USE__CLK {0} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \ + CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ + CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \ + CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ + CONFIG.PSU__DLL__ISUSED {1} \ + CONFIG.PSU__PL_CLK0_BUF {TRUE} \ + CONFIG.PSU__PL_CLK1_BUF {FALSE} \ + CONFIG.PSU__PL_CLK2_BUF {FALSE} \ + CONFIG.PSU__PL_CLK3_BUF {FALSE} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.988037} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {299.997009} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.999750} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785446} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {524.994751} \ + CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.000} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {0} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {524.994751} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.998749} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.998749} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.498123} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {199.998001} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.994995} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.498123} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.994995} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.994995} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.984985} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999500} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999800} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1066} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ + CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {99.999001} \ + CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {99.999001} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \ + CONFIG.PSU__GEN_IPI_0__MASTER {APU} \ + CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \ + CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \ + CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \ + CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_NAND__INT {0} \ + CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \ + CONFIG.PSU__IRQ_P2F_SPI0__INT {0} \ + CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \ + CONFIG.PSU__IRQ_P2F_UART0__INT {0} \ + CONFIG.PSU__IRQ_P2F_UART1__INT {0} \ + CONFIG.PSU__IRQ_P2F_CAN0__INT {0} \ + CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \ + CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_SDIO0__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO0_WAKE__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \ + CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \ + CONFIG.PSU__IRQ_P2F_AMS__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT0__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT0_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT1__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT1_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT2__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT2_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSU__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSU_DMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \ + CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPU__INT {0} \ + CONFIG.PSU__IRQ_P2F_SATA__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \ + CONFIG.PSU__NUM_FABRIC_RESETS {1} \ + CONFIG.PSU__GPIO_EMIO_WIDTH {1} \ + CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__TRISTATE__INVERTED {1} \ + CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \ + CONFIG.PSU__REPORT__DBGLOG {0} \ + CONFIG.IIC0_BOARD_INTERFACE {custom} \ + CONFIG.IIC1_BOARD_INTERFACE {custom} \ + CONFIG.QSPI_BOARD_INTERFACE {custom} \ + CONFIG.NAND_BOARD_INTERFACE {custom} \ + CONFIG.SD0_BOARD_INTERFACE {custom} \ + CONFIG.SD1_BOARD_INTERFACE {custom} \ + CONFIG.CAN0_BOARD_INTERFACE {custom} \ + CONFIG.CAN1_BOARD_INTERFACE {custom} \ + CONFIG.PJTAG_BOARD_INTERFACE {custom} \ + CONFIG.PMU_BOARD_INTERFACE {custom} \ + CONFIG.CSU_BOARD_INTERFACE {custom} \ + CONFIG.SPI0_BOARD_INTERFACE {custom} \ + CONFIG.SPI1_BOARD_INTERFACE {custom} \ + CONFIG.UART0_BOARD_INTERFACE {custom} \ + CONFIG.UART1_BOARD_INTERFACE {custom} \ + CONFIG.GPIO_BOARD_INTERFACE {custom} \ + CONFIG.SWDT0_BOARD_INTERFACE {custom} \ + CONFIG.SWDT1_BOARD_INTERFACE {custom} \ + CONFIG.TRACE_BOARD_INTERFACE {custom} \ + CONFIG.TTC0_BOARD_INTERFACE {custom} \ + CONFIG.TTC1_BOARD_INTERFACE {custom} \ + CONFIG.TTC2_BOARD_INTERFACE {custom} \ + CONFIG.TTC3_BOARD_INTERFACE {custom} \ + CONFIG.GEM0_BOARD_INTERFACE {custom} \ + CONFIG.GEM1_BOARD_INTERFACE {custom} \ + CONFIG.GEM2_BOARD_INTERFACE {custom} \ + CONFIG.GEM3_BOARD_INTERFACE {custom} \ + CONFIG.USB0_BOARD_INTERFACE {custom} \ + CONFIG.USB1_BOARD_INTERFACE {custom} \ + CONFIG.PCIE_BOARD_INTERFACE {custom} \ + CONFIG.DP_BOARD_INTERFACE {custom} \ + CONFIG.SATA_BOARD_INTERFACE {custom} \ + CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__NAND_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__RPU_COHERENCY {0} \ + CONFIG.PSU__PMU_COHERENCY {0} \ + CONFIG.PSU__CSU_COHERENCY {0} \ + CONFIG.PSU__USB0_COHERENCY {0} \ + CONFIG.PSU__USB1_COHERENCY {0} \ + CONFIG.PSU__LPDMA0_COHERENCY {0} \ + CONFIG.PSU__LPDMA1_COHERENCY {0} \ + CONFIG.PSU__LPDMA2_COHERENCY {0} \ + CONFIG.PSU__LPDMA3_COHERENCY {0} \ + CONFIG.PSU__LPDMA4_COHERENCY {0} \ + CONFIG.PSU__LPDMA5_COHERENCY {0} \ + CONFIG.PSU__LPDMA6_COHERENCY {0} \ + CONFIG.PSU__LPDMA7_COHERENCY {0} \ + CONFIG.PSU__SD0_COHERENCY {0} \ + CONFIG.PSU__SD1_COHERENCY {0} \ + CONFIG.PSU__NAND_COHERENCY {0} \ + CONFIG.PSU__QSPI_COHERENCY {0} \ + CONFIG.PSU__ENET0__TSU__ENABLE {0} \ + CONFIG.PSU__ENET1__TSU__ENABLE {0} \ + CONFIG.PSU__ENET2__TSU__ENABLE {0} \ + CONFIG.PSU__ENET3__TSU__ENABLE {0} \ + CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ + CONFIG.PSU__GEM0_COHERENCY {0} \ + CONFIG.PSU__GEM1_COHERENCY {0} \ + CONFIG.PSU__GEM2_COHERENCY {0} \ + CONFIG.PSU__GEM3_COHERENCY {0} \ + CONFIG.PSU__AFI0_COHERENCY {0} \ + CONFIG.PSU__AFI1_COHERENCY {0} \ + CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ + CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \ + CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ + ] +} + +