2 Commits
Author SHA1 Message Date
josh 9ac4c532f3 add dj_47dr_z7045 vitis fsbl project
boot image is created, and start-up test is passed
2024-07-02 14:13:03 +08:00
josh 3aac7f01b6 add dj_47dr_z7045 ibert project
ibert line rate 9.6 Gbps, refclk 150 MHz
2024-07-02 14:10:41 +08:00