 josh
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9ac4c532f3
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add dj_47dr_z7045 vitis fsbl project
boot image is created, and start-up test is passed
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2024-07-02 14:13:03 +08:00 |
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josh
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3aac7f01b6
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add dj_47dr_z7045 ibert project
ibert line rate 9.6 Gbps, refclk 150 MHz
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2024-07-02 14:10:41 +08:00 |
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josh
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47a1b38997
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update dj_47dr ps project, add tcp performance server project
refer to readme.md for details
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2024-07-01 19:27:23 +08:00 |
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josh
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0dcb823314
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add ax7020 pl project, including mpsoc bd core only
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2024-07-01 19:26:17 +08:00 |
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josh
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66f574fef7
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update dj_47dr pl, add ttc to mpsoc bd core
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2024-07-01 19:14:06 +08:00 |
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josh
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6a4af4fb55
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add rfsoc_eval vitis project, refer to readme for details
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2024-07-01 14:31:21 +08:00 |
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josh
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fad0306d82
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add rfsoc_eval pl project
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2024-06-29 00:11:59 +08:00 |
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josh
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cec690b984
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add dj_47dr vitis projects, refer to readme within each project for details
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2024-06-28 23:06:09 +08:00 |
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josh
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0eead518df
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add dj_47dr pl project, set .dcp as large file type
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2024-06-28 22:24:04 +08:00 |
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josh
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8c68cb519e
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add xilinx spi examlpe with ax7020
refer to projects/ax7020/ax7020_spi_loopback/README.md for detailed information
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2024-01-24 20:14:55 +08:00 |
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