Compare commits
4
Commits
118ade226e
...
3c6c573f6a
| Author | SHA1 | Date | |
|---|---|---|---|
 josh
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3c6c573f6a | ||
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josh
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a1680685ed | ||
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josh
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9eea2b693a | ||
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josh
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5defedcc88 |
+479
@@ -0,0 +1,479 @@
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{
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"schema": "xilinx.com:schema:json_instance:1.0",
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"ip_inst": {
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"xci_name": "ad9361_fifo",
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"component_reference": "xilinx.com:ip:fifo_generator:13.2",
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"ip_revision": "9",
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"gen_directory": "../../../../ad9361_mapping.gen/sources_1/ip/ad9361_fifo",
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"parameters": {
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"component_parameters": {
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"Component_Name": [ { "value": "ad9361_fifo", "resolve_type": "user", "usage": "all" } ],
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"Fifo_Implementation": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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"synchronization_stages": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
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"Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
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"asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Input_Data_Width": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"Input_Depth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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"Output_Data_Width": [ { "value": "12", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Output_Depth": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||||
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"Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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||||||
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"Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Reset_Type": [ { "value": "Asynchronous_Reset", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Full_Flags_Reset_Value": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
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"Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
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"dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Data_Count_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Write_Data_Count_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Read_Data_Count_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
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"Full_Threshold_Assert_Value": [ { "value": "13", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"Full_Threshold_Negate_Value": [ { "value": "12", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
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"Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
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"HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
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"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
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"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
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"FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
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"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||||
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"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||||
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"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
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"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||||
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"Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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||||||
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"Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
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"FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
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"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
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"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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||||||
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"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
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"FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
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"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
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"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
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"FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
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"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||||
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"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||||
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"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||||
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"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
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||||||
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"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
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"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
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"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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||||||
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"Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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||||||
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"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
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||||||
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"FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
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||||||
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"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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||||||
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"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
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"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
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"Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
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"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||||
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"Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
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"Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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||||||
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"Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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||||||
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"Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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||||||
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"Empty_Threshold_Assert_Value_rdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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||||||
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"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
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"FIFO_Implementation_axis": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
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||||||
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"FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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||||||
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"Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
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"Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||||
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"Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
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"Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||||
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"Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
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"Programmable_Full_Type_axis": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
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"Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
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"Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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||||||
|
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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"Enable_ECC_Type": [ { "value": "Hard_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
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"C_SELECT_XPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
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||||||
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"C_SELECT_XPM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_COUNT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_DATA_COUNT_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_DEFAULT_VALUE": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
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||||||
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"C_DIN_WIDTH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_DOUT_RST_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
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||||||
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"C_DOUT_WIDTH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_ENABLE_RLOCS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_FAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
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||||||
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||||||
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||||||
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"C_HAS_ALMOST_FULL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_HAS_BACKUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_HAS_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_HAS_INT_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_HAS_MEMINIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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||||||
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"C_HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_HAS_RD_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_HAS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_HAS_SRST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_HAS_UNDERFLOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_HAS_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_HAS_WR_ACK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_HAS_WR_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_IMPLEMENTATION_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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||||||
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"C_MEMORY_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_MIF_FILE_NAME": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
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||||||
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||||||
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"C_OVERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_PRELOAD_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
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"C_PRELOAD_REGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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"C_PRIM_FIFO_TYPE": [ { "value": "512x36", "resolve_type": "generated", "usage": "all" } ],
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||||||
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||||||
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"C_PROG_EMPTY_THRESH_NEGATE_VAL": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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||||||
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||||||
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||||||
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"C_PROG_FULL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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||||||
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"C_RD_DEPTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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||||||
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||||||
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|
||||||
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"C_USE_DOUT_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
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"C_USE_EMBEDDED_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
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"C_USE_PIPELINE_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
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||||||
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|
||||||
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|
||||||
|
"C_VALID_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
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"C_WR_ACK_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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|
||||||
|
"C_WR_DEPTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WR_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
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|
||||||
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|
||||||
|
"C_MSGON_VAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_RST_SYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ERROR_INJECTION_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||||
|
"C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_AXI_WR_CHANNEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_AXI_RD_CHANNEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_SLAVE_CE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_MASTER_CE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ADD_NGC_CONSTRAINT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_LEN_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_LOCK_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_AXI_AWUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_AXI_WUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_AXI_BUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_AXI_ARUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_AXI_RUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
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|
||||||
|
"C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"C_HAS_AXIS_TUSER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_AXIS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
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|
||||||
|
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|
||||||
|
"C_HAS_AXIS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXIS_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
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|
||||||
|
"C_AXIS_TUSER_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
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|
||||||
|
"C_AXIS_TKEEP_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"C_APPLICATION_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_APPLICATION_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PRIM_FIFO_TYPE_WACH": [ { "value": "512x36", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PRIM_FIFO_TYPE_WDCH": [ { "value": "1kx36", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PRIM_FIFO_TYPE_WRCH": [ { "value": "512x36", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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||||||
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||||||
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||||||
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||||||
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||||||
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|
||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
|
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||||||
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|
||||||
|
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|
||||||
|
"C_WR_DEPTH_RDCH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
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||||||
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||||||
|
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|
||||||
|
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|
||||||
|
"C_WR_PNTR_WIDTH_RACH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WR_PNTR_WIDTH_RDCH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
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|
||||||
|
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||||||
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||||||
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|
||||||
|
"C_HAS_DATA_COUNTS_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_DATA_COUNTS_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_DATA_COUNTS_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_PROG_FLAGS_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_PROG_FLAGS_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_PROG_FLAGS_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_PROG_FLAGS_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_PROG_FLAGS_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_PROG_FLAGS_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_THRESH_ASSERT_VAL_WACH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_THRESH_ASSERT_VAL_WDCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_THRESH_ASSERT_VAL_WRCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_THRESH_ASSERT_VAL_RACH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_THRESH_ASSERT_VAL_RDCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_THRESH_ASSERT_VAL_AXIS": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_REG_SLICE_MODE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_REG_SLICE_MODE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_REG_SLICE_MODE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_REG_SLICE_MODE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_REG_SLICE_MODE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_REG_SLICE_MODE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "kintex7" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xc7k410t" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffg900" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||||
|
"IPREVISION": [ { "value": "9" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../ad9361_mapping.gen/sources_1/ip/ad9361_fifo" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "." } ],
|
||||||
|
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"rst": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"wr_clk": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"rd_clk": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"din": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"wr_en": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"rd_en": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"dout": [ { "direction": "out", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"full": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||||
|
"empty": [ { "direction": "out", "driver_value": "0x1" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"write_clk": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "wr_clk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"read_clk": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "rd_clk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"FIFO_WRITE": {
|
||||||
|
"vlnv": "xilinx.com:interface:fifo_write:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:fifo_write_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"port_maps": {
|
||||||
|
"FULL": [ { "physical_name": "full" } ],
|
||||||
|
"WR_DATA": [ { "physical_name": "din" } ],
|
||||||
|
"WR_EN": [ { "physical_name": "wr_en" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"FIFO_READ": {
|
||||||
|
"vlnv": "xilinx.com:interface:fifo_read:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:fifo_read_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"port_maps": {
|
||||||
|
"EMPTY": [ { "physical_name": "empty" } ],
|
||||||
|
"RD_DATA": [ { "physical_name": "dout" } ],
|
||||||
|
"RD_EN": [ { "physical_name": "rd_en" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
+196
@@ -0,0 +1,196 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Company:
|
||||||
|
// Engineer:
|
||||||
|
// _ _ ____
|
||||||
|
// | | ___ ___| |__ / ___| __ _ ___
|
||||||
|
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||||
|
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||||
|
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||||
|
//
|
||||||
|
// Create Date: 2022/07/01 17:37:27
|
||||||
|
// Last Modified Date: 2023/03/06 11:26
|
||||||
|
// Design Name:
|
||||||
|
// Module Name: ad9361_rx_map_cmos_dual
|
||||||
|
// Project Name:
|
||||||
|
// Target Devices:
|
||||||
|
// Tool Versions:
|
||||||
|
// Description:
|
||||||
|
//
|
||||||
|
// Dependencies:
|
||||||
|
//
|
||||||
|
// Revision:
|
||||||
|
// Revision 0.01 - File Created
|
||||||
|
// Additional Comments:
|
||||||
|
//
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
|
module ad9361_rx_map_cmos_dual
|
||||||
|
(
|
||||||
|
input clk_2x_in ,
|
||||||
|
input clk_in_rst ,
|
||||||
|
|
||||||
|
input rx_data_clk , // sync to output data
|
||||||
|
input rx_data_clk_rst ,
|
||||||
|
|
||||||
|
input rx_fifo_rst , // async fifo reset
|
||||||
|
|
||||||
|
input rx_frame ,
|
||||||
|
input [11:0] rx_data ,
|
||||||
|
|
||||||
|
output [11:0] rx_ch1_i ,
|
||||||
|
output [11:0] rx_ch1_q ,
|
||||||
|
output [11:0] rx_ch2_i ,
|
||||||
|
output [11:0] rx_ch2_q
|
||||||
|
);
|
||||||
|
|
||||||
|
genvar m;
|
||||||
|
|
||||||
|
// rx data
|
||||||
|
wire [11:0] rx_data_i, rx_data_q;
|
||||||
|
|
||||||
|
generate
|
||||||
|
for (m=0; m<12; m=m+1) begin : rx_data_iddr
|
||||||
|
|
||||||
|
IDDR #(
|
||||||
|
.DDR_CLK_EDGE ("SAME_EDGE" ),
|
||||||
|
.INIT_Q1 (1'b0 ),
|
||||||
|
.INIT_Q2 (1'b0 ),
|
||||||
|
.SRTYPE ("ASYNC" )
|
||||||
|
) i_rx_data_iddr (
|
||||||
|
.CE (1'b1 ),
|
||||||
|
.R (1'b0 ),
|
||||||
|
.S (1'b0 ),
|
||||||
|
.C (clk_2x_in ),
|
||||||
|
.D (rx_data[m] ),
|
||||||
|
.Q1 (rx_data_q[m] ),
|
||||||
|
.Q2 (rx_data_i[m] )
|
||||||
|
);
|
||||||
|
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
// rx frame
|
||||||
|
wire rx_frame_i;
|
||||||
|
wire rx_frame_q;
|
||||||
|
|
||||||
|
IDDR #(
|
||||||
|
.DDR_CLK_EDGE ("SAME_EDGE" ),
|
||||||
|
.INIT_Q1 (1'b0 ),
|
||||||
|
.INIT_Q2 (1'b0 ),
|
||||||
|
.SRTYPE ("ASYNC" )
|
||||||
|
) i_rx_frame_iddr (
|
||||||
|
.CE (1'b1 ),
|
||||||
|
.R (1'b0 ),
|
||||||
|
.S (1'b0 ),
|
||||||
|
.C (clk_2x_in ),
|
||||||
|
.D (rx_frame ),
|
||||||
|
.Q1 (rx_frame_q ),
|
||||||
|
.Q2 (rx_frame_i )
|
||||||
|
);
|
||||||
|
|
||||||
|
// divide rx_data to dual channel
|
||||||
|
reg [11:0] rx1_data_i = 'b0;
|
||||||
|
reg [11:0] rx1_data_q = 'b0;
|
||||||
|
reg [11:0] rx2_data_i = 'b0;
|
||||||
|
reg [11:0] rx2_data_q = 'b0;
|
||||||
|
|
||||||
|
wire rx_fifo_wr_en;
|
||||||
|
reg rx_fifo_rd_en = 'b0;
|
||||||
|
|
||||||
|
wire rx_fifo_empty_1;
|
||||||
|
wire rx_fifo_empty_2;
|
||||||
|
wire rx_fifo_empty_3;
|
||||||
|
wire rx_fifo_empty_4;
|
||||||
|
|
||||||
|
assign rx_fifo_wr_en = rx_frame_i; // align data & write enable
|
||||||
|
|
||||||
|
always @ (posedge clk_2x_in) begin
|
||||||
|
if (clk_in_rst) begin
|
||||||
|
rx1_data_i <= 'b0;
|
||||||
|
rx2_data_i <= 'b0;
|
||||||
|
end
|
||||||
|
else if(rx_frame_i) begin
|
||||||
|
rx1_data_i <= rx_data_i;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
rx2_data_i <= rx_data_i;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @ (posedge clk_2x_in) begin
|
||||||
|
if (clk_in_rst) begin
|
||||||
|
rx1_data_q <= 'b0;
|
||||||
|
rx2_data_q <= 'b0;
|
||||||
|
end
|
||||||
|
else if(rx_frame_q) begin
|
||||||
|
rx1_data_q <= rx_data_q;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
rx2_data_q <= rx_data_q;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge rx_data_clk) begin
|
||||||
|
if (rx_data_clk_rst) begin
|
||||||
|
rx_fifo_rd_en <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4};
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
ad9361_fifo u_rx_fifo_ch1_i
|
||||||
|
(
|
||||||
|
.rst (rx_fifo_rst ), // input wire rst
|
||||||
|
.wr_clk (clk_2x_in ), // input wire wr_clk
|
||||||
|
.rd_clk (rx_data_clk ), // input wire rd_clk
|
||||||
|
.din (rx1_data_i ), // input wire [11 : 0] din
|
||||||
|
.wr_en (rx_fifo_wr_en ), // input wire wr_en
|
||||||
|
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||||
|
.dout (rx_ch1_i ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty (rx_fifo_empty_1) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
ad9361_fifo u_rx_fifo_ch1_q
|
||||||
|
(
|
||||||
|
.rst (rx_fifo_rst ), // input wire rst
|
||||||
|
.wr_clk (clk_2x_in ), // input wire wr_clk
|
||||||
|
.rd_clk (rx_data_clk ), // input wire rd_clk
|
||||||
|
.din (rx1_data_q ), // input wire [11 : 0] din
|
||||||
|
.wr_en (rx_fifo_wr_en ), // input wire wr_en
|
||||||
|
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||||
|
.dout (rx_ch1_q ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty (rx_fifo_empty_2) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
ad9361_fifo u_rx_fifo_ch2_i
|
||||||
|
(
|
||||||
|
.rst (rx_fifo_rst ), // input wire rst
|
||||||
|
.wr_clk (clk_2x_in ), // input wire wr_clk
|
||||||
|
.rd_clk (rx_data_clk ), // input wire rd_clk
|
||||||
|
.din (rx2_data_i ), // input wire [11 : 0] din
|
||||||
|
.wr_en (rx_fifo_wr_en ), // input wire wr_en
|
||||||
|
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||||
|
.dout (rx_ch2_i ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty (rx_fifo_empty_3) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
ad9361_fifo u_rx_fifo_ch2_q
|
||||||
|
(
|
||||||
|
.rst (rx_fifo_rst ), // input wire rst
|
||||||
|
.wr_clk (clk_2x_in ), // input wire wr_clk
|
||||||
|
.rd_clk (rx_data_clk ), // input wire rd_clk
|
||||||
|
.din (rx2_data_q ), // input wire [11 : 0] din
|
||||||
|
.wr_en (rx_fifo_wr_en ), // input wire wr_en
|
||||||
|
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||||
|
.dout (rx_ch2_q ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty (rx_fifo_empty_4) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
+124
@@ -0,0 +1,124 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Company:
|
||||||
|
// Engineer:
|
||||||
|
// _ _ ____
|
||||||
|
// | | ___ ___| |__ / ___| __ _ ___
|
||||||
|
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||||
|
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||||
|
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||||
|
//
|
||||||
|
// Create Date: 2022/07/01 17:37:27
|
||||||
|
// Last Modified Date: 2023/03/03 13:01
|
||||||
|
// Design Name:
|
||||||
|
// Module Name: ad9361_rx_map_cmos_single
|
||||||
|
// Project Name:
|
||||||
|
// Target Devices:
|
||||||
|
// Tool Versions:
|
||||||
|
// Description:
|
||||||
|
//
|
||||||
|
// Dependencies:
|
||||||
|
//
|
||||||
|
// Revision:
|
||||||
|
// Revision 0.01 - File Created
|
||||||
|
// Additional Comments:
|
||||||
|
//
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
|
module ad9361_rx_map_cmos_single
|
||||||
|
(
|
||||||
|
input clk_in ,
|
||||||
|
input clk_in_rst ,
|
||||||
|
|
||||||
|
input rx_data_clk ,
|
||||||
|
input rx_data_clk_rst ,
|
||||||
|
|
||||||
|
input rx_fifo_rst ,
|
||||||
|
|
||||||
|
input rx_frame ,
|
||||||
|
input [11:0] rx_data ,
|
||||||
|
|
||||||
|
output [11:0] rx_data_i ,
|
||||||
|
output [11:0] rx_data_q
|
||||||
|
);
|
||||||
|
|
||||||
|
genvar m;
|
||||||
|
|
||||||
|
// rx data
|
||||||
|
wire [11:0] rx_raw_i, rx_raw_q;
|
||||||
|
|
||||||
|
generate
|
||||||
|
for (m=0; m<12; m=m+1) begin : rx_data_iddr
|
||||||
|
|
||||||
|
IDDR #(
|
||||||
|
.DDR_CLK_EDGE ("SAME_EDGE" ),
|
||||||
|
.INIT_Q1 (1'b0 ),
|
||||||
|
.INIT_Q2 (1'b0 ),
|
||||||
|
.SRTYPE ("ASYNC" )
|
||||||
|
) i_rx_data_iddr (
|
||||||
|
.CE (1'b1 ),
|
||||||
|
.R (1'b0 ),
|
||||||
|
.S (1'b0 ),
|
||||||
|
.C (clk_in ),
|
||||||
|
.D (rx_data[m] ),
|
||||||
|
.Q1 (rx_raw_q[m] ),
|
||||||
|
.Q2 (rx_raw_i[m] )
|
||||||
|
);
|
||||||
|
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
|
||||||
|
// divide rx_data to dual channel
|
||||||
|
reg rx_fifo_wr_en = 1'b0;
|
||||||
|
reg rx_fifo_rd_en = 'b0;
|
||||||
|
|
||||||
|
wire rx_fifo_empty_1;
|
||||||
|
wire rx_fifo_empty_2;
|
||||||
|
|
||||||
|
always @(posedge clk_in) begin
|
||||||
|
if (clk_in_rst) begin
|
||||||
|
rx_fifo_wr_en <= 1'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
rx_fifo_wr_en <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge rx_data_clk) begin
|
||||||
|
if (rx_data_clk_rst) begin
|
||||||
|
rx_fifo_rd_en <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2};
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
ad9361_fifo u_rx_fifo_i
|
||||||
|
(
|
||||||
|
.rst (rx_fifo_rst ), // input wire rst
|
||||||
|
.wr_clk (clk_in ), // input wire wr_clk
|
||||||
|
.rd_clk (rx_data_clk ), // input wire rd_clk
|
||||||
|
.din (rx_raw_i ), // input wire [11 : 0] din
|
||||||
|
.wr_en (rx_fifo_wr_en ), // input wire wr_en
|
||||||
|
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||||
|
.dout (rx_data_i ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty (rx_fifo_empty_1) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
ad9361_fifo u_rx_fifo_q
|
||||||
|
(
|
||||||
|
.rst (rx_fifo_rst ), // input wire rst
|
||||||
|
.wr_clk (clk_in ), // input wire wr_clk
|
||||||
|
.rd_clk (rx_data_clk ), // input wire rd_clk
|
||||||
|
.din (rx_raw_q ), // input wire [11 : 0] din
|
||||||
|
.wr_en (rx_fifo_wr_en ), // input wire wr_en
|
||||||
|
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||||
|
.dout (rx_data_q ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty (rx_fifo_empty_2) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
+277
@@ -0,0 +1,277 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Company:
|
||||||
|
// Engineer:
|
||||||
|
// _ _ ____
|
||||||
|
// | | ___ ___| |__ / ___| __ _ ___
|
||||||
|
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||||
|
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||||
|
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||||
|
//
|
||||||
|
// Create Date: 2022/07/01 17:37:27
|
||||||
|
// Last Modified Date: 2023/03/06 10:54
|
||||||
|
// Design Name:
|
||||||
|
// Module Name: ad9361_rx_mapping_dual
|
||||||
|
// Project Name:
|
||||||
|
// Target Devices:
|
||||||
|
// Tool Versions:
|
||||||
|
// Description:
|
||||||
|
//
|
||||||
|
// Dependencies:
|
||||||
|
//
|
||||||
|
// Revision:
|
||||||
|
// Revision 0.01 - File Created
|
||||||
|
// Additional Comments:
|
||||||
|
//
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
|
module ad9361_rx_map_lvds_dual
|
||||||
|
(
|
||||||
|
input clk_4x_in , // sync to input data
|
||||||
|
input clk_in_rst ,
|
||||||
|
|
||||||
|
input rx_data_clk , // sync to output data
|
||||||
|
input rx_data_clk_rst ,
|
||||||
|
|
||||||
|
input rx_fifo_rst , // async fifo reset
|
||||||
|
|
||||||
|
input rx_frame_p ,
|
||||||
|
input rx_frame_n ,
|
||||||
|
input [ 5:0] rx_data_p , // data from ad9361 p1 port
|
||||||
|
input [ 5:0] rx_data_n ,
|
||||||
|
|
||||||
|
output [11:0] rx_ch1_i ,
|
||||||
|
output [11:0] rx_ch1_q ,
|
||||||
|
output [11:0] rx_ch2_i ,
|
||||||
|
output [11:0] rx_ch2_q
|
||||||
|
);
|
||||||
|
|
||||||
|
genvar m;
|
||||||
|
|
||||||
|
// rx data
|
||||||
|
wire [5:0] rx_data;
|
||||||
|
wire [5:0] rx_data_i, rx_data_q;
|
||||||
|
|
||||||
|
generate
|
||||||
|
for (m=0; m<6; m=m+1) begin : rx_data_iddr
|
||||||
|
|
||||||
|
IBUFDS #(
|
||||||
|
.DIFF_TERM ("TRUE" )
|
||||||
|
) u_ibufds_rx_data
|
||||||
|
(
|
||||||
|
.I (rx_data_p[m] ),
|
||||||
|
.IB (rx_data_n[m] ),
|
||||||
|
.O (rx_data[m] )
|
||||||
|
);
|
||||||
|
|
||||||
|
IDDR #(
|
||||||
|
.DDR_CLK_EDGE ("SAME_EDGE" ),
|
||||||
|
.INIT_Q1 (1'b0 ),
|
||||||
|
.INIT_Q2 (1'b0 ),
|
||||||
|
.SRTYPE ("ASYNC" )
|
||||||
|
) u_rx_data_iddr (
|
||||||
|
.CE (1'b1 ), // clock enable
|
||||||
|
.R (1'b0 ), // iddr reset
|
||||||
|
.S (1'b0 ), // iddr set
|
||||||
|
.C (clk_4x_in ), // iddr clock
|
||||||
|
.D (rx_data[m] ), // ddr data
|
||||||
|
.Q1 (rx_data_q[m] ), // sdr data at rising edge
|
||||||
|
.Q2 (rx_data_i[m] ) // sdr data at falling edge
|
||||||
|
);
|
||||||
|
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
// rx frame
|
||||||
|
wire rx_frame;
|
||||||
|
wire rx_frame_i;
|
||||||
|
wire rx_frame_q;
|
||||||
|
|
||||||
|
IBUFDS #(
|
||||||
|
.DIFF_TERM ("TRUE" )
|
||||||
|
) u_ibufds_rx_frame
|
||||||
|
(
|
||||||
|
.I (rx_frame_p ),
|
||||||
|
.IB (rx_frame_n ),
|
||||||
|
.O (rx_frame )
|
||||||
|
);
|
||||||
|
|
||||||
|
IDDR #(
|
||||||
|
.DDR_CLK_EDGE ("SAME_EDGE" ),
|
||||||
|
.INIT_Q1 (1'b0 ),
|
||||||
|
.INIT_Q2 (1'b0 ),
|
||||||
|
.SRTYPE ("ASYNC" )
|
||||||
|
) u_rx_frame_iddr (
|
||||||
|
.CE (1'b1 ), // clock enable
|
||||||
|
.R (1'b0 ), // iddr reset
|
||||||
|
.S (1'b0 ), // iddr set
|
||||||
|
.C (clk_4x_in ), // iddr clock
|
||||||
|
.D (rx_frame ), // ddr data
|
||||||
|
.Q1 (rx_frame_q ), // sdr data at rising edge
|
||||||
|
.Q2 (rx_frame_i ) // sdr data at falling edge
|
||||||
|
);
|
||||||
|
|
||||||
|
// unpack rx frame & data
|
||||||
|
reg rx_frame_i_d1 = 'b0;
|
||||||
|
reg [ 5:0] rx_data_i_d1 = 'b0;
|
||||||
|
reg [ 5:0] rx_data_q_d1 = 'b0;
|
||||||
|
reg rx_flag = 'b0; // rx frame rising edge indicator
|
||||||
|
reg [ 1:0] rx_cnt = 'b0; // unpack stage counter
|
||||||
|
|
||||||
|
always @(posedge clk_4x_in) begin
|
||||||
|
// wait for [rx_flag]
|
||||||
|
rx_frame_i_d1 <= rx_frame_i;
|
||||||
|
rx_data_i_d1 <= rx_data_i;
|
||||||
|
rx_data_q_d1 <= rx_data_q;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk_4x_in) begin
|
||||||
|
if (clk_in_rst) begin
|
||||||
|
rx_flag <= 'b0;
|
||||||
|
end
|
||||||
|
else if (~rx_frame_i_d1 & rx_frame_i) begin
|
||||||
|
// assert when rising edge of rx frame is detected
|
||||||
|
rx_flag <= 'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
rx_flag <= rx_flag;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk_4x_in) begin
|
||||||
|
if (clk_in_rst) begin
|
||||||
|
rx_cnt <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
rx_cnt <= (rx_flag) ? rx_cnt + 1'b1 : rx_cnt;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
reg [11:0] rx1_data_i = 'b0;
|
||||||
|
reg [11:0] rx1_data_q = 'b0;
|
||||||
|
reg [11:0] rx2_data_i = 'b0;
|
||||||
|
reg [11:0] rx2_data_q = 'b0;
|
||||||
|
|
||||||
|
always @(posedge clk_4x_in) begin
|
||||||
|
if (clk_in_rst) begin
|
||||||
|
rx1_data_i <= 'b0;
|
||||||
|
rx1_data_q <= 'b0;
|
||||||
|
rx2_data_i <= 'b0;
|
||||||
|
rx2_data_q <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
case (rx_cnt)
|
||||||
|
3'd0: begin
|
||||||
|
// 1st clock cycle: upper 6-bit of rx ch1 inphase/quadrature data
|
||||||
|
rx1_data_i[11:6] <= rx_data_i_d1;
|
||||||
|
rx1_data_q[11:6] <= rx_data_q_d1;
|
||||||
|
end
|
||||||
|
3'd1: begin
|
||||||
|
// 2nd clock cycle: lower 6-bit of rx ch1 inphase/quadrature data
|
||||||
|
rx1_data_i[ 5:0] <= rx_data_i_d1;
|
||||||
|
rx1_data_q[ 5:0] <= rx_data_q_d1;
|
||||||
|
end
|
||||||
|
3'd2: begin
|
||||||
|
// 3rd clock cycle: upper 6-bit of rx ch2 inphase/quadrature data
|
||||||
|
rx2_data_i[11:6] <= rx_data_i_d1;
|
||||||
|
rx2_data_q[11:6] <= rx_data_q_d1;
|
||||||
|
end
|
||||||
|
3'd3: begin
|
||||||
|
// 4th clock cycle: lower 6-bit of rx ch2 inphase/quadrature data
|
||||||
|
rx2_data_i[ 5:0] <= rx_data_i_d1;
|
||||||
|
rx2_data_q[ 5:0] <= rx_data_q_d1;
|
||||||
|
end
|
||||||
|
default: begin
|
||||||
|
rx1_data_i <= 'b0;
|
||||||
|
rx1_data_q <= 'b0;
|
||||||
|
rx2_data_i <= 'b0;
|
||||||
|
rx2_data_q <= 'b0;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// write fifo when rx1/2_data_i/q are all prepared with 192MHz clock
|
||||||
|
// read fifo at every clock cycle with 48MHz clock
|
||||||
|
reg fifo_wr_en = 'b0;
|
||||||
|
reg fifo_rd_en = 'b0;
|
||||||
|
wire rx_fifo_empty_1;
|
||||||
|
wire rx_fifo_empty_2;
|
||||||
|
wire rx_fifo_empty_3;
|
||||||
|
wire rx_fifo_empty_4;
|
||||||
|
|
||||||
|
always @(posedge clk_4x_in) begin
|
||||||
|
if (clk_in_rst) begin
|
||||||
|
fifo_wr_en <= 'b0;
|
||||||
|
end
|
||||||
|
else if (rx_cnt == 2'd3) begin
|
||||||
|
fifo_wr_en <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
fifo_wr_en <= 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge rx_data_clk) begin
|
||||||
|
if (rx_data_clk_rst) begin
|
||||||
|
fifo_rd_en <= 1'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4};
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
ad9361_fifo u_rx_fifo_ch1_i
|
||||||
|
(
|
||||||
|
.rst (rx_fifo_rst ), // input wire rst
|
||||||
|
.wr_clk (clk_4x_in ), // input wire wr_clk
|
||||||
|
.rd_clk (rx_data_clk ), // input wire rd_clk
|
||||||
|
.din (rx1_data_i ), // input wire [11 : 0] din
|
||||||
|
.wr_en (fifo_wr_en ), // input wire wr_en
|
||||||
|
.rd_en (fifo_rd_en ), // input wire rd_en
|
||||||
|
.dout (rx_ch1_i ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty (rx_fifo_empty_1) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
ad9361_fifo u_rx_fifo_ch1_q
|
||||||
|
(
|
||||||
|
.rst (rx_fifo_rst ), // input wire rst
|
||||||
|
.wr_clk (clk_4x_in ), // input wire wr_clk
|
||||||
|
.rd_clk (rx_data_clk ), // input wire rd_clk
|
||||||
|
.din (rx1_data_q ), // input wire [11 : 0] din
|
||||||
|
.wr_en (fifo_wr_en ), // input wire wr_en
|
||||||
|
.rd_en (fifo_rd_en ), // input wire rd_en
|
||||||
|
.dout (rx_ch1_q ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty (rx_fifo_empty_2) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
ad9361_fifo u_rx_fifo_ch2_i
|
||||||
|
(
|
||||||
|
.rst (rx_fifo_rst ), // input wire rst
|
||||||
|
.wr_clk (clk_4x_in ), // input wire wr_clk
|
||||||
|
.rd_clk (rx_data_clk ), // input wire rd_clk
|
||||||
|
.din (rx2_data_i ), // input wire [11 : 0] din
|
||||||
|
.wr_en (fifo_wr_en ), // input wire wr_en
|
||||||
|
.rd_en (fifo_rd_en ), // input wire rd_en
|
||||||
|
.dout (rx_ch2_i ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty (rx_fifo_empty_3) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
ad9361_fifo u_rx_fifo_ch2_q
|
||||||
|
(
|
||||||
|
.rst (rx_fifo_rst ), // input wire rst
|
||||||
|
.wr_clk (clk_4x_in ), // input wire wr_clk
|
||||||
|
.rd_clk (rx_data_clk ), // input wire rd_clk
|
||||||
|
.din (rx2_data_q ), // input wire [11 : 0] din
|
||||||
|
.wr_en (fifo_wr_en ), // input wire wr_en
|
||||||
|
.rd_en (fifo_rd_en ), // input wire rd_en
|
||||||
|
.dout (rx_ch2_q ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty (rx_fifo_empty_4) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
+183
@@ -0,0 +1,183 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Company:
|
||||||
|
// Engineer:
|
||||||
|
// _ _ ____
|
||||||
|
// | | ___ ___| |__ / ___| __ _ ___
|
||||||
|
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||||
|
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||||
|
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||||
|
//
|
||||||
|
// Create Date: 2022/07/01 16:39:19
|
||||||
|
// Last Modified Date: 2023/03/06 11:45
|
||||||
|
// Design Name:
|
||||||
|
// Module Name: ad9361_tx_map_cmos_dual
|
||||||
|
// Project Name:
|
||||||
|
// Target Devices:
|
||||||
|
// Tool Versions:
|
||||||
|
// Description:
|
||||||
|
//
|
||||||
|
// Dependencies:
|
||||||
|
//
|
||||||
|
// Revision:
|
||||||
|
// Revision 0.01 - File Created
|
||||||
|
// Additional Comments:
|
||||||
|
//
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
|
module ad9361_tx_map_cmos_dual
|
||||||
|
(
|
||||||
|
input clk_2x_in ,
|
||||||
|
input clk_in_rst ,
|
||||||
|
|
||||||
|
input tx_data_clk ,
|
||||||
|
input tx_data_clk_rst ,
|
||||||
|
|
||||||
|
input [11:0] tx_ch1_i ,
|
||||||
|
input [11:0] tx_ch1_q ,
|
||||||
|
input [11:0] tx_ch2_i ,
|
||||||
|
input [11:0] tx_ch2_q ,
|
||||||
|
|
||||||
|
output clk_out ,
|
||||||
|
output tx_frame ,
|
||||||
|
output [11:0] tx_data
|
||||||
|
);
|
||||||
|
|
||||||
|
genvar m;
|
||||||
|
|
||||||
|
// input data fifo
|
||||||
|
reg rx_fifo_rd_en = 'b0;
|
||||||
|
wire [11:0] tx_fifo_ch1_i;
|
||||||
|
wire [11:0] tx_fifo_ch1_q;
|
||||||
|
wire [11:0] tx_fifo_ch2_i;
|
||||||
|
wire [11:0] tx_fifo_ch2_q;
|
||||||
|
|
||||||
|
always @(posedge clk_2x_in) begin
|
||||||
|
if (clk_in_rst) begin
|
||||||
|
rx_fifo_rd_en <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
rx_fifo_rd_en <= ~rx_fifo_rd_en;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
ad9361_fifo u_tx_fifo_ch1_i
|
||||||
|
(
|
||||||
|
.rst (clk_in_rst ), // input wire rst
|
||||||
|
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||||
|
.rd_clk (clk_2x_in ), // input wire rd_clk
|
||||||
|
.din (tx_ch1_i ), // input wire [11 : 0] din
|
||||||
|
.wr_en (1'b1 ), // input wire wr_en
|
||||||
|
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||||
|
.dout (tx_fifo_ch1_i ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty ( ) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
ad9361_fifo u_tx_fifo_ch1_q
|
||||||
|
(
|
||||||
|
.rst (clk_in_rst ), // input wire rst
|
||||||
|
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||||
|
.rd_clk (clk_2x_in ), // input wire rd_clk
|
||||||
|
.din (tx_ch1_q ), // input wire [11 : 0] din
|
||||||
|
.wr_en (1'b1 ), // input wire wr_en
|
||||||
|
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||||
|
.dout (tx_fifo_ch1_q ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty ( ) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
ad9361_fifo u_tx_fifo_ch2_i
|
||||||
|
(
|
||||||
|
.rst (clk_in_rst ), // input wire rst
|
||||||
|
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||||
|
.rd_clk (clk_2x_in ), // input wire rd_clk
|
||||||
|
.din (tx_ch2_i ), // input wire [11 : 0] din
|
||||||
|
.wr_en (1'b1 ), // input wire wr_en
|
||||||
|
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||||
|
.dout (tx_fifo_ch2_i ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty ( ) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
ad9361_fifo u_tx_fifo_ch2_q
|
||||||
|
(
|
||||||
|
.rst (clk_in_rst ), // input wire rst
|
||||||
|
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||||
|
.rd_clk (clk_2x_in ), // input wire rd_clk
|
||||||
|
.din (tx_ch2_q ), // input wire [11 : 0] din
|
||||||
|
.wr_en (1'b1 ), // input wire wr_en
|
||||||
|
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||||
|
.dout (tx_fifo_ch2_q ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty ( ) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
// frame and data control
|
||||||
|
reg tx_frame_i = 'b0;
|
||||||
|
reg tx_frame_q = 'b0;
|
||||||
|
reg [11:0] tx_data_i = 'b0;
|
||||||
|
reg [11:0] tx_data_q = 'b0;
|
||||||
|
|
||||||
|
always @(posedge clk_2x_in) begin
|
||||||
|
if (clk_in_rst) begin
|
||||||
|
tx_frame_i <= 'b0;
|
||||||
|
tx_frame_q <= 'b0;
|
||||||
|
tx_data_i <= 'b0;
|
||||||
|
tx_data_q <= 'b0;
|
||||||
|
end
|
||||||
|
else if (rx_fifo_rd_en == 1'b0) begin
|
||||||
|
tx_frame_i <= 1'b1;
|
||||||
|
tx_frame_q <= 1'b1;
|
||||||
|
tx_data_i <= tx_fifo_ch1_i;
|
||||||
|
tx_data_q <= tx_fifo_ch1_q;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
tx_frame_i <= 1'b0;
|
||||||
|
tx_frame_q <= 1'b0;
|
||||||
|
tx_data_i <= tx_fifo_ch2_i;
|
||||||
|
tx_data_q <= tx_fifo_ch2_q;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// output clock to port
|
||||||
|
assign clk_out = clk_2x_in;
|
||||||
|
|
||||||
|
// output tx frame to port
|
||||||
|
ODDR #(
|
||||||
|
.DDR_CLK_EDGE ("SAME_EDGE" ),
|
||||||
|
.INIT (1'b0 ),
|
||||||
|
.SRTYPE ("ASYNC" )
|
||||||
|
) u_tx_frame_oddr (
|
||||||
|
.CE (1'b1 ),
|
||||||
|
.R (1'b0 ),
|
||||||
|
.S (1'b0 ),
|
||||||
|
.C (clk_2x_in ),
|
||||||
|
.D1 (tx_frame_i ),
|
||||||
|
.D2 (tx_frame_q ),
|
||||||
|
.Q (tx_frame )
|
||||||
|
);
|
||||||
|
|
||||||
|
// output tx data to port
|
||||||
|
generate
|
||||||
|
for (m=0; m<12; m=m+1) begin: tx_data_oddr
|
||||||
|
|
||||||
|
ODDR #(
|
||||||
|
.DDR_CLK_EDGE ("SAME_EDGE" ),
|
||||||
|
.INIT (1'b0 ),
|
||||||
|
.SRTYPE ("ASYNC" )
|
||||||
|
) u_tx_data_oddr (
|
||||||
|
.CE (1'b1 ),
|
||||||
|
.R (1'b0 ),
|
||||||
|
.S (1'b0 ),
|
||||||
|
.C (clk_2x_in ),
|
||||||
|
.D1 (tx_data_i[m] ),
|
||||||
|
.D2 (tx_data_q[m] ),
|
||||||
|
.Q (tx_data[m] )
|
||||||
|
);
|
||||||
|
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
endmodule
|
||||||
+119
@@ -0,0 +1,119 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Company:
|
||||||
|
// Engineer:
|
||||||
|
// _ _ ____
|
||||||
|
// | | ___ ___| |__ / ___| __ _ ___
|
||||||
|
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||||
|
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||||
|
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||||
|
//
|
||||||
|
// Create Date: 2022/07/01 16:39:19
|
||||||
|
// Design Name:
|
||||||
|
// Module Name: ad9361_tx_mapping_single
|
||||||
|
// Project Name:
|
||||||
|
// Target Devices:
|
||||||
|
// Tool Versions:
|
||||||
|
// Description:
|
||||||
|
//
|
||||||
|
// Dependencies:
|
||||||
|
//
|
||||||
|
// Revision:
|
||||||
|
// Revision 0.01 - File Created
|
||||||
|
// Additional Comments:
|
||||||
|
//
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
|
module ad9361_tx_map_cmos_single
|
||||||
|
(
|
||||||
|
input clk_in ,
|
||||||
|
input clk_in_rst ,
|
||||||
|
|
||||||
|
input tx_data_clk ,
|
||||||
|
input tx_data_clk_rst ,
|
||||||
|
|
||||||
|
input [11:0] tx_data_i ,
|
||||||
|
input [11:0] tx_data_q ,
|
||||||
|
|
||||||
|
output clk_out ,
|
||||||
|
output tx_frame ,
|
||||||
|
output [11:0] tx_data
|
||||||
|
);
|
||||||
|
|
||||||
|
genvar m;
|
||||||
|
|
||||||
|
// inout data fifo
|
||||||
|
wire [11:0] tx_fifo_i;
|
||||||
|
wire [11:0] tx_fifo_q;
|
||||||
|
|
||||||
|
ad9361_fifo u_tx_fifo_i
|
||||||
|
(
|
||||||
|
.rst (clk_in_rst ), // input wire rst
|
||||||
|
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||||
|
.rd_clk (clk_in ), // input wire rd_clk
|
||||||
|
.din (tx_data_i ), // input wire [11 : 0] din
|
||||||
|
.wr_en (1'b1 ), // input wire wr_en
|
||||||
|
.rd_en (1'b1 ), // input wire rd_en
|
||||||
|
.dout (tx_fifo_i ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty ( ) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
ad9361_fifo u_tx_fifo_q
|
||||||
|
(
|
||||||
|
.rst (clk_in_rst ), // input wire rst
|
||||||
|
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||||
|
.rd_clk (clk_in ), // input wire rd_clk
|
||||||
|
.din (tx_data_q ), // input wire [11 : 0] din
|
||||||
|
.wr_en (1'b1 ), // input wire wr_en
|
||||||
|
.rd_en (1'b1 ), // input wire rd_en
|
||||||
|
.dout (tx_fifo_q ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty ( ) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
// frame and data control
|
||||||
|
assign tx_frame_i = 1'b1;
|
||||||
|
assign tx_frame_q = 1'b0;
|
||||||
|
|
||||||
|
// output clock to port
|
||||||
|
assign clk_out = clk_in;
|
||||||
|
|
||||||
|
// output tx frame to port
|
||||||
|
ODDR #(
|
||||||
|
.DDR_CLK_EDGE ("SAME_EDGE" ),
|
||||||
|
.INIT (1'b0 ),
|
||||||
|
.SRTYPE ("ASYNC" )
|
||||||
|
) u_tx_frame_oddr (
|
||||||
|
.CE (1'b1 ),
|
||||||
|
.R (1'b0 ),
|
||||||
|
.S (1'b0 ),
|
||||||
|
.C (clk_in ),
|
||||||
|
.D1 (tx_frame_i ),
|
||||||
|
.D2 (tx_frame_q ),
|
||||||
|
.Q (tx_frame )
|
||||||
|
);
|
||||||
|
|
||||||
|
// output tx data to port
|
||||||
|
generate
|
||||||
|
for (m=0; m<12; m=m+1) begin: tx_data_oddr
|
||||||
|
|
||||||
|
ODDR #(
|
||||||
|
.DDR_CLK_EDGE ("SAME_EDGE" ),
|
||||||
|
.INIT (1'b0 ),
|
||||||
|
.SRTYPE ("ASYNC" )
|
||||||
|
) u_tx_data_oddr (
|
||||||
|
.CE (1'b1 ),
|
||||||
|
.R (1'b0 ),
|
||||||
|
.S (1'b0 ),
|
||||||
|
.C (clk_in ),
|
||||||
|
.D1 (tx_fifo_i[m] ),
|
||||||
|
.D2 (tx_fifo_q[m] ),
|
||||||
|
.Q (tx_data[m] )
|
||||||
|
);
|
||||||
|
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
endmodule
|
||||||
+246
@@ -0,0 +1,246 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Company:
|
||||||
|
// Engineer:
|
||||||
|
// _ _ ____
|
||||||
|
// | | ___ ___| |__ / ___| __ _ ___
|
||||||
|
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||||
|
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||||
|
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||||
|
//
|
||||||
|
// Create Date: 2023/03/05 23:21:27
|
||||||
|
// Last Modified Date: 2023/03/06 11:01
|
||||||
|
// Design Name:
|
||||||
|
// Module Name: ad9361_tx_map_lvds_dual
|
||||||
|
// Project Name:
|
||||||
|
// Target Devices:
|
||||||
|
// Tool Versions:
|
||||||
|
// Description:
|
||||||
|
//
|
||||||
|
// Dependencies:
|
||||||
|
//
|
||||||
|
// Revision:
|
||||||
|
// Revision 0.01 - File Created
|
||||||
|
// Additional Comments:
|
||||||
|
//
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
|
module ad9361_tx_map_lvds_dual
|
||||||
|
(
|
||||||
|
input clk_4x_in ,
|
||||||
|
input clk_in_rst ,
|
||||||
|
|
||||||
|
input tx_data_clk ,
|
||||||
|
input tx_data_clk_rst ,
|
||||||
|
|
||||||
|
input [11:0] tx_ch1_i ,
|
||||||
|
input [11:0] tx_ch1_q ,
|
||||||
|
input [11:0] tx_ch2_i ,
|
||||||
|
input [11:0] tx_ch2_q ,
|
||||||
|
|
||||||
|
output clk_out_p ,
|
||||||
|
output clk_out_n ,
|
||||||
|
output tx_frame_p ,
|
||||||
|
output tx_frame_n ,
|
||||||
|
output [ 5:0] tx_data_p ,
|
||||||
|
output [ 5:0] tx_data_n
|
||||||
|
);
|
||||||
|
|
||||||
|
genvar m;
|
||||||
|
|
||||||
|
// input data fifo
|
||||||
|
reg [1:0] tx_control_cnt = 'b0;
|
||||||
|
reg rx_fifo_rd_en = 'b0;
|
||||||
|
wire [11:0] tx_fifo_ch1_i;
|
||||||
|
wire [11:0] tx_fifo_ch1_q;
|
||||||
|
wire [11:0] tx_fifo_ch2_i;
|
||||||
|
wire [11:0] tx_fifo_ch2_q;
|
||||||
|
|
||||||
|
always @(posedge clk_4x_in) begin
|
||||||
|
if (clk_in_rst) begin
|
||||||
|
tx_control_cnt <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
tx_control_cnt <= tx_control_cnt + 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk_4x_in) begin
|
||||||
|
if (clk_in_rst) begin
|
||||||
|
rx_fifo_rd_en <= 'b0;
|
||||||
|
end
|
||||||
|
else if (tx_control_cnt == 2'd2) begin
|
||||||
|
rx_fifo_rd_en <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
rx_fifo_rd_en <= 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
ad9361_fifo u_tx_fifo_ch1_i
|
||||||
|
(
|
||||||
|
.rst (clk_in_rst ), // input wire rst
|
||||||
|
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||||
|
.rd_clk (clk_4x_in ), // input wire rd_clk
|
||||||
|
.din (tx_ch1_i ), // input wire [11 : 0] din
|
||||||
|
.wr_en (1'b1 ), // input wire wr_en
|
||||||
|
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||||
|
.dout (tx_fifo_ch1_i ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty ( ) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
ad9361_fifo u_tx_fifo_ch1_q
|
||||||
|
(
|
||||||
|
.rst (clk_in_rst ), // input wire rst
|
||||||
|
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||||
|
.rd_clk (clk_4x_in ), // input wire rd_clk
|
||||||
|
.din (tx_ch1_q ), // input wire [11 : 0] din
|
||||||
|
.wr_en (1'b1 ), // input wire wr_en
|
||||||
|
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||||
|
.dout (tx_fifo_ch1_q ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty ( ) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
ad9361_fifo u_tx_fifo_ch2_i
|
||||||
|
(
|
||||||
|
.rst (clk_in_rst ), // input wire rst
|
||||||
|
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||||
|
.rd_clk (clk_4x_in ), // input wire rd_clk
|
||||||
|
.din (tx_ch2_i ), // input wire [11 : 0] din
|
||||||
|
.wr_en (1'b1 ), // input wire wr_en
|
||||||
|
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||||
|
.dout (tx_fifo_ch2_i ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty ( ) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
ad9361_fifo u_tx_fifo_ch2_q
|
||||||
|
(
|
||||||
|
.rst (clk_in_rst ), // input wire rst
|
||||||
|
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||||
|
.rd_clk (clk_4x_in ), // input wire rd_clk
|
||||||
|
.din (tx_ch2_q ), // input wire [11 : 0] din
|
||||||
|
.wr_en (1'b1 ), // input wire wr_en
|
||||||
|
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||||
|
.dout (tx_fifo_ch2_q ), // output wire [11 : 0] dout
|
||||||
|
.full ( ), // output wire full
|
||||||
|
.empty ( ) // output wire empty
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
// frame and data control
|
||||||
|
reg tx_frame_r = 'b0; // rising edge data
|
||||||
|
reg tx_frame_f = 'b0; // falling edge data
|
||||||
|
reg [5:0] tx_data_r = 'b0;
|
||||||
|
reg [5:0] tx_data_f = 'b0;
|
||||||
|
|
||||||
|
always @(posedge clk_4x_in) begin
|
||||||
|
if (clk_in_rst) begin
|
||||||
|
tx_frame_r <= 'b0;
|
||||||
|
tx_frame_f <= 'b0;
|
||||||
|
tx_data_r <= 'b0;
|
||||||
|
tx_data_f <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
case (tx_control_cnt)
|
||||||
|
2'd0: begin
|
||||||
|
tx_frame_r <= 1'b1;
|
||||||
|
tx_frame_f <= 1'b1;
|
||||||
|
tx_data_r <= tx_fifo_ch1_i[11: 6];
|
||||||
|
tx_data_f <= tx_fifo_ch1_q[11: 6];
|
||||||
|
end
|
||||||
|
2'd1: begin
|
||||||
|
tx_frame_r <= 1'b1;
|
||||||
|
tx_frame_f <= 1'b1;
|
||||||
|
tx_data_r <= tx_fifo_ch1_i[5:0];
|
||||||
|
tx_data_f <= tx_fifo_ch1_q[5:0];
|
||||||
|
end
|
||||||
|
2'd2: begin
|
||||||
|
tx_frame_r <= 1'b0;
|
||||||
|
tx_frame_f <= 1'b0;
|
||||||
|
tx_data_r <= tx_fifo_ch2_i[11:6];
|
||||||
|
tx_data_f <= tx_fifo_ch2_q[11:6];
|
||||||
|
end
|
||||||
|
2'd3: begin
|
||||||
|
tx_frame_r <= 1'b0;
|
||||||
|
tx_frame_f <= 1'b0;
|
||||||
|
tx_data_r <= tx_fifo_ch2_i[5:0];
|
||||||
|
tx_data_f <= tx_fifo_ch2_q[5:0];
|
||||||
|
end
|
||||||
|
default: begin
|
||||||
|
tx_frame_r <= 'b0;
|
||||||
|
tx_frame_f <= 'b0;
|
||||||
|
tx_data_r <= 'b0;
|
||||||
|
tx_data_f <= 'b0;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// output clock to port
|
||||||
|
wire clk_out;
|
||||||
|
assign clk_out = clk_4x_in;
|
||||||
|
|
||||||
|
OBUFDS u_obufds_clk_out
|
||||||
|
(
|
||||||
|
.I (clk_out ),
|
||||||
|
.O (clk_out_p ),
|
||||||
|
.OB (clk_out_n )
|
||||||
|
);
|
||||||
|
|
||||||
|
// output tx frame to port
|
||||||
|
ODDR #(
|
||||||
|
.DDR_CLK_EDGE ("SAME_EDGE" ),
|
||||||
|
.INIT (1'b0 ),
|
||||||
|
.SRTYPE ("ASYNC" )
|
||||||
|
) u_tx_frame_oddr (
|
||||||
|
.CE (1'b1 ),
|
||||||
|
.R (1'b0 ),
|
||||||
|
.S (1'b0 ),
|
||||||
|
.C (clk_4x_in ),
|
||||||
|
.D1 (tx_frame_r ),
|
||||||
|
.D2 (tx_frame_f ),
|
||||||
|
.Q (tx_frame )
|
||||||
|
);
|
||||||
|
|
||||||
|
OBUFDS u_obufds_tx_frame
|
||||||
|
(
|
||||||
|
.I (tx_frame ),
|
||||||
|
.O (tx_frame_p ),
|
||||||
|
.OB (tx_frame_n )
|
||||||
|
);
|
||||||
|
|
||||||
|
// output tx data to port
|
||||||
|
wire [5:0] tx_data;
|
||||||
|
|
||||||
|
generate
|
||||||
|
for (m=0; m<6; m=m+1) begin: tx_data_oddr
|
||||||
|
|
||||||
|
ODDR #(
|
||||||
|
.DDR_CLK_EDGE ("SAME_EDGE" ),
|
||||||
|
.INIT (1'b0 ),
|
||||||
|
.SRTYPE ("ASYNC" )
|
||||||
|
) u_tx_data_oddr (
|
||||||
|
.CE (1'b1 ),
|
||||||
|
.R (1'b0 ),
|
||||||
|
.S (1'b0 ),
|
||||||
|
.C (clk_4x_in ),
|
||||||
|
.D1 (tx_data_r[m] ),
|
||||||
|
.D2 (tx_data_f[m] ),
|
||||||
|
.Q (tx_data[m] )
|
||||||
|
);
|
||||||
|
|
||||||
|
OBUFDS u_obufds_tx_data
|
||||||
|
(
|
||||||
|
.I (tx_data[m] ),
|
||||||
|
.O (tx_data_p[m] ),
|
||||||
|
.OB (tx_data_n[m] )
|
||||||
|
);
|
||||||
|
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,303 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||||
|
<!-- -->
|
||||||
|
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||||
|
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||||
|
|
||||||
|
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/Workspace/vivado/vivado_pub/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.xpr">
|
||||||
|
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||||
|
<Configuration>
|
||||||
|
<Option Name="Id" Val="6455237789e34802b5930fcc12496fe7"/>
|
||||||
|
<Option Name="Part" Val="xc7k410tffg900-2"/>
|
||||||
|
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||||
|
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||||
|
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||||
|
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||||
|
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||||
|
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||||
|
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||||
|
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||||
|
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||||
|
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||||
|
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||||
|
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||||
|
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||||
|
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||||
|
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||||
|
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||||
|
<Option Name="BoardPart" Val=""/>
|
||||||
|
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||||
|
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="ProjectType" Val="Default"/>
|
||||||
|
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||||
|
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||||
|
<Option Name="IPCachePermission" Val="read"/>
|
||||||
|
<Option Name="IPCachePermission" Val="write"/>
|
||||||
|
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||||
|
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||||
|
<Option Name="SimCompileState" Val="TRUE"/>
|
||||||
|
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||||
|
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||||
|
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||||
|
<Option Name="EnableBDX" Val="FALSE"/>
|
||||||
|
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||||
|
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTXSimExportSim" Val="1"/>
|
||||||
|
<Option Name="WTModelSimExportSim" Val="1"/>
|
||||||
|
<Option Name="WTQuestaExportSim" Val="1"/>
|
||||||
|
<Option Name="WTIesExportSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsExportSim" Val="1"/>
|
||||||
|
<Option Name="WTRivieraExportSim" Val="1"/>
|
||||||
|
<Option Name="WTActivehdlExportSim" Val="1"/>
|
||||||
|
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||||
|
<Option Name="XSimRadix" Val="hex"/>
|
||||||
|
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||||
|
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||||
|
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||||
|
<Option Name="SimTypes" Val="rtl"/>
|
||||||
|
<Option Name="SimTypes" Val="bfm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||||
|
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||||
|
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||||
|
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||||
|
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||||
|
</Configuration>
|
||||||
|
<FileSets Version="1" Minor="32">
|
||||||
|
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||||
|
<Filter Type="Srcs"/>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_cmos_dual.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_lvds_dual.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="AutoDisabled" Val="1"/>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_cmos_single.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="AutoDisabled" Val="1"/>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_cmos_single.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="AutoDisabled" Val="1"/>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_lvds_dual.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="AutoDisabled" Val="1"/>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_cmos_dual.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="AutoDisabled" Val="1"/>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="ad9361_rx_map_cmos_dual"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||||
|
<Filter Type="Constrs"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="ConstrsType" Val="XDC"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="ad9361_rx_map_cmos_dual"/>
|
||||||
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
<Option Name="TransportPathDelay" Val="0"/>
|
||||||
|
<Option Name="TransportIntDelay" Val="0"/>
|
||||||
|
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||||
|
<Option Name="PamDesignTestbench" Val=""/>
|
||||||
|
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||||
|
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||||
|
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||||
|
<Option Name="SrcSet" Val="sources_1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||||
|
<Filter Type="Utils"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="ad9361_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ad9361_fifo" RelGenDir="$PGENDIR/ad9361_fifo">
|
||||||
|
<File Path="$PSRCDIR/sources_1/ip/ad9361_fifo/ad9361_fifo.xci">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopModule" Val="ad9361_fifo"/>
|
||||||
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
</FileSets>
|
||||||
|
<Simulators>
|
||||||
|
<Simulator Name="XSim">
|
||||||
|
<Option Name="Description" Val="Vivado Simulator"/>
|
||||||
|
<Option Name="CompiledLib" Val="0"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ModelSim">
|
||||||
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Questa">
|
||||||
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Xcelium">
|
||||||
|
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="VCS">
|
||||||
|
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Riviera">
|
||||||
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
</Simulators>
|
||||||
|
<Runs Version="1" Minor="21">
|
||||||
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="ad9361_fifo_synth_1" Type="Ft3:Synth" SrcSet="ad9361_fifo" Part="xc7k410tffg900-2" ConstrsSet="ad9361_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ad9361_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ad9361_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ad9361_fifo_synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="ad9361_fifo_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ad9361_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ad9361_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ad9361_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ad9361_fifo_impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
</Runs>
|
||||||
|
<Board/>
|
||||||
|
<DashboardSummary Version="1" Minor="0">
|
||||||
|
<Dashboards>
|
||||||
|
<Dashboard Name="default_dashboard">
|
||||||
|
<Gadgets>
|
||||||
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||||
|
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||||
|
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
</Gadgets>
|
||||||
|
</Dashboard>
|
||||||
|
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||||
|
</Dashboards>
|
||||||
|
</DashboardSummary>
|
||||||
|
</Project>
|
||||||
+17408
File diff suppressed because it is too large
Load Diff
+118
@@ -0,0 +1,118 @@
|
|||||||
|
%% File Header/文件说明
|
||||||
|
%
|
||||||
|
% 调零算法对幅相一致性的要求较高，且 AD9361 多片同步的精度随机性较大，因此需要对
|
||||||
|
% AD9361 多片同步误差进行精细校准。采用收发扩频码的方式在校准过程中对两片 AD9361
|
||||||
|
% 的两个接收通道进行幅相测量，在接收端使用加法器进行非相干相关峰累积，累积 N 个
|
||||||
|
% 符号后出峰，根据相关峰的高度差和相位差，在接收端对信号的幅度和相位进行补偿。
|
||||||
|
%
|
||||||
|
clc; clear; close all;
|
||||||
|
%% initial system parameters/初始系统参数
|
||||||
|
rng(0);
|
||||||
|
Eb_N0 = 30; % energy per bit to noise power spectral density ratio
|
||||||
|
interp = 8; % interpolation factor
|
||||||
|
SNR = 10*log10(2/interp) + Eb_N0; % signal-to-noise power ration
|
||||||
|
channelNum = 2;
|
||||||
|
deltaAmp = 1-(2*rand-1)*0.05; % random amplitude error, range: [0.95,1.05]
|
||||||
|
deltaAngRad = (2*rand-1)*pi; % random phase error, range: [-pi,pi]
|
||||||
|
deltaAngDeg = deltaAngRad/pi*180;
|
||||||
|
angleInit = 20/pi*180;
|
||||||
|
|
||||||
|
% standard pn sequence
|
||||||
|
pnSequence = comm.PNSequence('Polynomial','x^7+x^6+1', ...
|
||||||
|
'InitialConditions',[zeros(1,6),1],'SamplesPerFrame',2^7-1);
|
||||||
|
PRBS7 = pnSequence();
|
||||||
|
PRBS7_polar = 1-2*[PRBS7;0];
|
||||||
|
|
||||||
|
chipLen = length(PRBS7_polar); % pn chip length
|
||||||
|
accumSymbolNum = 16;
|
||||||
|
totalSymbolNum = accumSymbolNum+1;
|
||||||
|
|
||||||
|
randomChipIndex_ch1 = randi(chipLen*interp*2-1)-chipLen*interp; % random rx chip index
|
||||||
|
randomChipIndex_ch2 = randomChipIndex_ch1 + (randi(2*interp-1)-interp); % random rx chip index
|
||||||
|
% randomChipIndex_ch1 = -2; % random rx chip index
|
||||||
|
% randomChipIndex_ch2 = 5; % random rx chip index
|
||||||
|
|
||||||
|
%%
|
||||||
|
% 发送信号：方波成型
|
||||||
|
seqTx = kron(repmat(PRBS7_polar,totalSymbolNum,1),ones(interp,1));
|
||||||
|
|
||||||
|
% 接收信号：随机初始相位，加噪，随机幅度误差，随机相位误差
|
||||||
|
seqRx = awgn(seqTx,SNR,'measured').*[1,deltaAmp].*[exp(1i*angleInit),...
|
||||||
|
exp(1i*(angleInit+deltaAngRad))];
|
||||||
|
seqRx(:,1) = circshift(seqRx(:,1),randomChipIndex_ch1);
|
||||||
|
seqRx(:,2) = circshift(seqRx(:,2),randomChipIndex_ch2);
|
||||||
|
|
||||||
|
% 降采样，与 Verilog 实现一样在码片中心采样
|
||||||
|
seqRxDown = zeros(chipLen*accumSymbolNum,channelNum,interp);
|
||||||
|
|
||||||
|
for i = 0:interp-1
|
||||||
|
% 补偿 Verilog 模块的读数延迟
|
||||||
|
seqRxDown(:,:,i+1) = downsample(seqRx((1:accumSymbolNum*chipLen*interp)+2,:),interp,i);
|
||||||
|
end
|
||||||
|
|
||||||
|
% 取符号位
|
||||||
|
seqRxMsbReal = zeros(size(seqRxDown));
|
||||||
|
seqRxMsbImag = zeros(size(seqRxDown));
|
||||||
|
seqRxMsbReal(real(seqRxDown)>0) = 1;
|
||||||
|
seqRxMsbReal(real(seqRxDown)<0) = -1;
|
||||||
|
seqRxMsbImag(imag(seqRxDown)>0) = 1;
|
||||||
|
seqRxMsbImag(imag(seqRxDown)<0) = -1;
|
||||||
|
|
||||||
|
% 符号位累积
|
||||||
|
seqRxMsbRealAccum = zeros(chipLen,channelNum,interp);
|
||||||
|
seqRxMsbImagAccum = zeros(chipLen,channelNum,interp);
|
||||||
|
|
||||||
|
for i = 0:chipLen-1
|
||||||
|
% PN 码圆周移位，遍历所有 PN 码相位
|
||||||
|
PRBS7_cshift = circshift(repmat(PRBS7_polar,accumSymbolNum,1),-i); % 负号为了和 Verilog 程序对应
|
||||||
|
% 累积，若当前比特与 PN 码相同，结果 +1；否则结果 -1
|
||||||
|
seqRxMsbRealAccum(i+1,:,:) = sum(PRBS7_cshift==seqRxMsbReal)-...
|
||||||
|
sum(PRBS7_cshift~=seqRxMsbReal);
|
||||||
|
seqRxMsbImagAccum(i+1,:,:) = sum(PRBS7_cshift==seqRxMsbImag)-...
|
||||||
|
sum(PRBS7_cshift~=seqRxMsbImag);
|
||||||
|
end
|
||||||
|
|
||||||
|
seqRxMsbAccum = seqRxMsbRealAccum+1i*seqRxMsbImagAccum;
|
||||||
|
|
||||||
|
% 通过相关峰位置判断目标信号位置
|
||||||
|
maxPeakIndex = zeros(2,interp);
|
||||||
|
|
||||||
|
for i = 1:2
|
||||||
|
for j = 1:interp
|
||||||
|
maxPeakIndex(i,j) = find(abs(seqRxMsbAccum(:,i,j))==max(abs(seqRxMsbAccum(:,i,j))),1); % PN 码相位
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
maxPeakIndexDiff = zeros(channelNum,1); % 相位差
|
||||||
|
|
||||||
|
for i = 1:channelNum
|
||||||
|
for j = 1:interp
|
||||||
|
if (maxPeakIndex(i,j)==maxPeakIndex(i,1))
|
||||||
|
maxPeakIndexDiff(i) = j;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
% 以下条件仅对双通道有效
|
||||||
|
if (maxPeakIndex(1,1) == maxPeakIndex(2,1))
|
||||||
|
relativeDelay = maxPeakIndexDiff(2) - maxPeakIndexDiff(1);
|
||||||
|
desiredPointIndex = [1,1]+[0,chipLen];
|
||||||
|
elseif (mod(maxPeakIndex(1,1)-1,chipLen) == mod(maxPeakIndex(2,1),chipLen))
|
||||||
|
relativeDelay = maxPeakIndexDiff(2) - maxPeakIndexDiff(1) + interp;
|
||||||
|
desiredPointIndex = [1,2]+[0,chipLen];
|
||||||
|
elseif (mod(maxPeakIndex(1,1)+1,chipLen) == mod(maxPeakIndex(2,1),chipLen))
|
||||||
|
relativeDelay = maxPeakIndexDiff(2) - maxPeakIndexDiff(1) - interp;
|
||||||
|
desiredPointIndex = [2,1]+[0,chipLen];
|
||||||
|
end
|
||||||
|
|
||||||
|
% 输入信号累加
|
||||||
|
seqRxDownAccum = squeeze(sum(reshape(seqRxDown(:,:,1),128,[],2),2));
|
||||||
|
% 取目标位置信号
|
||||||
|
desiredPoint = seqRxDownAccum(desiredPointIndex);
|
||||||
|
|
||||||
|
ampEst = abs(desiredPoint)./abs(desiredPoint(1));
|
||||||
|
angleEst = (angle(desiredPoint) - angle(desiredPoint(1)))/pi*180;
|
||||||
|
|
||||||
|
seqRxExport = round([real(seqRx(:,1)),imag(seqRx(:,1)),real(seqRx(:,2)),...
|
||||||
|
imag(seqRx(:,2))]/max(abs(seqRx),[],'all')*(2^11-1));
|
||||||
|
writematrix(seqRxExport,'./fine_cal_data.txt');
|
||||||
@@ -0,0 +1,168 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Company:
|
||||||
|
// Engineer:
|
||||||
|
// _ _ ____
|
||||||
|
// | | ___ ___| |__ / ___| __ _ ___
|
||||||
|
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||||
|
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||||
|
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||||
|
//
|
||||||
|
// Create Date: 2023/02/17 16:51:52
|
||||||
|
// Design Name:
|
||||||
|
// Module Name: tb
|
||||||
|
// Project Name:
|
||||||
|
// Target Devices:
|
||||||
|
// Tool Versions:
|
||||||
|
// Description: testbench for [multi_ch_cal]
|
||||||
|
//
|
||||||
|
// Dependencies:
|
||||||
|
//
|
||||||
|
// Revision:
|
||||||
|
// Revision 0.01 - File Created
|
||||||
|
// Additional Comments:
|
||||||
|
//
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
|
module tb_multi_ch_cal;
|
||||||
|
|
||||||
|
localparam DATA_FILE_PATH = "../fine_cal_data.txt";
|
||||||
|
localparam DATA_LEN = 16384;
|
||||||
|
localparam DATA_WIDTH = 12;
|
||||||
|
localparam ACCUM_SYMBOL_NUM = 4;
|
||||||
|
|
||||||
|
// localparam DATA_FILE_PATH = "D:\\iladata_pn_trx_4.csv";
|
||||||
|
// localparam DATA_LEN = 131072;
|
||||||
|
// localparam DATA_WIDTH = 12;
|
||||||
|
|
||||||
|
reg clk = 'b0;
|
||||||
|
reg rst = 1'b1;
|
||||||
|
|
||||||
|
reg ad9361_1_cal_start = 'b0;
|
||||||
|
wire ad9361_1_cal_done ;
|
||||||
|
reg ad9361_2_cal_start = 'b0;
|
||||||
|
wire ad9361_2_cal_done ;
|
||||||
|
wire ad9361_cal_result ;
|
||||||
|
wire ad9361_cal_valid;
|
||||||
|
reg ad9361_recal = 'b0;
|
||||||
|
|
||||||
|
// phase difference of 180 degree
|
||||||
|
reg signed [11:0] rx_ch1_i = 'b0;
|
||||||
|
reg signed [11:0] rx_ch1_q = 'b0;
|
||||||
|
reg signed [11:0] rx_ch2_i = 'b0;
|
||||||
|
reg signed [11:0] rx_ch2_q = 'b0;
|
||||||
|
reg signed [11:0] rx_ch3_q = 'b0;
|
||||||
|
reg signed [11:0] rx_ch3_i = 'b0;
|
||||||
|
reg signed [11:0] rx_ch4_i = 'b0;
|
||||||
|
reg signed [11:0] rx_ch4_q = 'b0;
|
||||||
|
|
||||||
|
wire [11:0] rx_cal_ch1_i;
|
||||||
|
wire [11:0] rx_cal_ch2_i;
|
||||||
|
wire [11:0] rx_cal_ch3_i;
|
||||||
|
wire [11:0] rx_cal_ch4_i;
|
||||||
|
wire [11:0] rx_cal_ch1_q;
|
||||||
|
wire [11:0] rx_cal_ch2_q;
|
||||||
|
wire [11:0] rx_cal_ch3_q;
|
||||||
|
wire [11:0] rx_cal_ch4_q;
|
||||||
|
|
||||||
|
integer i = 0;
|
||||||
|
integer r_file;
|
||||||
|
|
||||||
|
multi_ch_cal #(
|
||||||
|
.ACCUM_SYMBOL_NUM (ACCUM_SYMBOL_NUM )
|
||||||
|
) u_multi_ch_cal
|
||||||
|
(
|
||||||
|
// clock & reset
|
||||||
|
.clk (clk ), // input clk
|
||||||
|
.rst (rst ), // input rst
|
||||||
|
// control interface
|
||||||
|
.ad9361_1_cal_start (ad9361_1_cal_start ), // input ad9361_1_cal_start
|
||||||
|
.ad9361_1_cal_done (ad9361_1_cal_done ), // output ad9361_1_cal_done
|
||||||
|
.ad9361_2_cal_start (ad9361_2_cal_start ), // input ad9361_2_cal_start
|
||||||
|
.ad9361_2_cal_done (ad9361_2_cal_done ), // output ad9361_2_cal_done
|
||||||
|
.ad9361_cal_result (ad9361_cal_result ), // output ad9361_cal_result
|
||||||
|
.ad9361_cal_valid (ad9361_cal_valid ), // output ad9361_cal_valid
|
||||||
|
.ad9361_recal (ad9361_recal ), // input ad9361_recal
|
||||||
|
// input data interface
|
||||||
|
.rx_ch1_i (rx_ch1_i ), // input [11:0] rx_ch1_i
|
||||||
|
.rx_ch2_i (rx_ch2_i ), // input [11:0] rx_ch2_i
|
||||||
|
.rx_ch3_i (rx_ch3_i ), // input [11:0] rx_ch3_i
|
||||||
|
.rx_ch4_i (rx_ch4_i ), // input [11:0] rx_ch4_i
|
||||||
|
.rx_ch1_q (rx_ch1_q ), // input [11:0] rx_ch1_q
|
||||||
|
.rx_ch2_q (rx_ch2_q ), // input [11:0] rx_ch2_q
|
||||||
|
.rx_ch3_q (rx_ch3_q ), // input [11:0] rx_ch3_q
|
||||||
|
.rx_ch4_q (rx_ch4_q ), // input [11:0] rx_ch4_q
|
||||||
|
// output data interface
|
||||||
|
.rx_cal_ch1_i (rx_cal_ch1_i ), // output [11:0] rx_cal_ch1_i
|
||||||
|
.rx_cal_ch2_i (rx_cal_ch2_i ), // output [11:0] rx_cal_ch2_i
|
||||||
|
.rx_cal_ch3_i (rx_cal_ch3_i ), // output [11:0] rx_cal_ch3_i
|
||||||
|
.rx_cal_ch4_i (rx_cal_ch4_i ), // output [11:0] rx_cal_ch4_i
|
||||||
|
.rx_cal_ch1_q (rx_cal_ch1_q ), // output [11:0] rx_cal_ch1_q
|
||||||
|
.rx_cal_ch2_q (rx_cal_ch2_q ), // output [11:0] rx_cal_ch2_q
|
||||||
|
.rx_cal_ch3_q (rx_cal_ch3_q ), // output [11:0] rx_cal_ch3_q
|
||||||
|
.rx_cal_ch4_q (rx_cal_ch4_q ) // output [11:0] rx_cal_ch4_q
|
||||||
|
);
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
r_file = $fopen(DATA_FILE_PATH,"r");
|
||||||
|
#102
|
||||||
|
rst = 1'b0;
|
||||||
|
#100
|
||||||
|
ad9361_1_cal_start = 1'b1;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (ad9361_1_cal_start) begin
|
||||||
|
if (i == DATA_LEN-1) begin
|
||||||
|
$fscanf(r_file,"%d,%d,%d,%d",
|
||||||
|
rx_ch2_i,
|
||||||
|
rx_ch2_q,
|
||||||
|
rx_ch4_i,
|
||||||
|
rx_ch4_q);
|
||||||
|
$fclose(r_file);
|
||||||
|
r_file = $fopen(DATA_FILE_PATH,"r");
|
||||||
|
i <= 0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
$fscanf(r_file,"%d,%d,%d,%d",
|
||||||
|
rx_ch2_i,
|
||||||
|
rx_ch2_q,
|
||||||
|
rx_ch4_i,
|
||||||
|
rx_ch4_q);
|
||||||
|
i <= i + 1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always begin
|
||||||
|
#10 clk = ~clk;
|
||||||
|
end
|
||||||
|
|
||||||
|
// initial begin
|
||||||
|
// #10000
|
||||||
|
// ad9361_recal = 1'b1;
|
||||||
|
// #20
|
||||||
|
// ad9361_recal = 1'b0;
|
||||||
|
// end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (ad9361_1_cal_done) begin
|
||||||
|
ad9361_2_cal_start <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
ad9361_2_cal_start <= 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (ad9361_2_cal_done) begin
|
||||||
|
#2000
|
||||||
|
ad9361_recal <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
ad9361_recal <= 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
+188
@@ -0,0 +1,188 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "atan2_16b",
|
||||||
|
"component_reference": "xilinx.com:ip:cordic:6.0",
|
||||||
|
"ip_revision": "20",
|
||||||
|
"gen_directory": "../../../../multi_ch_cal.gen/sources_1/ip/atan2_16b",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"Component_Name": [ { "value": "atan2_16b", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Functional_Selection": [ { "value": "Arc_Tan", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Architectural_Configuration": [ { "value": "Parallel", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Pipelining_Mode": [ { "value": "Maximum", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Data_Format": [ { "value": "SignedFraction", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Phase_Format": [ { "value": "Scaled_Radians", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Input_Width": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Output_Width": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Round_Mode": [ { "value": "Truncate", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Iterations": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Precision": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Coarse_Rotation": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Compensation_Scaling": [ { "value": "No_Scale_Compensation", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"cartesian_has_tuser": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"cartesian_tuser_width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
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|
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|
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|
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|
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+214
@@ -0,0 +1,214 @@
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|||||||
|
{
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|
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|
||||||
|
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|
||||||
|
"ip_revision": "20",
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
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|
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||||||
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|
||||||
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||||||
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||||||
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||||||
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|
||||||
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|
||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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|
||||||
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||||||
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||||||
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||||||
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|
||||||
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|
||||||
|
"C_TLAST_RESOLUTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_S_AXIS_PHASE_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_S_AXIS_PHASE_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXIS_PHASE_TDATA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXIS_PHASE_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_S_AXIS_CARTESIAN_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_S_AXIS_CARTESIAN_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXIS_CARTESIAN_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXIS_CARTESIAN_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXIS_DOUT_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXIS_DOUT_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "kintex7" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xc7k410t" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffg900" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||||
|
"IPREVISION": [ { "value": "20" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../multi_ch_cal.gen/sources_1/ip/rotate_16b" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "." } ],
|
||||||
|
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"aclk": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||||
|
"s_axis_phase_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axis_phase_tdata": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"s_axis_cartesian_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axis_cartesian_tdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"m_axis_dout_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||||
|
"m_axis_dout_tdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"S_AXIS_CARTESIAN": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "s_axis_cartesian_tdata" } ],
|
||||||
|
"TVALID": [ { "physical_name": "s_axis_cartesian_tvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"aclk_intf": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS_DOUT:S_AXIS_PHASE:S_AXIS_CARTESIAN", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "1000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "aclk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"aresetn_intf": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"aclken_intf": {
|
||||||
|
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"S_AXIS_PHASE": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "s_axis_phase_tdata" } ],
|
||||||
|
"TVALID": [ { "physical_name": "s_axis_phase_tvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXIS_DOUT": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "m_axis_dout_tdata" } ],
|
||||||
|
"TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,893 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Company:
|
||||||
|
// Engineer:
|
||||||
|
// _ _ ____
|
||||||
|
// | | ___ ___| |__ / ___| __ _ ___
|
||||||
|
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||||
|
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||||
|
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||||
|
//
|
||||||
|
// Create Date: 2023/02/15 17:47:17
|
||||||
|
// Last Modified Date: 2023/03/04 12:30:00
|
||||||
|
// Design Name:
|
||||||
|
// Module Name: multi_ch_cal
|
||||||
|
// Project Name:
|
||||||
|
// Target Devices:
|
||||||
|
// Tool Versions:
|
||||||
|
// Description: 本程序用于
|
||||||
|
//
|
||||||
|
// Dependencies:
|
||||||
|
//
|
||||||
|
// Revision:
|
||||||
|
// Revision 0.01 - File Created
|
||||||
|
// 20230304-1230
|
||||||
|
// 1. 修改相位差计算结果，原计算结果可能超出 [-pi,pi] 范围，现在会进行修正；
|
||||||
|
// 2. 修改 CORDIC IP 核相位输入输出为 Scaled Radians 模式；
|
||||||
|
// 3. 修改 [cnt_decim] 在校准完成状态下的值为 0；
|
||||||
|
// 4. 通道间相对延迟计算不正确，修改 [peak_index_num] 为无符号数即可；
|
||||||
|
// 5. 修改 [atan2_data_xxxx] 在累积结果长度小于 CORDIC AXIS 位宽时的符号位扩展方法。
|
||||||
|
// Additional Comments:
|
||||||
|
//
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
|
module multi_ch_cal
|
||||||
|
#(
|
||||||
|
parameter ADC_DATA_WIDTH = 12,
|
||||||
|
parameter PRBS = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
|
||||||
|
parameter PRBS_LEN = 128, // length of pseudorandom bit sequence
|
||||||
|
parameter INTERP_FACTOR = 8, // interpolation factor, max inter-channel delay ranges in [-INTERP_FACTOR+1,INTERP_FACTOR-1]
|
||||||
|
parameter ACCUM_SYMBOL_NUM = 16,
|
||||||
|
parameter CORDIC_WIDTH = 16, // input and output data width of cordic-ip-based atan2 and rotation operation
|
||||||
|
parameter CHANNEL_NUM = 2 // the channel number of current algorithm is LIMITED to 2
|
||||||
|
)
|
||||||
|
(
|
||||||
|
// clock & reset
|
||||||
|
input clk ,
|
||||||
|
input rst ,
|
||||||
|
// control interface
|
||||||
|
input ad9361_1_cal_start ,
|
||||||
|
output ad9361_1_cal_done ,
|
||||||
|
input ad9361_2_cal_start ,
|
||||||
|
output ad9361_2_cal_done ,
|
||||||
|
output ad9361_cal_result ,
|
||||||
|
output ad9361_cal_valid ,
|
||||||
|
input ad9361_recal ,
|
||||||
|
// input data interface
|
||||||
|
input [ADC_DATA_WIDTH-1 : 0] rx_ch1_i ,
|
||||||
|
input [ADC_DATA_WIDTH-1 : 0] rx_ch1_q ,
|
||||||
|
input [ADC_DATA_WIDTH-1 : 0] rx_ch2_i ,
|
||||||
|
input [ADC_DATA_WIDTH-1 : 0] rx_ch2_q ,
|
||||||
|
input [ADC_DATA_WIDTH-1 : 0] rx_ch3_i ,
|
||||||
|
input [ADC_DATA_WIDTH-1 : 0] rx_ch3_q ,
|
||||||
|
input [ADC_DATA_WIDTH-1 : 0] rx_ch4_i ,
|
||||||
|
input [ADC_DATA_WIDTH-1 : 0] rx_ch4_q ,
|
||||||
|
// output data interface
|
||||||
|
output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch1_i ,
|
||||||
|
output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch1_q ,
|
||||||
|
output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch2_i ,
|
||||||
|
output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch2_q ,
|
||||||
|
output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch3_i ,
|
||||||
|
output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch3_q ,
|
||||||
|
output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch4_i ,
|
||||||
|
output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch4_q
|
||||||
|
);
|
||||||
|
|
||||||
|
localparam STATE_IDLE = 2'd0; // idle state
|
||||||
|
localparam STATE_CAL_1 = 2'd1; // correlation, accumulation and peak finding
|
||||||
|
localparam STATE_CAL_2 = 2'd2; // phase calculation, rotation and delay compensation
|
||||||
|
localparam STATE_DONE = 2'd3; // done state
|
||||||
|
|
||||||
|
localparam signed POS_PI_2Q13_SCALED = 16'b001_00000_00000_000;
|
||||||
|
localparam signed NEG_PI_2Q13_SCALED = 16'b111_00000_00000_000;
|
||||||
|
|
||||||
|
integer i, j;
|
||||||
|
genvar m, n;
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
///////////////////////////// Center State Machine /////////////////////////////
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// buffer input control signals (clock domain crossing from ps to pl clock domain)
|
||||||
|
reg ad9361_1_cal_start_d1 = 'b0;
|
||||||
|
reg ad9361_1_cal_start_d2 = 'b0;
|
||||||
|
reg ad9361_2_cal_start_d1 = 'b0;
|
||||||
|
reg ad9361_2_cal_start_d2 = 'b0;
|
||||||
|
reg ad9361_recal_d1 = 'b0;
|
||||||
|
reg ad9361_recal_d2 = 'b0;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
ad9361_1_cal_start_d1 <= ad9361_1_cal_start;
|
||||||
|
ad9361_1_cal_start_d2 <= ad9361_1_cal_start_d1;
|
||||||
|
|
||||||
|
ad9361_2_cal_start_d1 <= ad9361_2_cal_start;
|
||||||
|
ad9361_2_cal_start_d2 <= ad9361_2_cal_start_d1;
|
||||||
|
|
||||||
|
ad9361_recal_d1 <= ad9361_recal;
|
||||||
|
ad9361_recal_d2 <= ad9361_recal_d1;
|
||||||
|
end
|
||||||
|
|
||||||
|
// center state machine
|
||||||
|
reg [ 1:0] curr_state = STATE_IDLE;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
curr_state <= STATE_IDLE;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
case (curr_state)
|
||||||
|
STATE_IDLE: begin
|
||||||
|
// move to next state when [ad9361_1_cal_start] asserts
|
||||||
|
curr_state <= ad9361_1_cal_start_d2 ? STATE_CAL_1 : STATE_IDLE;
|
||||||
|
end
|
||||||
|
STATE_CAL_1: begin
|
||||||
|
// move to next state when 1st cal finishes and [ad9361_2_cal_start] asserts
|
||||||
|
curr_state <= ad9361_1_cal_done ? STATE_CAL_2 : STATE_CAL_1;
|
||||||
|
end
|
||||||
|
STATE_CAL_2: begin
|
||||||
|
// move to next state when 2nd cal finishes
|
||||||
|
curr_state <= ad9361_2_cal_done ? STATE_DONE : STATE_CAL_2;
|
||||||
|
end
|
||||||
|
STATE_DONE: begin
|
||||||
|
// move to IDLE state when it needs to recal
|
||||||
|
curr_state <= (ad9361_recal_d2) ? STATE_IDLE : STATE_DONE;
|
||||||
|
end
|
||||||
|
default: begin
|
||||||
|
curr_state <= STATE_IDLE;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
///////////////////////////////// Accumulation /////////////////////////////////
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// state counter
|
||||||
|
reg [$clog2(INTERP_FACTOR)-1 : 0] cnt_decim = 'b0; // downsample counter, mod [INTERP_FACTOR]
|
||||||
|
reg [$clog2(PRBS_LEN)-1 : 0] cnt_chip_in = 'b0; // input chip counter, mod [PRBS_LEN]
|
||||||
|
reg [$clog2(PRBS_LEN)-1 : 0] pn_curr_addr = 'b0; // current local pn address, mod [PRBS_LEN]
|
||||||
|
reg [$clog2(ACCUM_SYMBOL_NUM)-1 : 0] cnt_symbol = 'b0; // accumulation symbol counter, mod [ACCUM_SYMBOL_NUM]
|
||||||
|
reg [$clog2(PRBS_LEN)-1 : 0] cnt_accum = 'b0; // accumulation result index indicator, mod [PRBS_LEN]
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
// downsample counter, each clock cycles increase by 1 during calibration state
|
||||||
|
if (rst) begin
|
||||||
|
cnt_decim <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
case (curr_state)
|
||||||
|
STATE_IDLE : cnt_decim <= 'b0;
|
||||||
|
STATE_CAL_1: cnt_decim <= cnt_decim + 1'b1;
|
||||||
|
STATE_CAL_2: cnt_decim <= cnt_decim + 1'b1;
|
||||||
|
STATE_DONE : cnt_decim <= 'b0;
|
||||||
|
default : cnt_decim <= 'b0;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
cnt_chip_in <= 'b0;
|
||||||
|
end
|
||||||
|
else if (curr_state == STATE_IDLE) begin
|
||||||
|
// reset at IDLE state
|
||||||
|
cnt_chip_in <= 'b0;
|
||||||
|
end
|
||||||
|
else if (cnt_decim == INTERP_FACTOR-1) begin
|
||||||
|
// each time the number of samples received is [INTERP_FACTOR], increase the counter by 1,
|
||||||
|
// indicating a new chip is received
|
||||||
|
cnt_chip_in <= cnt_chip_in + 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cnt_chip_in <= cnt_chip_in;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
pn_curr_addr <= 'b0;
|
||||||
|
end
|
||||||
|
else if (curr_state == STATE_IDLE) begin
|
||||||
|
// reset at IDLE state
|
||||||
|
pn_curr_addr <= 'b0;
|
||||||
|
end
|
||||||
|
else if (cnt_decim == INTERP_FACTOR-1) begin
|
||||||
|
// each time the number of samples received is [INTERP_FACTOR], if the number of complete symbols
|
||||||
|
// accumulated is [ACCUM_SYMBOL_NUM], increase the address by 2; otherwise by 1. The increasing-by-2
|
||||||
|
// behaviour is analogous to `circshift` operation in MATLAB.
|
||||||
|
pn_curr_addr <= (cnt_symbol == ACCUM_SYMBOL_NUM-1 && cnt_chip_in == PRBS_LEN-1) ? pn_curr_addr + 2'd2 : pn_curr_addr + 2'd1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
pn_curr_addr <= pn_curr_addr;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
cnt_symbol <= 'b0;
|
||||||
|
end
|
||||||
|
else if (curr_state == STATE_IDLE) begin
|
||||||
|
// reset at IDLE state
|
||||||
|
cnt_symbol <= 'b0;
|
||||||
|
end
|
||||||
|
else if (cnt_chip_in == PRBS_LEN-1 && cnt_decim == INTERP_FACTOR-1) begin
|
||||||
|
// each time the number of complete chips received is [PRBS_LEN], increase the counter by 1,
|
||||||
|
// indicating a complete symbol is received
|
||||||
|
cnt_symbol <= cnt_symbol + 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cnt_symbol <= cnt_symbol;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
cnt_accum <= 'b0;
|
||||||
|
end
|
||||||
|
else if (curr_state == STATE_IDLE) begin
|
||||||
|
// reset at IDLE state
|
||||||
|
cnt_accum <= 'b0;
|
||||||
|
end
|
||||||
|
else if (cnt_symbol == ACCUM_SYMBOL_NUM-1 && cnt_chip_in == PRBS_LEN-1 && cnt_decim == INTERP_FACTOR-1) begin
|
||||||
|
// each time the number of complete symbols received is [ACCUM_SYMBOL_NUM], increase the counter by 1,
|
||||||
|
// indicating the accumulation of current pn code phased is finished
|
||||||
|
cnt_accum <= cnt_accum + 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cnt_accum <= cnt_accum;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// accumulate the msb of input data at different sample position
|
||||||
|
localparam MSB_ACCUM_LEN = $clog2(PRBS_LEN*ACCUM_SYMBOL_NUM)+2; // extra 2 bits to ensure signed operation and to prevent overflow
|
||||||
|
|
||||||
|
reg signed [MSB_ACCUM_LEN-1 : 0] msb_accum_i [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1];
|
||||||
|
reg signed [MSB_ACCUM_LEN-1 : 0] msb_accum_q [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1];
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
for (i = 0; i < CHANNEL_NUM; i = i + 1) begin
|
||||||
|
for (j = 0; j < INTERP_FACTOR; j = j + 1) begin
|
||||||
|
msb_accum_i[i][j] <= 'b0;
|
||||||
|
msb_accum_q[i][j] <= 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else if (curr_state == STATE_CAL_1) begin
|
||||||
|
if (cnt_symbol == 'b0 && cnt_chip_in == 'b0) begin
|
||||||
|
// set the initial value to 1 when msb equals current pn code, otherwise set to -1
|
||||||
|
msb_accum_i[0][cnt_decim] <= (rx_ch2_i[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? 1'b1 : -1'b1;
|
||||||
|
msb_accum_q[0][cnt_decim] <= (rx_ch2_q[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? 1'b1 : -1'b1;
|
||||||
|
msb_accum_i[1][cnt_decim] <= (rx_ch4_i[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? 1'b1 : -1'b1;
|
||||||
|
msb_accum_q[1][cnt_decim] <= (rx_ch4_q[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? 1'b1 : -1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
// increase when msb equals current pn code, otherwise decrease
|
||||||
|
msb_accum_i[0][cnt_decim] <= (rx_ch2_i[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? (msb_accum_i[0][cnt_decim] + 1'b1) : (msb_accum_i[0][cnt_decim] - 1'b1);
|
||||||
|
msb_accum_q[0][cnt_decim] <= (rx_ch2_q[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? (msb_accum_q[0][cnt_decim] + 1'b1) : (msb_accum_q[0][cnt_decim] - 1'b1);
|
||||||
|
msb_accum_i[1][cnt_decim] <= (rx_ch4_i[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? (msb_accum_i[1][cnt_decim] + 1'b1) : (msb_accum_i[1][cnt_decim] - 1'b1);
|
||||||
|
msb_accum_q[1][cnt_decim] <= (rx_ch4_q[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? (msb_accum_q[1][cnt_decim] + 1'b1) : (msb_accum_q[1][cnt_decim] - 1'b1);
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
for (i = 0; i < CHANNEL_NUM; i = i + 1) begin
|
||||||
|
for (j = 0; j < INTERP_FACTOR; j = j + 1) begin
|
||||||
|
msb_accum_i[i][j] <= 'b0;
|
||||||
|
msb_accum_q[i][j] <= 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// flag signal indicating the accumulation within one symbol (i.e. one kind of pn phase) is finished
|
||||||
|
reg symbol_msb_accum_valid = 'b0;
|
||||||
|
// preserve pn phase index for approximate moduli module
|
||||||
|
reg [$clog2(PRBS_LEN)-1 : 0] symbol_msb_accum_index = 'b0;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
symbol_msb_accum_valid <= 'b0;
|
||||||
|
end
|
||||||
|
else if (cnt_symbol == ACCUM_SYMBOL_NUM-1 && cnt_chip_in == PRBS_LEN-1 && cnt_decim == INTERP_FACTOR-1) begin
|
||||||
|
symbol_msb_accum_valid <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
symbol_msb_accum_valid <= 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
symbol_msb_accum_index <= 'b0;
|
||||||
|
end
|
||||||
|
else if (curr_state == STATE_IDLE) begin
|
||||||
|
symbol_msb_accum_index <= 'b0;
|
||||||
|
end
|
||||||
|
else if (cnt_symbol == ACCUM_SYMBOL_NUM-1 && cnt_chip_in == PRBS_LEN-1 && cnt_decim == INTERP_FACTOR-1) begin
|
||||||
|
symbol_msb_accum_index <= cnt_accum;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
symbol_msb_accum_index <= symbol_msb_accum_index;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// truncate or shift to fit in 26-bit data format & get the absolute value
|
||||||
|
wire [25 : 0] msb_accum_i_26b [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1];
|
||||||
|
wire [25 : 0] msb_accum_q_26b [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1];
|
||||||
|
wire [25 : 0] msb_accum_abs [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1];
|
||||||
|
wire msb_accum_abs_valid [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1];
|
||||||
|
|
||||||
|
generate
|
||||||
|
for (m = 0; m < CHANNEL_NUM; m = m + 1) begin
|
||||||
|
for (n = 0; n < INTERP_FACTOR; n = n + 1) begin
|
||||||
|
|
||||||
|
assign msb_accum_i_26b[m][n] = (MSB_ACCUM_LEN > 26) ? msb_accum_i[m][n][MSB_ACCUM_LEN-1 -: 26] : {{(26-MSB_ACCUM_LEN){msb_accum_i[m][n][MSB_ACCUM_LEN-1]}},msb_accum_i[m][n]};
|
||||||
|
assign msb_accum_q_26b[m][n] = (MSB_ACCUM_LEN > 26) ? msb_accum_q[m][n][MSB_ACCUM_LEN-1 -: 26] : {{(26-MSB_ACCUM_LEN){msb_accum_q[m][n][MSB_ACCUM_LEN-1]}},msb_accum_q[m][n]};
|
||||||
|
|
||||||
|
ApproxModuli_26bit u_msb_accum_abs
|
||||||
|
(
|
||||||
|
.clk (clk ),
|
||||||
|
.din_valid (symbol_msb_accum_valid ),
|
||||||
|
.din_I (msb_accum_i_26b[m][n] ),
|
||||||
|
.din_Q (msb_accum_q_26b[m][n] ),
|
||||||
|
.dout_valid (msb_accum_abs_valid[m][n] ),
|
||||||
|
.dout (msb_accum_abs[m][n] )
|
||||||
|
);
|
||||||
|
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
|
||||||
|
// record the peak index and corresponding value
|
||||||
|
reg [25 : 0] msb_accum_abs_peak [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1];
|
||||||
|
reg [$clog2(PRBS_LEN)-1 : 0] msb_accum_abs_peak_index [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1];
|
||||||
|
|
||||||
|
generate
|
||||||
|
for (m = 0; m < CHANNEL_NUM; m = m + 1) begin
|
||||||
|
for (n = 0; n < INTERP_FACTOR; n = n + 1) begin
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
msb_accum_abs_peak[m][n] <= 'b0;
|
||||||
|
msb_accum_abs_peak_index[m][n] <= 'b0;
|
||||||
|
end
|
||||||
|
else if (curr_state == STATE_IDLE) begin
|
||||||
|
msb_accum_abs_peak[m][n] <= 'b0;
|
||||||
|
msb_accum_abs_peak_index[m][n] <= 'b0;
|
||||||
|
end
|
||||||
|
else if (msb_accum_abs_valid[m][n]) begin
|
||||||
|
msb_accum_abs_peak[m][n] <= (msb_accum_abs_peak[m][n] >= msb_accum_abs[m][n]) ? msb_accum_abs_peak[m][n] : msb_accum_abs[m][n];
|
||||||
|
msb_accum_abs_peak_index[m][n] <= (msb_accum_abs_peak[m][n] >= msb_accum_abs[m][n]) ? msb_accum_abs_peak_index[m][n] : symbol_msb_accum_index;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
|
||||||
|
// accumulate input data at the 1st sample position and the 1st and 2nd chip position
|
||||||
|
// during the last msb accumulation cycle
|
||||||
|
localparam DATA_ACCUM_LEN = $clog2(ACCUM_SYMBOL_NUM)+ADC_DATA_WIDTH;
|
||||||
|
|
||||||
|
reg signed [DATA_ACCUM_LEN-1 : 0] rx_i_accum [0 : CHANNEL_NUM-1][0 : 1];
|
||||||
|
reg signed [DATA_ACCUM_LEN-1 : 0] rx_q_accum [0 : CHANNEL_NUM-1][0 : 1];
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
for(i = 0; i < CHANNEL_NUM; i = i + 1) begin
|
||||||
|
for(j = 0; j < 2; j = j + 1) begin
|
||||||
|
rx_i_accum[i][j] <= 'b0;
|
||||||
|
rx_q_accum[i][j] <= 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else if (curr_state == STATE_IDLE) begin
|
||||||
|
for(i = 0; i < CHANNEL_NUM; i = i + 1) begin
|
||||||
|
for(j = 0; j < 2; j = j + 1) begin
|
||||||
|
// reset at IDLE state
|
||||||
|
rx_i_accum[i][j] <= 'b0;
|
||||||
|
rx_q_accum[i][j] <= 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else if (cnt_accum == PRBS_LEN-1 && cnt_decim == 'b0) begin
|
||||||
|
case (cnt_chip_in)
|
||||||
|
1'b0: begin
|
||||||
|
rx_i_accum[0][0] <= rx_i_accum[0][0] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch2_i[ADC_DATA_WIDTH-1]}},rx_ch2_i};
|
||||||
|
rx_q_accum[0][0] <= rx_q_accum[0][0] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch2_q[ADC_DATA_WIDTH-1]}},rx_ch2_q};
|
||||||
|
rx_i_accum[1][0] <= rx_i_accum[1][0] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch4_i[ADC_DATA_WIDTH-1]}},rx_ch4_i};
|
||||||
|
rx_q_accum[1][0] <= rx_q_accum[1][0] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch4_q[ADC_DATA_WIDTH-1]}},rx_ch4_q};
|
||||||
|
end
|
||||||
|
1'b1: begin
|
||||||
|
rx_i_accum[0][1] <= rx_i_accum[0][1] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch2_i[ADC_DATA_WIDTH-1]}},rx_ch2_i};
|
||||||
|
rx_q_accum[0][1] <= rx_q_accum[0][1] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch2_q[ADC_DATA_WIDTH-1]}},rx_ch2_q};
|
||||||
|
rx_i_accum[1][1] <= rx_i_accum[1][1] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch4_i[ADC_DATA_WIDTH-1]}},rx_ch4_i};
|
||||||
|
rx_q_accum[1][1] <= rx_q_accum[1][1] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch4_q[ADC_DATA_WIDTH-1]}},rx_ch4_q};
|
||||||
|
end
|
||||||
|
default: begin
|
||||||
|
for(i = 0; i < CHANNEL_NUM; i = i + 1) begin
|
||||||
|
for(j = 0; j < 2; j = j + 1) begin
|
||||||
|
rx_i_accum[i][j] <= rx_i_accum[i][j];
|
||||||
|
rx_q_accum[i][j] <= rx_q_accum[i][j];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
for(i = 0; i < CHANNEL_NUM; i = i + 1) begin
|
||||||
|
for(j = 0; j < 2; j = j + 1) begin
|
||||||
|
rx_i_accum[i][j] <= rx_i_accum[i][j];
|
||||||
|
rx_q_accum[i][j] <= rx_q_accum[i][j];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// flag signal indicating the accumulation stage of calculation is finished
|
||||||
|
reg ad9361_1_cal_done_buf = 'b0;
|
||||||
|
|
||||||
|
assign ad9361_1_cal_done = ad9361_1_cal_done_buf;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
ad9361_1_cal_done_buf <= 'b0;
|
||||||
|
end
|
||||||
|
else if (curr_state == STATE_IDLE) begin
|
||||||
|
// reset at IDLE state
|
||||||
|
ad9361_1_cal_done_buf <= 'b0;
|
||||||
|
end
|
||||||
|
else if (cnt_accum == PRBS_LEN-1 && cnt_symbol == ACCUM_SYMBOL_NUM-1 && cnt_chip_in == PRBS_LEN-1 && cnt_decim == INTERP_FACTOR-1) begin
|
||||||
|
ad9361_1_cal_done_buf <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
ad9361_1_cal_done_buf <= ad9361_1_cal_done_buf;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
///////////////////////////////// Accumulation /////////////////////////////////
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// indicating the peak finding process is finished
|
||||||
|
reg peak_index_valid = 'b0;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
peak_index_valid <= 'b0;
|
||||||
|
end
|
||||||
|
else if (curr_state == STATE_CAL_2) begin
|
||||||
|
peak_index_valid <= msb_accum_abs_valid[0][0] ? 1'b1 : peak_index_valid;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
peak_index_valid <= 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// count the number of same peak index
|
||||||
|
reg [$clog2(INTERP_FACTOR)-1 : 0] peak_index_num [0 : CHANNEL_NUM-1];
|
||||||
|
reg peak_index_num_valid = 'b0;
|
||||||
|
|
||||||
|
reg signed [$clog2(INTERP_FACTOR) : 0] peak_index_num_diff = 'b0; // currently limit channel number to 2
|
||||||
|
reg peak_index_num_diff_valid = 'b0;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
for (i = 0; i < CHANNEL_NUM; i = i + 1) begin
|
||||||
|
peak_index_num[i] <= 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else if (curr_state == STATE_CAL_2 && cnt_chip_in == 2'd2) begin
|
||||||
|
for (i = 0; i < CHANNEL_NUM; i = i + 1) begin
|
||||||
|
if (msb_accum_abs_peak_index[i][cnt_decim] == msb_accum_abs_peak_index[i][0]) begin
|
||||||
|
peak_index_num[i] <= cnt_decim;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
peak_index_num[i] <= peak_index_num[i];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
peak_index_num_valid <= 'b0;
|
||||||
|
end
|
||||||
|
else if (curr_state == STATE_IDLE) begin
|
||||||
|
peak_index_num_valid <= 'b0;
|
||||||
|
end
|
||||||
|
else if (curr_state == STATE_CAL_2 && cnt_chip_in == 2'd2 && cnt_decim == INTERP_FACTOR-1) begin
|
||||||
|
peak_index_num_valid <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
peak_index_num_valid <= 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
peak_index_num_diff <= 'b0;
|
||||||
|
end
|
||||||
|
else if (peak_index_num_valid) begin
|
||||||
|
peak_index_num_diff <= peak_index_num[1] - peak_index_num[0];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
peak_index_num_diff_valid <= 'b0;
|
||||||
|
end
|
||||||
|
else if (curr_state == STATE_IDLE) begin
|
||||||
|
peak_index_num_diff_valid <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
peak_index_num_diff_valid <= peak_index_num_valid;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
//
|
||||||
|
reg [$clog2(PRBS_LEN)-1 : 0] peak_index_plus_minus [0 : 2];
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
for (i = 0; i < 3; i = i + 1) begin
|
||||||
|
peak_index_plus_minus[i] <= 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else if (curr_state == STATE_CAL_2) begin
|
||||||
|
peak_index_plus_minus[0] <= msb_accum_abs_peak_index[0][0];
|
||||||
|
peak_index_plus_minus[1] <= msb_accum_abs_peak_index[0][0] - 1'b1;
|
||||||
|
peak_index_plus_minus[2] <= msb_accum_abs_peak_index[0][0] + 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// get target downsample position
|
||||||
|
localparam CORDIC_LATENCY = 20;
|
||||||
|
|
||||||
|
reg target_accum_index [0 : CHANNEL_NUM-1];
|
||||||
|
reg target_accum_index_valid = 'b0;
|
||||||
|
reg [$clog2(INTERP_FACTOR+CORDIC_LATENCY)-1 : 0] relative_delay = 'b0; // compensate cordic delay
|
||||||
|
reg ad9361_cal_result_buf = 'b0;
|
||||||
|
|
||||||
|
assign ad9361_cal_result = ad9361_cal_result_buf;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
for (i = 0; i < CHANNEL_NUM; i = i + 1) begin
|
||||||
|
target_accum_index[i] <= 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else if (peak_index_num_diff_valid) begin
|
||||||
|
if (msb_accum_abs_peak_index[1][0] == peak_index_plus_minus[0]) begin
|
||||||
|
target_accum_index[0] <= 1'b0;
|
||||||
|
target_accum_index[1] <= 1'b0;
|
||||||
|
relative_delay <= peak_index_num_diff + (CORDIC_LATENCY-1);
|
||||||
|
ad9361_cal_result_buf <= 1'b1;
|
||||||
|
end
|
||||||
|
else if (msb_accum_abs_peak_index[1][0] == peak_index_plus_minus[1]) begin
|
||||||
|
target_accum_index[0] <= 1'b0;
|
||||||
|
target_accum_index[1] <= 1'b1;
|
||||||
|
relative_delay <= peak_index_num_diff + INTERP_FACTOR + (CORDIC_LATENCY-1);
|
||||||
|
ad9361_cal_result_buf <= 1'b1;
|
||||||
|
end
|
||||||
|
else if (msb_accum_abs_peak_index[1][0] == peak_index_plus_minus[2]) begin
|
||||||
|
target_accum_index[0] <= 1'b1;
|
||||||
|
target_accum_index[1] <= 1'b0;
|
||||||
|
relative_delay <= peak_index_num_diff - INTERP_FACTOR + (CORDIC_LATENCY-1);
|
||||||
|
ad9361_cal_result_buf <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
target_accum_index[0] <= 1'b0;
|
||||||
|
target_accum_index[1] <= 1'b0;
|
||||||
|
relative_delay <= peak_index_num_diff + (CORDIC_LATENCY-1);
|
||||||
|
ad9361_cal_result_buf <= 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
for (i = 0; i < CHANNEL_NUM; i = i + 1) begin
|
||||||
|
target_accum_index[i] <= target_accum_index[i];
|
||||||
|
end
|
||||||
|
relative_delay <= relative_delay;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
target_accum_index_valid <= 'b0;
|
||||||
|
end
|
||||||
|
else if (curr_state == STATE_IDLE) begin
|
||||||
|
target_accum_index_valid <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
target_accum_index_valid <= peak_index_num_diff_valid;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
// get target data
|
||||||
|
reg [DATA_ACCUM_LEN-1 : 0] rx_i_accum_target [0 : CHANNEL_NUM-1];
|
||||||
|
reg [DATA_ACCUM_LEN-1 : 0] rx_q_accum_target [0 : CHANNEL_NUM-1];
|
||||||
|
reg rx_accum_target_valid = 'b0;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
for (i = 0; i < CHANNEL_NUM; i = i + 1) begin
|
||||||
|
rx_i_accum_target[i] <= 'b0;
|
||||||
|
rx_q_accum_target[i] <= 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else if (target_accum_index_valid) begin
|
||||||
|
for (i = 0; i < CHANNEL_NUM; i = i + 1) begin
|
||||||
|
rx_i_accum_target[i] <= rx_i_accum[i][target_accum_index[i]];
|
||||||
|
rx_q_accum_target[i] <= rx_q_accum[i][target_accum_index[i]];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
rx_accum_target_valid <= 'b0;
|
||||||
|
end
|
||||||
|
else if (curr_state == STATE_IDLE) begin
|
||||||
|
rx_accum_target_valid <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
rx_accum_target_valid <= target_accum_index_valid;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// calculate phase difference
|
||||||
|
localparam AXIS_CORDIC_WIDTH = 8*((CORDIC_WIDTH-1)/8+1);
|
||||||
|
|
||||||
|
wire [AXIS_CORDIC_WIDTH-1 : 0] atan2_data_real [0 : CHANNEL_NUM-1];
|
||||||
|
wire [AXIS_CORDIC_WIDTH-1 : 0] atan2_data_imag [0 : CHANNEL_NUM-1];
|
||||||
|
|
||||||
|
wire [2*AXIS_CORDIC_WIDTH-1:0] atan2_data [0 : CHANNEL_NUM-1];
|
||||||
|
wire atan2_valid_i [0 : CHANNEL_NUM-1];
|
||||||
|
|
||||||
|
wire signed [AXIS_CORDIC_WIDTH-1:0] atan2_phase [0 : CHANNEL_NUM-1];
|
||||||
|
wire atan2_valid_o [0 : CHANNEL_NUM-1];
|
||||||
|
|
||||||
|
generate
|
||||||
|
for (m = 0; m < CHANNEL_NUM; m = m + 1) begin
|
||||||
|
|
||||||
|
assign atan2_data_real[m] = (DATA_ACCUM_LEN > AXIS_CORDIC_WIDTH) ? rx_i_accum_target[m][DATA_ACCUM_LEN-1 -: AXIS_CORDIC_WIDTH] : {{(AXIS_CORDIC_WIDTH-DATA_ACCUM_LEN){rx_i_accum_target[m][DATA_ACCUM_LEN-1]}},rx_i_accum_target[m]};
|
||||||
|
assign atan2_data_imag[m] = (DATA_ACCUM_LEN > AXIS_CORDIC_WIDTH) ? rx_q_accum_target[m][DATA_ACCUM_LEN-1 -: AXIS_CORDIC_WIDTH] : {{(AXIS_CORDIC_WIDTH-DATA_ACCUM_LEN){rx_q_accum_target[m][DATA_ACCUM_LEN-1]}},rx_q_accum_target[m]};
|
||||||
|
|
||||||
|
assign atan2_data[m] = {atan2_data_imag[m],atan2_data_real[m]};
|
||||||
|
assign atan2_valid_i[m] = rx_accum_target_valid;
|
||||||
|
|
||||||
|
atan2_16b u_atan2
|
||||||
|
(
|
||||||
|
.aclk (clk ), // input wire aclk
|
||||||
|
.s_axis_cartesian_tvalid(atan2_valid_i[m] ), // input wire s_axis_cartesian_tvalid
|
||||||
|
.s_axis_cartesian_tdata (atan2_data[m] ), // input wire [31 : 0] s_axis_cartesian_tdata
|
||||||
|
.m_axis_dout_tvalid (atan2_valid_o[m] ), // output wire m_axis_dout_tvalid
|
||||||
|
.m_axis_dout_tdata (atan2_phase[m] ) // output wire [15 : 0] m_axis_dout_tdata
|
||||||
|
);
|
||||||
|
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
reg signed [AXIS_CORDIC_WIDTH-1:0] phase_diff_raw = 'b0;
|
||||||
|
reg phase_diff_raw_valid = 'b0;
|
||||||
|
|
||||||
|
reg signed [AXIS_CORDIC_WIDTH-1:0] phase_diff = 'b0;
|
||||||
|
reg phase_diff_valid = 'b0;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
phase_diff_raw <= 'b0;
|
||||||
|
end
|
||||||
|
else if (atan2_valid_o[0]) begin
|
||||||
|
// here calculate the phase difference from target channel to another channel,
|
||||||
|
// then rotate another channel to target channel
|
||||||
|
phase_diff_raw <= atan2_phase[0] - atan2_phase[1];
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
phase_diff_raw <= phase_diff_raw;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
phase_diff_raw_valid <= 'b0;
|
||||||
|
end
|
||||||
|
else if (curr_state == STATE_IDLE) begin
|
||||||
|
phase_diff_raw_valid <= 'b0;
|
||||||
|
end
|
||||||
|
else if (atan2_valid_o[0]) begin
|
||||||
|
phase_diff_raw_valid <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
phase_diff_raw_valid <= phase_diff_raw_valid;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
phase_diff <= 'b0;
|
||||||
|
end
|
||||||
|
else if (phase_diff_raw_valid) begin
|
||||||
|
if (phase_diff_raw > POS_PI_2Q13_SCALED) begin
|
||||||
|
phase_diff <= phase_diff_raw - (2*POS_PI_2Q13_SCALED);
|
||||||
|
end
|
||||||
|
else if (phase_diff_raw < NEG_PI_2Q13_SCALED) begin
|
||||||
|
phase_diff <= phase_diff_raw + (2*POS_PI_2Q13_SCALED);
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
phase_diff <= phase_diff_raw;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
phase_diff_valid <= 'b0;
|
||||||
|
end
|
||||||
|
else if (curr_state == STATE_IDLE) begin
|
||||||
|
phase_diff_valid <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
phase_diff_valid <= phase_diff_raw_valid;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// rotate the 3rd and 4th channel
|
||||||
|
wire rotate_phase_valid;
|
||||||
|
wire [AXIS_CORDIC_WIDTH-1 : 0] rotate_phase_data;
|
||||||
|
|
||||||
|
wire rotate_cart_valid;
|
||||||
|
wire [AXIS_CORDIC_WIDTH-1 : 0] rotate_cart_ch3_data_real;
|
||||||
|
wire [AXIS_CORDIC_WIDTH-1 : 0] rotate_cart_ch3_data_imag;
|
||||||
|
wire [AXIS_CORDIC_WIDTH-1 : 0] rotate_cart_ch4_data_real;
|
||||||
|
wire [AXIS_CORDIC_WIDTH-1 : 0] rotate_cart_ch4_data_imag;
|
||||||
|
wire [2*AXIS_CORDIC_WIDTH-1 : 0] rotate_cart_ch3_data;
|
||||||
|
wire [2*AXIS_CORDIC_WIDTH-1 : 0] rotate_cart_ch4_data;
|
||||||
|
|
||||||
|
wire rotate_dout_ch3_valid;
|
||||||
|
wire rotate_dout_ch4_valid;
|
||||||
|
wire [2*AXIS_CORDIC_WIDTH-1 : 0] rotate_dout_ch3_data;
|
||||||
|
wire [2*AXIS_CORDIC_WIDTH-1 : 0] rotate_dout_ch4_data;
|
||||||
|
wire [AXIS_CORDIC_WIDTH-1 : 0] rx_ch3_rotate_i;
|
||||||
|
wire [AXIS_CORDIC_WIDTH-1 : 0] rx_ch3_rotate_q;
|
||||||
|
wire [AXIS_CORDIC_WIDTH-1 : 0] rx_ch4_rotate_i;
|
||||||
|
wire [AXIS_CORDIC_WIDTH-1 : 0] rx_ch4_rotate_q;
|
||||||
|
|
||||||
|
assign rotate_phase_valid = phase_diff_valid;
|
||||||
|
assign rotate_phase_data = phase_diff;
|
||||||
|
|
||||||
|
assign rotate_cart_valid = 1'b1;
|
||||||
|
assign rotate_cart_ch3_data_real = (ADC_DATA_WIDTH > AXIS_CORDIC_WIDTH) ? rx_ch3_i[ADC_DATA_WIDTH-1 -: AXIS_CORDIC_WIDTH] : {rx_ch3_i,{(AXIS_CORDIC_WIDTH-ADC_DATA_WIDTH){1'b0}}};
|
||||||
|
assign rotate_cart_ch3_data_imag = (ADC_DATA_WIDTH > AXIS_CORDIC_WIDTH) ? rx_ch3_q[ADC_DATA_WIDTH-1 -: AXIS_CORDIC_WIDTH] : {rx_ch3_q,{(AXIS_CORDIC_WIDTH-ADC_DATA_WIDTH){1'b0}}};
|
||||||
|
assign rotate_cart_ch4_data_real = (ADC_DATA_WIDTH > AXIS_CORDIC_WIDTH) ? rx_ch4_i[ADC_DATA_WIDTH-1 -: AXIS_CORDIC_WIDTH] : {rx_ch4_i,{(AXIS_CORDIC_WIDTH-ADC_DATA_WIDTH){1'b0}}};
|
||||||
|
assign rotate_cart_ch4_data_imag = (ADC_DATA_WIDTH > AXIS_CORDIC_WIDTH) ? rx_ch4_q[ADC_DATA_WIDTH-1 -: AXIS_CORDIC_WIDTH] : {rx_ch4_q,{(AXIS_CORDIC_WIDTH-ADC_DATA_WIDTH){1'b0}}};
|
||||||
|
|
||||||
|
assign rotate_cart_ch3_data = {rotate_cart_ch3_data_imag,rotate_cart_ch3_data_real};
|
||||||
|
assign rotate_cart_ch4_data = {rotate_cart_ch4_data_imag,rotate_cart_ch4_data_real};
|
||||||
|
|
||||||
|
assign {rx_ch3_rotate_q,rx_ch3_rotate_i} = rotate_dout_ch3_data;
|
||||||
|
assign {rx_ch4_rotate_q,rx_ch4_rotate_i} = rotate_dout_ch4_data;
|
||||||
|
|
||||||
|
rotate_16b u_rotate_16b_ch3
|
||||||
|
(
|
||||||
|
.aclk (clk ), // input wire aclk
|
||||||
|
.s_axis_phase_tvalid (rotate_phase_valid ), // input wire s_axis_phase_tvalid
|
||||||
|
.s_axis_phase_tdata (rotate_phase_data ), // input wire [15 : 0] s_axis_phase_tdata
|
||||||
|
.s_axis_cartesian_tvalid(rotate_cart_valid ), // input wire s_axis_cartesian_tvalid
|
||||||
|
.s_axis_cartesian_tdata (rotate_cart_ch3_data ), // input wire [31 : 0] s_axis_cartesian_tdata
|
||||||
|
.m_axis_dout_tvalid (rotate_dout_ch3_valid ), // output wire m_axis_dout_tvalid
|
||||||
|
.m_axis_dout_tdata (rotate_dout_ch3_data ) // output wire [31 : 0] m_axis_dout_tdata
|
||||||
|
);
|
||||||
|
|
||||||
|
rotate_16b u_rotate_16b_ch4
|
||||||
|
(
|
||||||
|
.aclk (clk ), // input wire aclk
|
||||||
|
.s_axis_phase_tvalid (rotate_phase_valid ), // input wire s_axis_phase_tvalid
|
||||||
|
.s_axis_phase_tdata (rotate_phase_data ), // input wire [15 : 0] s_axis_phase_tdata
|
||||||
|
.s_axis_cartesian_tvalid(rotate_cart_valid ), // input wire s_axis_cartesian_tvalid
|
||||||
|
.s_axis_cartesian_tdata (rotate_cart_ch4_data ), // input wire [31 : 0] s_axis_cartesian_tdata
|
||||||
|
.m_axis_dout_tvalid (rotate_dout_ch4_valid ), // output wire m_axis_dout_tvalid
|
||||||
|
.m_axis_dout_tdata (rotate_dout_ch4_data ) // output wire [31 : 0] m_axis_dout_tdata
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
localparam TOTAL_LATENCY = CORDIC_LATENCY+INTERP_FACTOR-1;
|
||||||
|
|
||||||
|
reg [ADC_DATA_WIDTH-1 : 0] rx_ch1_i_delay [0 : TOTAL_LATENCY-1];
|
||||||
|
reg [ADC_DATA_WIDTH-1 : 0] rx_ch1_q_delay [0 : TOTAL_LATENCY-1];
|
||||||
|
reg [ADC_DATA_WIDTH-1 : 0] rx_ch2_i_delay [0 : TOTAL_LATENCY-1];
|
||||||
|
reg [ADC_DATA_WIDTH-1 : 0] rx_ch2_q_delay [0 : TOTAL_LATENCY-1];
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
for (i = 0; i < TOTAL_LATENCY; i = i + 1) begin
|
||||||
|
rx_ch1_i_delay[i] <= 'b0;
|
||||||
|
rx_ch1_q_delay[i] <= 'b0;
|
||||||
|
rx_ch2_i_delay[i] <= 'b0;
|
||||||
|
rx_ch2_q_delay[i] <= 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
for (i = 1; i < TOTAL_LATENCY; i = i + 1) begin
|
||||||
|
rx_ch1_i_delay[i] <= rx_ch1_i_delay[i-1];
|
||||||
|
rx_ch1_q_delay[i] <= rx_ch1_q_delay[i-1];
|
||||||
|
rx_ch2_i_delay[i] <= rx_ch2_i_delay[i-1];
|
||||||
|
rx_ch2_q_delay[i] <= rx_ch2_q_delay[i-1];
|
||||||
|
end
|
||||||
|
rx_ch1_i_delay[0] <= rx_ch1_i;
|
||||||
|
rx_ch1_q_delay[0] <= rx_ch1_q;
|
||||||
|
rx_ch2_i_delay[0] <= rx_ch2_i;
|
||||||
|
rx_ch2_q_delay[0] <= rx_ch2_q;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch1_i_buf = 'b0;
|
||||||
|
reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch1_q_buf = 'b0;
|
||||||
|
reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch2_i_buf = 'b0;
|
||||||
|
reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch2_q_buf = 'b0;
|
||||||
|
reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch3_i_buf = 'b0;
|
||||||
|
reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch3_q_buf = 'b0;
|
||||||
|
reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch4_i_buf = 'b0;
|
||||||
|
reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch4_q_buf = 'b0;
|
||||||
|
|
||||||
|
assign rx_cal_ch1_i = rx_cal_ch1_i_buf;
|
||||||
|
assign rx_cal_ch1_q = rx_cal_ch1_q_buf;
|
||||||
|
assign rx_cal_ch2_i = rx_cal_ch2_i_buf;
|
||||||
|
assign rx_cal_ch2_q = rx_cal_ch2_q_buf;
|
||||||
|
assign rx_cal_ch3_i = rx_cal_ch3_i_buf;
|
||||||
|
assign rx_cal_ch3_q = rx_cal_ch3_q_buf;
|
||||||
|
assign rx_cal_ch4_i = rx_cal_ch4_i_buf;
|
||||||
|
assign rx_cal_ch4_q = rx_cal_ch4_q_buf;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
rx_cal_ch1_i_buf <= 'b0;
|
||||||
|
rx_cal_ch1_q_buf <= 'b0;
|
||||||
|
rx_cal_ch2_i_buf <= 'b0;
|
||||||
|
rx_cal_ch2_q_buf <= 'b0;
|
||||||
|
rx_cal_ch3_i_buf <= 'b0;
|
||||||
|
rx_cal_ch3_q_buf <= 'b0;
|
||||||
|
rx_cal_ch4_i_buf <= 'b0;
|
||||||
|
rx_cal_ch4_q_buf <= 'b0;
|
||||||
|
end
|
||||||
|
else if (rotate_dout_ch3_valid) begin
|
||||||
|
rx_cal_ch1_i_buf <= rx_ch1_i_delay[relative_delay];
|
||||||
|
rx_cal_ch1_q_buf <= rx_ch1_q_delay[relative_delay];
|
||||||
|
rx_cal_ch2_i_buf <= -rx_ch2_i_delay[relative_delay];
|
||||||
|
rx_cal_ch2_q_buf <= -rx_ch2_q_delay[relative_delay];
|
||||||
|
rx_cal_ch3_i_buf <= rx_ch3_rotate_i[AXIS_CORDIC_WIDTH-1 -: ADC_DATA_WIDTH];
|
||||||
|
rx_cal_ch3_q_buf <= rx_ch3_rotate_q[AXIS_CORDIC_WIDTH-1 -: ADC_DATA_WIDTH];
|
||||||
|
rx_cal_ch4_i_buf <= -rx_ch4_rotate_i[AXIS_CORDIC_WIDTH-1 -: ADC_DATA_WIDTH];
|
||||||
|
rx_cal_ch4_q_buf <= -rx_ch4_rotate_q[AXIS_CORDIC_WIDTH-1 -: ADC_DATA_WIDTH];
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
rx_cal_ch1_i_buf <= rx_ch1_i;
|
||||||
|
rx_cal_ch1_q_buf <= rx_ch1_q;
|
||||||
|
rx_cal_ch2_i_buf <= rx_ch2_i;
|
||||||
|
rx_cal_ch2_q_buf <= rx_ch2_q;
|
||||||
|
rx_cal_ch3_i_buf <= rx_ch3_i;
|
||||||
|
rx_cal_ch3_q_buf <= rx_ch3_q;
|
||||||
|
rx_cal_ch4_i_buf <= rx_ch4_i;
|
||||||
|
rx_cal_ch4_q_buf <= rx_ch4_q;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
//
|
||||||
|
reg ad9361_2_cal_done_buf = 'b0;
|
||||||
|
|
||||||
|
assign ad9361_2_cal_done = ad9361_2_cal_done_buf;
|
||||||
|
assign ad9361_cal_valid = ad9361_2_cal_done_buf;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
ad9361_2_cal_done_buf <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
ad9361_2_cal_done_buf <= rotate_dout_ch3_valid;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,321 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||||
|
<!-- -->
|
||||||
|
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||||
|
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||||
|
|
||||||
|
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/Workspace/vivado/vivado_pub/modules/xc7k410tffg900-2/multi_ch_cal/multi_ch_cal.xpr">
|
||||||
|
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||||
|
<Configuration>
|
||||||
|
<Option Name="Id" Val="3d8cac293e8046f6ba9154243a7267d4"/>
|
||||||
|
<Option Name="Part" Val="xc7k410tffg900-2"/>
|
||||||
|
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||||
|
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||||
|
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||||
|
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||||
|
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||||
|
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||||
|
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||||
|
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||||
|
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||||
|
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||||
|
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||||
|
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||||
|
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||||
|
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||||
|
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||||
|
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||||
|
<Option Name="BoardPart" Val=""/>
|
||||||
|
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||||
|
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="ProjectType" Val="Default"/>
|
||||||
|
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||||
|
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||||
|
<Option Name="IPCachePermission" Val="read"/>
|
||||||
|
<Option Name="IPCachePermission" Val="write"/>
|
||||||
|
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||||
|
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||||
|
<Option Name="SimCompileState" Val="TRUE"/>
|
||||||
|
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||||
|
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||||
|
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||||
|
<Option Name="EnableBDX" Val="FALSE"/>
|
||||||
|
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||||
|
<Option Name="WTXSimLaunchSim" Val="3"/>
|
||||||
|
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTXSimExportSim" Val="2"/>
|
||||||
|
<Option Name="WTModelSimExportSim" Val="2"/>
|
||||||
|
<Option Name="WTQuestaExportSim" Val="2"/>
|
||||||
|
<Option Name="WTIesExportSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsExportSim" Val="2"/>
|
||||||
|
<Option Name="WTRivieraExportSim" Val="2"/>
|
||||||
|
<Option Name="WTActivehdlExportSim" Val="2"/>
|
||||||
|
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||||
|
<Option Name="XSimRadix" Val="hex"/>
|
||||||
|
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||||
|
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||||
|
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||||
|
<Option Name="SimTypes" Val="rtl"/>
|
||||||
|
<Option Name="SimTypes" Val="bfm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||||
|
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||||
|
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||||
|
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||||
|
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||||
|
</Configuration>
|
||||||
|
<FileSets Version="1" Minor="32">
|
||||||
|
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||||
|
<Filter Type="Srcs"/>
|
||||||
|
<File Path="$PPRDIR/../../../common/ApproxModuli_26bit.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/multi_ch_cal.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="multi_ch_cal"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||||
|
<Filter Type="Constrs"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="ConstrsType" Val="XDC"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||||
|
<File Path="$PSRCDIR/sim_1/new/tb_multi_ch_cal.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="tb_multi_ch_cal"/>
|
||||||
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
<Option Name="TransportPathDelay" Val="0"/>
|
||||||
|
<Option Name="TransportIntDelay" Val="0"/>
|
||||||
|
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||||
|
<Option Name="PamDesignTestbench" Val=""/>
|
||||||
|
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||||
|
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||||
|
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||||
|
<Option Name="SrcSet" Val="sources_1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||||
|
<Filter Type="Utils"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="atan2_16b" Type="BlockSrcs" RelSrcDir="$PSRCDIR/atan2_16b" RelGenDir="$PGENDIR/atan2_16b">
|
||||||
|
<File Path="$PSRCDIR/sources_1/ip/atan2_16b/atan2_16b.xci">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopModule" Val="atan2_16b"/>
|
||||||
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="rotate_16b" Type="BlockSrcs" RelSrcDir="$PSRCDIR/rotate_16b" RelGenDir="$PGENDIR/rotate_16b">
|
||||||
|
<File Path="$PSRCDIR/sources_1/ip/rotate_16b/rotate_16b.xci">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopModule" Val="rotate_16b"/>
|
||||||
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
</FileSets>
|
||||||
|
<Simulators>
|
||||||
|
<Simulator Name="XSim">
|
||||||
|
<Option Name="Description" Val="Vivado Simulator"/>
|
||||||
|
<Option Name="CompiledLib" Val="0"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ModelSim">
|
||||||
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Questa">
|
||||||
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Xcelium">
|
||||||
|
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="VCS">
|
||||||
|
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Riviera">
|
||||||
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
</Simulators>
|
||||||
|
<Runs Version="1" Minor="21">
|
||||||
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="atan2_16b_synth_1" Type="Ft3:Synth" SrcSet="atan2_16b" Part="xc7k410tffg900-2" ConstrsSet="atan2_16b" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/atan2_16b_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/atan2_16b_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/atan2_16b_synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="rotate_16b_synth_1" Type="Ft3:Synth" SrcSet="rotate_16b" Part="xc7k410tffg900-2" ConstrsSet="rotate_16b" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/rotate_16b_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/rotate_16b_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/rotate_16b_synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="atan2_16b_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="atan2_16b" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="atan2_16b_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/atan2_16b_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/atan2_16b_impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="rotate_16b_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="rotate_16b" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="rotate_16b_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/rotate_16b_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/rotate_16b_impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
</Runs>
|
||||||
|
<Board/>
|
||||||
|
<DashboardSummary Version="1" Minor="0">
|
||||||
|
<Dashboards>
|
||||||
|
<Dashboard Name="default_dashboard">
|
||||||
|
<Gadgets>
|
||||||
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||||
|
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||||
|
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
</Gadgets>
|
||||||
|
</Dashboard>
|
||||||
|
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||||
|
</Dashboards>
|
||||||
|
</DashboardSummary>
|
||||||
|
</Project>
|
||||||
@@ -0,0 +1,130 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Company:
|
||||||
|
// Engineer:
|
||||||
|
// _ _ ____
|
||||||
|
// | | ___ ___| |__ / ___| __ _ ___
|
||||||
|
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||||
|
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||||
|
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||||
|
|
||||||
|
// Create Date: 2020/12/08 12:43:46
|
||||||
|
// Design Name:
|
||||||
|
// Module Name: tb_tx_qpsk
|
||||||
|
// Project Name:
|
||||||
|
// Target Devices:
|
||||||
|
// Tool Versions:
|
||||||
|
// Description:
|
||||||
|
//
|
||||||
|
// Dependencies:
|
||||||
|
//
|
||||||
|
// Revision:
|
||||||
|
// Revision 0.01 - File Created
|
||||||
|
// Additional Comments:
|
||||||
|
//
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
|
module tb_tx_qpsk;
|
||||||
|
|
||||||
|
reg clk = 1'b0 ;
|
||||||
|
reg rst = 1'b1 ;
|
||||||
|
reg tx_on = 1'b1 ;
|
||||||
|
reg [31:0] freq_set ;
|
||||||
|
reg [ 1:0] waveform_sel = 2'd1 ;
|
||||||
|
reg [ 1:0] iq_sel = 2'b11 ;
|
||||||
|
wire [11:0] tx_data_i ;
|
||||||
|
wire [11:0] tx_data_q ;
|
||||||
|
reg [ 3:0] bb_rshift = 5'b0 ;
|
||||||
|
|
||||||
|
tx_qpsk u_tx_qpsk
|
||||||
|
(
|
||||||
|
.clk (clk ),
|
||||||
|
.rst (rst ),
|
||||||
|
.tx_data_i (tx_data_i ),
|
||||||
|
.tx_data_q (tx_data_q ),
|
||||||
|
.waveform_sel (waveform_sel ),
|
||||||
|
.sweep_on (1'b0 ),
|
||||||
|
// .freq_set (32'd447392426 ),
|
||||||
|
.freq_set (32'd0 ),
|
||||||
|
.iq_sel (iq_sel ),
|
||||||
|
.bb_rshift (bb_rshift )
|
||||||
|
);
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
#102
|
||||||
|
rst = 1'b0;
|
||||||
|
// freq_set = 32'd873813333;
|
||||||
|
// waveform_sel = 2'b00;
|
||||||
|
// bb_rshift = 5'd0;
|
||||||
|
// #5000
|
||||||
|
// bb_rshift = 5'd1;
|
||||||
|
// #5000
|
||||||
|
// bb_rshift = 5'd2;
|
||||||
|
// #5000
|
||||||
|
// bb_rshift = 5'd3;
|
||||||
|
// #5000
|
||||||
|
// bb_rshift = 5'd4;
|
||||||
|
// #5000
|
||||||
|
// bb_rshift = 5'd5;
|
||||||
|
// #5000
|
||||||
|
// bb_rshift = 5'd6;
|
||||||
|
// #5000
|
||||||
|
// bb_rshift = 5'd7;
|
||||||
|
// #5000
|
||||||
|
// bb_rshift = 5'd8;
|
||||||
|
// #5000
|
||||||
|
// bb_rshift = 5'd9;
|
||||||
|
// #5000
|
||||||
|
// bb_rshift = 5'd14;
|
||||||
|
// #5000
|
||||||
|
// bb_rshift = 5'd15;
|
||||||
|
// #5000
|
||||||
|
// bb_rshift = 5'd16;
|
||||||
|
// freq_set = 32'd0;
|
||||||
|
// func_sel = 3'b010;
|
||||||
|
// #7777
|
||||||
|
// freq_set = 32'd536870912;
|
||||||
|
// func_sel = 3'b100;
|
||||||
|
// #7777
|
||||||
|
// freq_set = 32'd0;
|
||||||
|
// func_sel = 3'b100;
|
||||||
|
// #7777
|
||||||
|
// freq_set = 32'd536870912;
|
||||||
|
// func_sel = 3'b010;
|
||||||
|
// #7777
|
||||||
|
// freq_set = 32'd0;
|
||||||
|
// func_sel = 3'b010;
|
||||||
|
// freq_set = 32'd536870912;
|
||||||
|
// iq_sel = 2'b00;
|
||||||
|
// #7777
|
||||||
|
// freq_set = 32'd536870912;
|
||||||
|
// iq_sel = 2'b01;
|
||||||
|
// #7777
|
||||||
|
// freq_set = 32'd536870912;
|
||||||
|
// iq_sel = 2'b10;
|
||||||
|
// #7777
|
||||||
|
// freq_set = 32'd536870912;
|
||||||
|
// iq_sel = 2'b11;
|
||||||
|
end
|
||||||
|
|
||||||
|
always #5 clk = ~clk;
|
||||||
|
|
||||||
|
// integer i;
|
||||||
|
// integer w_file;
|
||||||
|
|
||||||
|
// initial begin
|
||||||
|
// w_file = $fopen("D:\\qpsk_josh.txt","w");
|
||||||
|
// for (i = 0; i <= 35000; i = i + 1) begin
|
||||||
|
// wait(clk);
|
||||||
|
// #10;
|
||||||
|
// $fdisplay(w_file,"%d %d",$signed(tx_data_i),
|
||||||
|
// $signed(tx_data_q));
|
||||||
|
// if (i == 35000) begin
|
||||||
|
// $fclose(w_file);
|
||||||
|
// $stop;
|
||||||
|
// end
|
||||||
|
// end
|
||||||
|
// end
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,212 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "cmpy_18x8",
|
||||||
|
"component_reference": "xilinx.com:ip:cmpy:6.0",
|
||||||
|
"ip_revision": "22",
|
||||||
|
"gen_directory": "../../../../tx_qpsk.gen/sources_1/ip/cmpy_18x8",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"Component_Name": [ { "value": "cmpy_18x8", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"APortWidth": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"HasATLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"HasATUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"ATUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"BPortWidth": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"HasBTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"HasBTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"BTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"MultType": [ { "value": "Use_LUTs", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"OptimizeGoal": [ { "value": "Resources", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"FlowControl": [ { "value": "NonBlocking", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"RoundMode": [ { "value": "Truncate", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"OutputWidth": [ { "value": "27", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"HasCTRLTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"HasCTRLTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CTRLTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"OutTLASTBehv": [ { "value": "Null", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"LatencyConfig": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"MinimumLatency": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"ARESETN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_XDEVICEFAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_XDEVICE": [ { "value": "xc7k410t", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_A_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_B_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_OUT_WIDTH": [ { "value": "27", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LATENCY": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MULT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_OPTIMIZE_GOAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"HAS_NEGATE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"SINGLE_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"ROUND": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"USE_DSP_CASCADES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_THROTTLE_SCHEME": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_ARESETN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_S_AXIS_A_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_S_AXIS_A_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_S_AXIS_B_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_S_AXIS_B_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_S_AXIS_CTRL_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_S_AXIS_CTRL_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_TLAST_RESOLUTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXIS_A_TDATA_WIDTH": [ { "value": "48", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXIS_A_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXIS_B_TDATA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXIS_B_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXIS_CTRL_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXIS_CTRL_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXIS_DOUT_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXIS_DOUT_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "kintex7" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xc7k410t" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffg900" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||||
|
"IPREVISION": [ { "value": "22" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../tx_qpsk.gen/sources_1/ip/cmpy_18x8" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "." } ],
|
||||||
|
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axis_a_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axis_a_tdata": [ { "direction": "in", "size_left": "47", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"s_axis_b_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axis_b_tdata": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"m_axis_dout_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||||
|
"m_axis_dout_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"M_AXIS_DOUT": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "m_axis_dout_tdata" } ],
|
||||||
|
"TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"aclk_intf": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CTRL:S_AXIS_B:S_AXIS_A:M_AXIS_DOUT", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "aclk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"aresetn_intf": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"aclken_intf": {
|
||||||
|
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"S_AXIS_A": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "6", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "s_axis_a_tdata" } ],
|
||||||
|
"TVALID": [ { "physical_name": "s_axis_a_tvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"S_AXIS_B": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "s_axis_b_tdata" } ],
|
||||||
|
"TVALID": [ { "physical_name": "s_axis_b_tvalid" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,771 @@
|
|||||||
|
RADIX = 10;
|
||||||
|
COEFDATA =
|
||||||
|
-47,
|
||||||
|
-30,
|
||||||
|
-13,
|
||||||
|
4,
|
||||||
|
21,
|
||||||
|
38,
|
||||||
|
56,
|
||||||
|
73,
|
||||||
|
89,
|
||||||
|
106,
|
||||||
|
122,
|
||||||
|
138,
|
||||||
|
153,
|
||||||
|
168,
|
||||||
|
182,
|
||||||
|
196,
|
||||||
|
209,
|
||||||
|
221,
|
||||||
|
232,
|
||||||
|
243,
|
||||||
|
252,
|
||||||
|
261,
|
||||||
|
268,
|
||||||
|
275,
|
||||||
|
281,
|
||||||
|
285,
|
||||||
|
289,
|
||||||
|
291,
|
||||||
|
292,
|
||||||
|
292,
|
||||||
|
291,
|
||||||
|
288,
|
||||||
|
285,
|
||||||
|
280,
|
||||||
|
274,
|
||||||
|
267,
|
||||||
|
259,
|
||||||
|
249,
|
||||||
|
239,
|
||||||
|
228,
|
||||||
|
215,
|
||||||
|
202,
|
||||||
|
187,
|
||||||
|
172,
|
||||||
|
156,
|
||||||
|
139,
|
||||||
|
122,
|
||||||
|
104,
|
||||||
|
85,
|
||||||
|
66,
|
||||||
|
46,
|
||||||
|
26,
|
||||||
|
5,
|
||||||
|
-15,
|
||||||
|
-36,
|
||||||
|
-56,
|
||||||
|
-77,
|
||||||
|
-98,
|
||||||
|
-118,
|
||||||
|
-138,
|
||||||
|
-158,
|
||||||
|
-177,
|
||||||
|
-195,
|
||||||
|
-213,
|
||||||
|
-231,
|
||||||
|
-247,
|
||||||
|
-263,
|
||||||
|
-277,
|
||||||
|
-291,
|
||||||
|
-303,
|
||||||
|
-314,
|
||||||
|
-325,
|
||||||
|
-333,
|
||||||
|
-341,
|
||||||
|
-347,
|
||||||
|
-351,
|
||||||
|
-354,
|
||||||
|
-356,
|
||||||
|
-356,
|
||||||
|
-354,
|
||||||
|
-351,
|
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|
-346,
|
||||||
|
-340,
|
||||||
|
-332,
|
||||||
|
-322,
|
||||||
|
-311,
|
||||||
|
-298,
|
||||||
|
-284,
|
||||||
|
-268,
|
||||||
|
-250,
|
||||||
|
-231,
|
||||||
|
-211,
|
||||||
|
-189,
|
||||||
|
-166,
|
||||||
|
-142,
|
||||||
|
-117,
|
||||||
|
-90,
|
||||||
|
-63,
|
||||||
|
-35,
|
||||||
|
-6,
|
||||||
|
24,
|
||||||
|
54,
|
||||||
|
85,
|
||||||
|
116,
|
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|
147,
|
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|
179,
|
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|
210,
|
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|
242,
|
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|
273,
|
||||||
|
304,
|
||||||
|
334,
|
||||||
|
363,
|
||||||
|
392,
|
||||||
|
420,
|
||||||
|
447,
|
||||||
|
473,
|
||||||
|
497,
|
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|
520,
|
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|
542,
|
||||||
|
562,
|
||||||
|
580,
|
||||||
|
596,
|
||||||
|
611,
|
||||||
|
623,
|
||||||
|
633,
|
||||||
|
641,
|
||||||
|
647,
|
||||||
|
650,
|
||||||
|
650,
|
||||||
|
649,
|
||||||
|
644,
|
||||||
|
637,
|
||||||
|
627,
|
||||||
|
615,
|
||||||
|
600,
|
||||||
|
582,
|
||||||
|
562,
|
||||||
|
538,
|
||||||
|
513,
|
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|
484,
|
||||||
|
453,
|
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|
419,
|
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|
383,
|
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|
345,
|
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|
304,
|
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|
261,
|
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|
216,
|
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|
169,
|
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|
119,
|
||||||
|
69,
|
||||||
|
16,
|
||||||
|
-38,
|
||||||
|
-93,
|
||||||
|
-150,
|
||||||
|
-207,
|
||||||
|
-265,
|
||||||
|
-324,
|
||||||
|
-383,
|
||||||
|
-443,
|
||||||
|
-502,
|
||||||
|
-562,
|
||||||
|
-621,
|
||||||
|
-679,
|
||||||
|
-736,
|
||||||
|
-793,
|
||||||
|
-848,
|
||||||
|
-902,
|
||||||
|
-954,
|
||||||
|
-1004,
|
||||||
|
-1052,
|
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|
-1097,
|
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|
-1140,
|
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|
-1181,
|
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|
-1218,
|
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|
-1252,
|
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|
-1283,
|
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|
-1310,
|
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|
-1333,
|
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|
-1353,
|
||||||
|
-1369,
|
||||||
|
-1380,
|
||||||
|
-1387,
|
||||||
|
-1389,
|
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|
-1387,
|
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|
-1381,
|
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|
-1369,
|
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|
-1353,
|
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|
-1332,
|
||||||
|
-1306,
|
||||||
|
-1274,
|
||||||
|
-1238,
|
||||||
|
-1197,
|
||||||
|
-1151,
|
||||||
|
-1100,
|
||||||
|
-1044,
|
||||||
|
-983,
|
||||||
|
-918,
|
||||||
|
-848,
|
||||||
|
-773,
|
||||||
|
-694,
|
||||||
|
-611,
|
||||||
|
-524,
|
||||||
|
-432,
|
||||||
|
-337,
|
||||||
|
-239,
|
||||||
|
-137,
|
||||||
|
-33,
|
||||||
|
74,
|
||||||
|
184,
|
||||||
|
296,
|
||||||
|
410,
|
||||||
|
525,
|
||||||
|
642,
|
||||||
|
759,
|
||||||
|
877,
|
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|
995,
|
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|
1113,
|
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|
1230,
|
||||||
|
1346,
|
||||||
|
1461,
|
||||||
|
1575,
|
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|
1686,
|
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|
1794,
|
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|
1900,
|
||||||
|
2002,
|
||||||
|
2101,
|
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|
2195,
|
||||||
|
2285,
|
||||||
|
2371,
|
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|
2451,
|
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|
2525,
|
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|
2593,
|
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|
2655,
|
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|
2711,
|
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|
2759,
|
||||||
|
2800,
|
||||||
|
2833,
|
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|
2859,
|
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|
2876,
|
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|
2885,
|
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|
2886,
|
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|
2877,
|
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|
2860,
|
||||||
|
2833,
|
||||||
|
2798,
|
||||||
|
2752,
|
||||||
|
2698,
|
||||||
|
2633,
|
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|
2559,
|
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|
2476,
|
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|
2382,
|
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|
2280,
|
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|
2168,
|
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|
2046,
|
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|
1915,
|
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|
1775,
|
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|
1627,
|
||||||
|
1469,
|
||||||
|
1304,
|
||||||
|
1130,
|
||||||
|
948,
|
||||||
|
759,
|
||||||
|
563,
|
||||||
|
360,
|
||||||
|
151,
|
||||||
|
-64,
|
||||||
|
-284,
|
||||||
|
-509,
|
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|
-739,
|
||||||
|
-972,
|
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|
-1208,
|
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|
-1447,
|
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|
-1687,
|
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|
-1929,
|
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|
-2172,
|
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|
-2414,
|
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|
-2656,
|
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|
-2896,
|
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|
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|
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|
-3368,
|
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|
-3600,
|
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|
-3826,
|
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|
-4048,
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
-1971,
|
||||||
|
-1529,
|
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|
-1066,
|
||||||
|
-582,
|
||||||
|
-79,
|
||||||
|
444,
|
||||||
|
985,
|
||||||
|
1545,
|
||||||
|
2123,
|
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|
2717,
|
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|
3328,
|
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|
3955,
|
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|
4597,
|
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|
5253,
|
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|
5921,
|
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|
6603,
|
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|
7295,
|
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|
7998,
|
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|
8711,
|
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|
9432,
|
||||||
|
10160,
|
||||||
|
10895,
|
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|
11635,
|
||||||
|
12379,
|
||||||
|
13126,
|
||||||
|
13875,
|
||||||
|
14624,
|
||||||
|
15374,
|
||||||
|
16121,
|
||||||
|
16866,
|
||||||
|
17607,
|
||||||
|
18342,
|
||||||
|
19071,
|
||||||
|
19793,
|
||||||
|
20505,
|
||||||
|
21208,
|
||||||
|
21900,
|
||||||
|
22579,
|
||||||
|
23245,
|
||||||
|
23896,
|
||||||
|
24532,
|
||||||
|
25151,
|
||||||
|
25752,
|
||||||
|
26334,
|
||||||
|
26896,
|
||||||
|
27438,
|
||||||
|
27957,
|
||||||
|
28455,
|
||||||
|
28928,
|
||||||
|
29377,
|
||||||
|
29801,
|
||||||
|
30200,
|
||||||
|
30571,
|
||||||
|
30915,
|
||||||
|
31232,
|
||||||
|
31520,
|
||||||
|
31779,
|
||||||
|
32009,
|
||||||
|
32209,
|
||||||
|
32379,
|
||||||
|
32518,
|
||||||
|
32627,
|
||||||
|
32704,
|
||||||
|
32751,
|
||||||
|
32767,
|
||||||
|
32751,
|
||||||
|
32704,
|
||||||
|
32627,
|
||||||
|
32518,
|
||||||
|
32379,
|
||||||
|
32209,
|
||||||
|
32009,
|
||||||
|
31779,
|
||||||
|
31520,
|
||||||
|
31232,
|
||||||
|
30915,
|
||||||
|
30571,
|
||||||
|
30200,
|
||||||
|
29801,
|
||||||
|
29377,
|
||||||
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28928,
|
||||||
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28455,
|
||||||
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27957,
|
||||||
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27438,
|
||||||
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26896,
|
||||||
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26334,
|
||||||
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25752,
|
||||||
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25151,
|
||||||
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24532,
|
||||||
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23896,
|
||||||
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23245,
|
||||||
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22579,
|
||||||
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21900,
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||||||
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21208,
|
||||||
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20505,
|
||||||
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19793,
|
||||||
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19071,
|
||||||
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18342,
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||||||
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17607,
|
||||||
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16866,
|
||||||
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16121,
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||||||
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15374,
|
||||||
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14624,
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||||||
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13875,
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||||||
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13126,
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||||||
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12379,
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||||||
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11635,
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||||||
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10895,
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||||||
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10160,
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||||||
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9432,
|
||||||
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8711,
|
||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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3955,
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
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|
||||||
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|
||||||
|
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|
||||||
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|
||||||
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|
||||||
|
-5050,
|
||||||
|
-4866,
|
||||||
|
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|
||||||
|
-4472,
|
||||||
|
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|
||||||
|
-4048,
|
||||||
|
-3826,
|
||||||
|
-3600,
|
||||||
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-3368,
|
||||||
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|
||||||
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|
||||||
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|
||||||
|
-2414,
|
||||||
|
-2172,
|
||||||
|
-1929,
|
||||||
|
-1687,
|
||||||
|
-1447,
|
||||||
|
-1208,
|
||||||
|
-972,
|
||||||
|
-739,
|
||||||
|
-509,
|
||||||
|
-284,
|
||||||
|
-64,
|
||||||
|
151,
|
||||||
|
360,
|
||||||
|
563,
|
||||||
|
759,
|
||||||
|
948,
|
||||||
|
1130,
|
||||||
|
1304,
|
||||||
|
1469,
|
||||||
|
1627,
|
||||||
|
1775,
|
||||||
|
1915,
|
||||||
|
2046,
|
||||||
|
2168,
|
||||||
|
2280,
|
||||||
|
2382,
|
||||||
|
2476,
|
||||||
|
2559,
|
||||||
|
2633,
|
||||||
|
2698,
|
||||||
|
2752,
|
||||||
|
2798,
|
||||||
|
2833,
|
||||||
|
2860,
|
||||||
|
2877,
|
||||||
|
2886,
|
||||||
|
2885,
|
||||||
|
2876,
|
||||||
|
2859,
|
||||||
|
2833,
|
||||||
|
2800,
|
||||||
|
2759,
|
||||||
|
2711,
|
||||||
|
2655,
|
||||||
|
2593,
|
||||||
|
2525,
|
||||||
|
2451,
|
||||||
|
2371,
|
||||||
|
2285,
|
||||||
|
2195,
|
||||||
|
2101,
|
||||||
|
2002,
|
||||||
|
1900,
|
||||||
|
1794,
|
||||||
|
1686,
|
||||||
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1575,
|
||||||
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1461,
|
||||||
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1346,
|
||||||
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1230,
|
||||||
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1113,
|
||||||
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995,
|
||||||
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877,
|
||||||
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759,
|
||||||
|
642,
|
||||||
|
525,
|
||||||
|
410,
|
||||||
|
296,
|
||||||
|
184,
|
||||||
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74,
|
||||||
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-33,
|
||||||
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|
||||||
|
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
-773,
|
||||||
|
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|
||||||
|
-918,
|
||||||
|
-983,
|
||||||
|
-1044,
|
||||||
|
-1100,
|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
-1004,
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
-736,
|
||||||
|
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|
||||||
|
-621,
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
-38,
|
||||||
|
16,
|
||||||
|
69,
|
||||||
|
119,
|
||||||
|
169,
|
||||||
|
216,
|
||||||
|
261,
|
||||||
|
304,
|
||||||
|
345,
|
||||||
|
383,
|
||||||
|
419,
|
||||||
|
453,
|
||||||
|
484,
|
||||||
|
513,
|
||||||
|
538,
|
||||||
|
562,
|
||||||
|
582,
|
||||||
|
600,
|
||||||
|
615,
|
||||||
|
627,
|
||||||
|
637,
|
||||||
|
644,
|
||||||
|
649,
|
||||||
|
650,
|
||||||
|
650,
|
||||||
|
647,
|
||||||
|
641,
|
||||||
|
633,
|
||||||
|
623,
|
||||||
|
611,
|
||||||
|
596,
|
||||||
|
580,
|
||||||
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562,
|
||||||
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542,
|
||||||
|
520,
|
||||||
|
497,
|
||||||
|
473,
|
||||||
|
447,
|
||||||
|
420,
|
||||||
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392,
|
||||||
|
363,
|
||||||
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334,
|
||||||
|
304,
|
||||||
|
273,
|
||||||
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242,
|
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|
210,
|
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|
179,
|
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147,
|
||||||
|
116,
|
||||||
|
85,
|
||||||
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54,
|
||||||
|
24,
|
||||||
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-6,
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||||||
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-35,
|
||||||
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|
||||||
|
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||||||
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
-211,
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
-356,
|
||||||
|
-354,
|
||||||
|
-351,
|
||||||
|
-347,
|
||||||
|
-341,
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
-213,
|
||||||
|
-195,
|
||||||
|
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|
||||||
|
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|
||||||
|
-138,
|
||||||
|
-118,
|
||||||
|
-98,
|
||||||
|
-77,
|
||||||
|
-56,
|
||||||
|
-36,
|
||||||
|
-15,
|
||||||
|
5,
|
||||||
|
26,
|
||||||
|
46,
|
||||||
|
66,
|
||||||
|
85,
|
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|
104,
|
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|
122,
|
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|
139,
|
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|
156,
|
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|
172,
|
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187,
|
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|
202,
|
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215,
|
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228,
|
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239,
|
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249,
|
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259,
|
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267,
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274,
|
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280,
|
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|
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288,
|
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291,
|
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|
292,
|
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292,
|
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291,
|
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289,
|
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285,
|
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281,
|
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275,
|
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268,
|
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261,
|
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252,
|
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243,
|
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|
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|
221,
|
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|
209,
|
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196,
|
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|
182,
|
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|
168,
|
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|
153,
|
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|
138,
|
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|
122,
|
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|
106,
|
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|
89,
|
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|
73,
|
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|
56,
|
||||||
|
38,
|
||||||
|
21,
|
||||||
|
4,
|
||||||
|
-13,
|
||||||
|
-30,
|
||||||
|
-47;
|
||||||
@@ -0,0 +1,258 @@
|
|||||||
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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|
||||||
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||||||
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"MANAGED": [ { "value": "TRUE" } ],
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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|
||||||
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|
||||||
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||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
|
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|
||||||
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||||||
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|
||||||
|
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|
||||||
|
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
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||||||
|
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|
||||||
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||||||
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||||||
|
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|
||||||
|
}
|
||||||
|
},
|
||||||
|
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|
||||||
|
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||||
|
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|
||||||
|
"parameters": {
|
||||||
|
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||||
|
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|
||||||
|
}
|
||||||
|
},
|
||||||
|
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|
||||||
|
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||||
|
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|
||||||
|
"parameters": {
|
||||||
|
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||||
|
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|
||||||
|
}
|
||||||
|
},
|
||||||
|
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|
||||||
|
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
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|
||||||
|
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"event_s_phase_chanid_incorrect_intf": {
|
||||||
|
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"event_s_config_tlast_missing_intf": {
|
||||||
|
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"event_s_config_tlast_unexpected_intf": {
|
||||||
|
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"aclk_intf": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "aclk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"aresetn_intf": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"aclken_intf": {
|
||||||
|
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXIS_DATA": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
|
||||||
|
"TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"S_AXIS_CONFIG": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "s_axis_config_tdata" } ],
|
||||||
|
"TVALID": [ { "physical_name": "s_axis_config_tvalid" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,252 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "hop_rom",
|
||||||
|
"component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
|
||||||
|
"ip_revision": "7",
|
||||||
|
"gen_directory": "../../../../tx_qpsk.gen/sources_1/ip/hop_rom",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"Component_Name": [ { "value": "hop_rom", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"Memory_Type": [ { "value": "Single_Port_ROM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Use_Byte_Write_Enable": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Byte_Size": [ { "value": "9", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Write_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Write_Depth_A": [ { "value": "256", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Read_Width_A": [ { "value": "32", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Write_Width_B": [ { "value": "32", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Read_Width_B": [ { "value": "32", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Enable_B": [ { "value": "Always_Enabled", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Load_Init_File": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Coe_File": [ { "value": "../coe/sweep_freq.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Port_A_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Port_B_Clock": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Port_B_Enable_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_FAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_XDEVICEFAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_32BIT_ADDRESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MEM_TYPE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_BYTE_SIZE": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LOAD_INIT_FILE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INIT_FILE_NAME": [ { "value": "hop_rom.mif", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_INIT_FILE": [ { "value": "hop_rom.mem", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_HAS_ENA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_BYTE_WEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WEA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_WRITE_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_READ_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WRITE_DEPTH_A": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_READ_DEPTH_A": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ADDRA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_HAS_ENB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_BYTE_WEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WEB_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_WRITE_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_READ_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WRITE_DEPTH_B": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_READ_DEPTH_B": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ADDRB_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_COUNT_36K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_COUNT_18K_BRAM": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 3.375199 mW", "resolve_type": "generated", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "kintex7" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
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"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xc7k410t" } ],
|
||||||
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"PACKAGE": [ { "value": "ffg900" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||||
|
"IPREVISION": [ { "value": "7" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../tx_qpsk.gen/sources_1/ip/hop_rom" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "." } ],
|
||||||
|
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"clka": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"addra": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"douta": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"CLK.ACLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"RST.ARESETN": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"BRAM_PORTA": {
|
||||||
|
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"ADDR": [ { "physical_name": "addra" } ],
|
||||||
|
"CLK": [ { "physical_name": "clka" } ],
|
||||||
|
"DOUT": [ { "physical_name": "douta" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"memory_maps": {
|
||||||
|
"S_1": {
|
||||||
|
"address_blocks": {
|
||||||
|
"Mem0": {
|
||||||
|
"base_address": "0",
|
||||||
|
"range": "4096",
|
||||||
|
"usage": "memory",
|
||||||
|
"access": "read-write",
|
||||||
|
"parameters": {
|
||||||
|
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||||
|
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
+349
@@ -0,0 +1,349 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "hrc_64_12_025",
|
||||||
|
"component_reference": "xilinx.com:ip:fir_compiler:7.2",
|
||||||
|
"ip_revision": "20",
|
||||||
|
"gen_directory": "../../../../tx_qpsk.gen/sources_1/ip/hrc_64_12_025",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"Component_Name": [ { "value": "hrc_64_12_025", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"GUI_Behaviour": [ { "value": "Coregen", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CoefficientSource": [ { "value": "COE_File", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CoefficientVector": [ { "value": "6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Coefficient_File": [ { "value": "../coe/hrc_64_12_025.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Coefficient_Sets": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Coefficient_Reload": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Filter_Type": [ { "value": "Interpolation", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Rate_Change_Type": [ { "value": "Integer", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Interpolation_Rate": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Decimation_Rate": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Zero_Pack_Factor": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Channel_Sequence": [ { "value": "Basic", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Number_Channels": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Select_Pattern": [ { "value": "All", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Pattern_List": [ { "value": "P4-0,P4-1,P4-2,P4-3,P4-4", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Number_Paths": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"RateSpecification": [ { "value": "Input_Sample_Period", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"HardwareOversamplingRate": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"SamplePeriod": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"Sample_Frequency": [ { "value": "0.001", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"Clock_Frequency": [ { "value": "300.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"Coefficient_Sign": [ { "value": "Signed", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Quantization": [ { "value": "Integer_Coefficients", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Coefficient_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"BestPrecision": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Coefficient_Fractional_Bits": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Coefficient_Structure": [ { "value": "Inferred", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Data_Sign": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Data_Width": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Data_Fractional_Bits": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Output_Rounding_Mode": [ { "value": "Full_Precision", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Output_Width": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Filter_Architecture": [ { "value": "Systolic_Multiply_Accumulate", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Optimization_Goal": [ { "value": "Area", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Optimization_Selection": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Data_Path_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Pre_Adder_Pipeline": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Coefficient_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Control_Path_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Control_Column_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Control_Broadcast_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Control_LUT_Pipeline": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"No_BRAM_Read_First_Mode": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Optimal_Column_Lengths": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Data_Path_Broadcast": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Disable_Half_Band_Centre_Tap": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"No_SRL_Attributes": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Other": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Optimization_List": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Data_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Coefficient_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Input_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Output_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Preference_For_Other_Storage": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Multi_Column_Support": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Inter_Column_Pipe_Length": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ColumnConfig": [ { "value": "7", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DATA_Has_TLAST": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"M_DATA_Has_TREADY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"S_DATA_Has_FIFO": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"S_DATA_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"M_DATA_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DATA_TUSER_Width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"S_CONFIG_Sync_Mode": [ { "value": "On_Vector", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"S_CONFIG_Method": [ { "value": "Single", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Num_Reload_Slots": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Has_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Has_ARESETn": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Reset_Data_Vector": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Blank_Output": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Gen_MIF_from_Spec": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Gen_MIF_from_COE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Reload_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Gen_MIF_Files": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"DisplayReloadOrder": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Passband_Min": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"Passband_Max": [ { "value": "0.5", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"Stopband_Min": [ { "value": "0.5", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"Stopband_Max": [ { "value": "1.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"Filter_Selection": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_XDEVICEFAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
|
||||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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||||||
|
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "s_axis_data_tdata" } ],
|
||||||
|
"TREADY": [ { "physical_name": "s_axis_data_tready" } ],
|
||||||
|
"TVALID": [ { "physical_name": "s_axis_data_tvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXIS_DATA": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "3", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
|
||||||
|
"TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,412 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Company:
|
||||||
|
// Engineer:
|
||||||
|
// _ _ ____
|
||||||
|
// | | ___ ___| |__ / ___| __ _ ___
|
||||||
|
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||||
|
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||||
|
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||||
|
//
|
||||||
|
// Create Date: 2022/03/23 20:17:56
|
||||||
|
// Last Modified Date: 2023/03/10 15:41
|
||||||
|
// Design Name:
|
||||||
|
// Module Name: tx_qpsk
|
||||||
|
// Project Name:
|
||||||
|
// Target Devices:
|
||||||
|
// Tool Versions:
|
||||||
|
// Description:
|
||||||
|
//
|
||||||
|
// Dependencies:
|
||||||
|
//
|
||||||
|
// Revision:
|
||||||
|
// Revision 0.01 - File Created
|
||||||
|
// 20230228-1541 - 修改不扫频、无基带频偏时 [baseband_i/q] 的数据输出，原来从
|
||||||
|
// 乘法器引出，会导致频率为 0 时输出数据错误，现在直接从基带数据引出。
|
||||||
|
// 20230310-1542 - 增加输入参数，发送数据更改为直接由参数输入，发送方波改为 8
|
||||||
|
// 倍过采样，发送双音信号中 1MHz 信号的频率控制字可以根据参数中的时钟频率计
|
||||||
|
// 算得出。
|
||||||
|
// Additional Comments:
|
||||||
|
//
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
|
module tx_qpsk
|
||||||
|
#(
|
||||||
|
parameter DATA_WIDTH = 12, // need to be <= 16
|
||||||
|
parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
|
||||||
|
parameter BIT_DATA_LEN = 128,
|
||||||
|
parameter SQUARE_INTERP = 8,
|
||||||
|
parameter CLK_FREQ = 245760000 // in Hertz
|
||||||
|
)
|
||||||
|
(
|
||||||
|
input clk ,
|
||||||
|
input rst ,
|
||||||
|
output [DATA_WIDTH-1:0] tx_data_i ,
|
||||||
|
output [DATA_WIDTH-1:0] tx_data_q ,
|
||||||
|
// debug ports
|
||||||
|
input [ 1:0] waveform_sel ,
|
||||||
|
input sweep_on ,
|
||||||
|
input [31:0] freq_set ,
|
||||||
|
input [ 1:0] iq_sel ,
|
||||||
|
input [ 3:0] bb_rshift
|
||||||
|
);
|
||||||
|
|
||||||
|
localparam RCOS_INTERP = 64;
|
||||||
|
localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP;
|
||||||
|
localparam FREQ_WORD_1M = 64'd2**64'd32*64'd1000000/CLK_FREQ;
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
///////////////////////////////// Data Counter /////////////////////////////////
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// symbol & interpolation counter
|
||||||
|
reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0] cnt = 'b0;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
cnt <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
////////////////////// Root-Rasied Cosine Shaping Filter ///////////////////////
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// address
|
||||||
|
reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_i = 'b0;
|
||||||
|
reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_q = 'b1;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
hrc_data_addr_i <= 'b0;
|
||||||
|
hrc_data_addr_q <= 'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
hrc_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0};
|
||||||
|
hrc_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1};
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// bit data
|
||||||
|
reg hrc_data_i = 'b0;
|
||||||
|
reg hrc_data_q = 'b0;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
hrc_data_i <= 'b0;
|
||||||
|
hrc_data_q <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
hrc_data_i <= BIT_DATA[hrc_data_addr_i];
|
||||||
|
hrc_data_q <= BIT_DATA[hrc_data_addr_q];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// polarization
|
||||||
|
wire [ 7:0] hrc_data_polar_i;
|
||||||
|
wire [ 7:0] hrc_data_polar_q;
|
||||||
|
|
||||||
|
assign hrc_data_polar_i = {{7{hrc_data_i}},1'b1};
|
||||||
|
assign hrc_data_polar_q = {{7{hrc_data_q}},1'b1};
|
||||||
|
|
||||||
|
// root raised cosine shaping-filter
|
||||||
|
wire [23:0] hrc_wave_i;
|
||||||
|
wire [23:0] hrc_wave_q;
|
||||||
|
|
||||||
|
hrc_64_12_025 u_hrc_i (
|
||||||
|
.aclk (clk ), // input wire aclk
|
||||||
|
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
|
||||||
|
.s_axis_data_tready ( ), // output wire s_axis_data_tready
|
||||||
|
.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
|
||||||
|
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||||
|
.m_axis_data_tdata (hrc_wave_i ) // output wire [23 : 0] m_axis_data_tdata
|
||||||
|
);
|
||||||
|
|
||||||
|
hrc_64_12_025 u_hrc_q (
|
||||||
|
.aclk (clk ), // input wire aclk
|
||||||
|
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
|
||||||
|
.s_axis_data_tready ( ), // output wire s_axis_data_tready
|
||||||
|
.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
|
||||||
|
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||||
|
.m_axis_data_tdata (hrc_wave_q ) // output wire [23 : 0] m_axis_data_tdata
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
//////////////////////////// Square Shaping Filter /////////////////////////////
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// address
|
||||||
|
reg [$clog2(BIT_DATA_LEN)-1 : 0] hsq_data_addr = 'b0;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
hsq_data_addr <= 'b0;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
hsq_data_addr <= {cnt[$clog2(SQUARE_INTERP) +: $clog2(BIT_DATA_LEN)]};
|
||||||
|
end
|
||||||
|
|
||||||
|
// bit data
|
||||||
|
reg hsq_data = 'b0;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
hsq_data <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
hsq_data <= BIT_DATA[hsq_data_addr];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// square shaping-filter
|
||||||
|
reg [17:0] hsq_wave_i ='b0;
|
||||||
|
reg [17:0] hsq_wave_q ='b0;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
hsq_wave_i <= 'b0;
|
||||||
|
hsq_wave_q <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
hsq_wave_i <= hsq_data ? 18'b01_1111_1111_1111_1111 : 18'b10_0000_0000_0000_0001;
|
||||||
|
hsq_wave_q <= hsq_data ? 18'b10_0000_0000_0000_0001 : 18'b01_1111_1111_1111_1111;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
/////////////////////////////// Two Tone Siganl ////////////////////////////////
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// cosine wave with freq of 1 MHz
|
||||||
|
wire signed [7:0] cos_1m;
|
||||||
|
wire signed [7:0] sin_1m;
|
||||||
|
|
||||||
|
dds_32b_8b u_dds_1m
|
||||||
|
(
|
||||||
|
.aclk (clk ), // input wire aclk
|
||||||
|
.s_axis_config_tvalid (1'b1 ), // input wire s_axis_config_tvalid
|
||||||
|
.s_axis_config_tdata (FREQ_WORD_1M[31:0] ), // input wire [31 : 0] s_axis_config_tdata
|
||||||
|
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||||
|
.m_axis_data_tdata ({sin_1m,cos_1m} ) // output wire [15 : 0] m_axis_data_tdata
|
||||||
|
);
|
||||||
|
|
||||||
|
// two-tone signal
|
||||||
|
reg signed [16:0] two_tone_wave_i = 'b0;
|
||||||
|
reg signed [16:0] two_tone_wave_q = 'b0;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
two_tone_wave_i <= 'b0;
|
||||||
|
two_tone_wave_q <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
two_tone_wave_i <= 17'b0_0111_1111_1111_1111 + {cos_1m[7],cos_1m,8'd0};
|
||||||
|
two_tone_wave_q <= 17'b0 + {sin_1m[7],sin_1m,8'd0};
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
///////////////////// Waveform Selection & Hopping Control /////////////////////
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// baseband signal select
|
||||||
|
reg [17:0] baseband_sel_i = 'b0;
|
||||||
|
reg [17:0] baseband_sel_q = 'b0;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
baseband_sel_i <= 'b0;
|
||||||
|
baseband_sel_q <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
case (waveform_sel[1:0])
|
||||||
|
2'd0: begin
|
||||||
|
baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
|
||||||
|
baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
|
||||||
|
end
|
||||||
|
2'd1: begin
|
||||||
|
baseband_sel_i <= hsq_wave_i[17:0];
|
||||||
|
baseband_sel_q <= hsq_wave_q[17:0];
|
||||||
|
end
|
||||||
|
2'd2: begin
|
||||||
|
baseband_sel_i <= 18'b01_1111_1111_1111_1111;
|
||||||
|
baseband_sel_q <= 18'b0;
|
||||||
|
end
|
||||||
|
2'd3: begin
|
||||||
|
baseband_sel_i <= {two_tone_wave_i[16:0],1'b0};
|
||||||
|
baseband_sel_q <= {two_tone_wave_q[16:0],1'b0};
|
||||||
|
end
|
||||||
|
default: begin
|
||||||
|
baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
|
||||||
|
baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// hopping control, 3750hop/s
|
||||||
|
reg [23:0] sweep_rom_addr = 'b0;
|
||||||
|
wire [31:0] freq_sweep;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
sweep_rom_addr <= 'b0;
|
||||||
|
end
|
||||||
|
else if (sweep_on) begin
|
||||||
|
sweep_rom_addr <= sweep_rom_addr + 24'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
sweep_rom_addr <= 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
hop_rom u_sweep_rom
|
||||||
|
(
|
||||||
|
.clka (clk ), // input wire clka
|
||||||
|
.addra (sweep_rom_addr[23:16] ), // input wire [7 : 0] addra
|
||||||
|
.douta (freq_sweep ) // output wire [31 : 0] douta
|
||||||
|
);
|
||||||
|
|
||||||
|
// choose the actual frequency word
|
||||||
|
reg [31:0] freq_word = 'b0;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
freq_word <= 'b0;
|
||||||
|
end
|
||||||
|
else if (sweep_on) begin
|
||||||
|
// frequency sweep
|
||||||
|
freq_word <= freq_sweep;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
// normal operation
|
||||||
|
freq_word <= freq_set;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// baseband frequency shift carrier generation
|
||||||
|
wire [ 7:0] cos_dds;
|
||||||
|
wire [ 7:0] sin_dds;
|
||||||
|
reg [ 7:0] cos = 'b0;
|
||||||
|
reg [ 7:0] sin = 'b0;
|
||||||
|
|
||||||
|
dds_32b_8b u_dds_bb_shift (
|
||||||
|
.aclk (clk ), // input wire aclk
|
||||||
|
.s_axis_config_tvalid (~rst ), // input wire s_axis_config_tvalid
|
||||||
|
.s_axis_config_tdata (freq_word ), // input wire [31 : 0] s_axis_config_tdata
|
||||||
|
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||||
|
.m_axis_data_tdata ({sin_dds,cos_dds}) // output wire [31 : 0] m_axis_data_tdata
|
||||||
|
);
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
cos <= 'b0;
|
||||||
|
sin <= 'b0;
|
||||||
|
end
|
||||||
|
else if (freq_word == 'b0) begin
|
||||||
|
// to make sure the carriers stay at the right position when freq = 0
|
||||||
|
cos <= 8'b0111_1111;
|
||||||
|
sin <= 8'b0111_1111;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cos <= cos_dds;
|
||||||
|
sin <= sin_dds;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// baseband frequency shift modulation
|
||||||
|
wire [47:0] mod_cmpy_a;
|
||||||
|
wire [15:0] mod_cmpy_b;
|
||||||
|
wire [63:0] mod_cmpy_out;
|
||||||
|
|
||||||
|
wire [26:0] baseband_mult_i;
|
||||||
|
wire [26:0] baseband_mult_q;
|
||||||
|
|
||||||
|
assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i};
|
||||||
|
assign mod_cmpy_b = {-sin,cos};
|
||||||
|
|
||||||
|
assign baseband_mult_i = mod_cmpy_out[58:32];
|
||||||
|
assign baseband_mult_q = mod_cmpy_out[26: 0];
|
||||||
|
|
||||||
|
cmpy_18x8 u_cmpy_18x8
|
||||||
|
(
|
||||||
|
.aclk (clk ), // input wire aclk
|
||||||
|
.s_axis_a_tvalid (1'b1 ), // input wire s_axis_a_tvalid
|
||||||
|
.s_axis_a_tdata (mod_cmpy_a ), // input wire [47 : 0] s_axis_a_tdata
|
||||||
|
.s_axis_b_tvalid (1'b1 ), // input wire s_axis_b_tvalid
|
||||||
|
.s_axis_b_tdata (mod_cmpy_b ), // input wire [15 : 0] s_axis_b_tdata
|
||||||
|
.m_axis_dout_tvalid ( ), // output wire m_axis_dout_tvalid
|
||||||
|
.m_axis_dout_tdata (mod_cmpy_out ) // output wire [63 : 0] m_axis_dout_tdata
|
||||||
|
);
|
||||||
|
|
||||||
|
// truncate to 16-bit
|
||||||
|
reg signed [15:0] baseband_i = 'b0;
|
||||||
|
reg signed [15:0] baseband_q = 'b0;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
baseband_i <= 'b0;
|
||||||
|
baseband_q <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
case (waveform_sel[1:0])
|
||||||
|
2'd0: begin
|
||||||
|
// scale rasied-cosine-shaped bpsk signal by 1.125 or 1.625
|
||||||
|
baseband_i <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_i[17 -: 16] + {{3{baseband_sel_i[17]}},baseband_sel_i[17 -: 13]}) : (baseband_mult_i[25:10] + {baseband_mult_i[25],baseband_mult_i[25:11]} + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]});
|
||||||
|
baseband_q <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_q[17 -: 16] + {{3{baseband_sel_q[17]}},baseband_sel_q[17 -: 13]}) : (baseband_mult_q[25:10] + {baseband_mult_q[25],baseband_mult_q[25:11]} + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]});
|
||||||
|
end
|
||||||
|
2'd1: begin
|
||||||
|
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : (baseband_mult_i[25:10] + {{2{baseband_mult_i[25]}},baseband_mult_i[25:12]});
|
||||||
|
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : (baseband_mult_q[25:10] + {{2{baseband_mult_q[25]}},baseband_mult_q[25:12]});
|
||||||
|
end
|
||||||
|
2'd2: begin
|
||||||
|
baseband_i <= baseband_mult_i[24:9];
|
||||||
|
baseband_q <= baseband_mult_q[24:9];
|
||||||
|
end
|
||||||
|
2'd3: begin
|
||||||
|
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9];
|
||||||
|
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9];
|
||||||
|
end
|
||||||
|
default: begin
|
||||||
|
// scale rasied-cosine-shaped bpsk signal by 1.125
|
||||||
|
baseband_i <= baseband_mult_i[25:10] + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]};
|
||||||
|
baseband_q <= baseband_mult_q[25:10] + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]};
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// iq selection & baseband right shift
|
||||||
|
reg signed [15:0] baseband_data_i = 'b0;
|
||||||
|
reg signed [15:0] baseband_data_q = 'b0;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
baseband_data_i <= 'b0;
|
||||||
|
baseband_data_q <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
// inphase selection
|
||||||
|
if (iq_sel[1]) begin
|
||||||
|
baseband_data_i <= baseband_i >>> bb_rshift;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
baseband_data_i <= 'b0;
|
||||||
|
end
|
||||||
|
// quadrature selection
|
||||||
|
if (iq_sel[0]) begin
|
||||||
|
baseband_data_q <= baseband_q >>> bb_rshift;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
baseband_data_q <= 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// output data to ports
|
||||||
|
assign tx_data_i = baseband_data_i[15 -: DATA_WIDTH];
|
||||||
|
assign tx_data_q = baseband_data_q[15 -: DATA_WIDTH];
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,414 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||||
|
<!-- -->
|
||||||
|
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||||
|
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||||
|
|
||||||
|
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/Workspace/vivado/vivado_pub/modules/xc7k410tffg900-2/tx_qpsk/tx_qpsk.xpr">
|
||||||
|
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||||
|
<Configuration>
|
||||||
|
<Option Name="Id" Val="148f7275fd02472a85da2f9f50b75194"/>
|
||||||
|
<Option Name="Part" Val="xc7k410tffg900-2"/>
|
||||||
|
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||||
|
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||||
|
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||||
|
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||||
|
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||||
|
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||||
|
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||||
|
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||||
|
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||||
|
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||||
|
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||||
|
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||||
|
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||||
|
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||||
|
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||||
|
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||||
|
<Option Name="BoardPart" Val=""/>
|
||||||
|
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||||
|
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="ProjectType" Val="Default"/>
|
||||||
|
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||||
|
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||||
|
<Option Name="IPCachePermission" Val="read"/>
|
||||||
|
<Option Name="IPCachePermission" Val="write"/>
|
||||||
|
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||||
|
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||||
|
<Option Name="SimCompileState" Val="TRUE"/>
|
||||||
|
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||||
|
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||||
|
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||||
|
<Option Name="EnableBDX" Val="FALSE"/>
|
||||||
|
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||||
|
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTXSimExportSim" Val="4"/>
|
||||||
|
<Option Name="WTModelSimExportSim" Val="4"/>
|
||||||
|
<Option Name="WTQuestaExportSim" Val="4"/>
|
||||||
|
<Option Name="WTIesExportSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsExportSim" Val="4"/>
|
||||||
|
<Option Name="WTRivieraExportSim" Val="4"/>
|
||||||
|
<Option Name="WTActivehdlExportSim" Val="4"/>
|
||||||
|
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||||
|
<Option Name="XSimRadix" Val="hex"/>
|
||||||
|
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||||
|
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||||
|
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||||
|
<Option Name="SimTypes" Val="rtl"/>
|
||||||
|
<Option Name="SimTypes" Val="bfm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||||
|
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||||
|
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||||
|
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||||
|
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||||
|
</Configuration>
|
||||||
|
<FileSets Version="1" Minor="32">
|
||||||
|
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||||
|
<Filter Type="Srcs"/>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/tx_qpsk.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/ip/coe/hrc_64_12_025.coe">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/ip/coe/sweep_freq.coe">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="tx_qpsk"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||||
|
<Filter Type="Constrs"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="ConstrsType" Val="XDC"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||||
|
<File Path="$PSRCDIR/sim_1/new/tb_tx_qpsk.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="tb_tx_qpsk"/>
|
||||||
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
<Option Name="TransportPathDelay" Val="0"/>
|
||||||
|
<Option Name="TransportIntDelay" Val="0"/>
|
||||||
|
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||||
|
<Option Name="PamDesignTestbench" Val=""/>
|
||||||
|
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||||
|
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||||
|
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||||
|
<Option Name="SrcSet" Val="sources_1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||||
|
<Filter Type="Utils"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="dds_32b_8b" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dds_32b_8b" RelGenDir="$PGENDIR/dds_32b_8b">
|
||||||
|
<File Path="$PSRCDIR/sources_1/ip/dds_32b_8b/dds_32b_8b.xci">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopModule" Val="dds_32b_8b"/>
|
||||||
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="hrc_64_12_025" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_64_12_025" RelGenDir="$PGENDIR/hrc_64_12_025">
|
||||||
|
<File Path="$PSRCDIR/sources_1/ip/hrc_64_12_025/hrc_64_12_025.xci">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopModule" Val="hrc_64_12_025"/>
|
||||||
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="cmpy_18x8" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_18x8" RelGenDir="$PGENDIR/cmpy_18x8">
|
||||||
|
<File Path="$PSRCDIR/sources_1/ip/cmpy_18x8/cmpy_18x8.xci">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopModule" Val="cmpy_18x8"/>
|
||||||
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="hop_rom" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hop_rom" RelGenDir="$PGENDIR/hop_rom">
|
||||||
|
<File Path="$PSRCDIR/sources_1/ip/hop_rom/hop_rom.xci">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopModule" Val="hop_rom"/>
|
||||||
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
</FileSets>
|
||||||
|
<Simulators>
|
||||||
|
<Simulator Name="XSim">
|
||||||
|
<Option Name="Description" Val="Vivado Simulator"/>
|
||||||
|
<Option Name="CompiledLib" Val="0"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ModelSim">
|
||||||
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Questa">
|
||||||
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Xcelium">
|
||||||
|
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="VCS">
|
||||||
|
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Riviera">
|
||||||
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
</Simulators>
|
||||||
|
<Runs Version="1" Minor="21">
|
||||||
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="dds_32b_8b_synth_1" Type="Ft3:Synth" SrcSet="dds_32b_8b" Part="xc7k410tffg900-2" ConstrsSet="dds_32b_8b" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dds_32b_8b_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dds_32b_8b_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dds_32b_8b_synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="hrc_64_12_025_synth_1" Type="Ft3:Synth" SrcSet="hrc_64_12_025" Part="xc7k410tffg900-2" ConstrsSet="hrc_64_12_025" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hrc_64_12_025_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="cmpy_18x8_synth_1" Type="Ft3:Synth" SrcSet="cmpy_18x8" Part="xc7k410tffg900-2" ConstrsSet="cmpy_18x8" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/cmpy_18x8_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_18x8_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_18x8_synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="hop_rom_synth_1" Type="Ft3:Synth" SrcSet="hop_rom" Part="xc7k410tffg900-2" ConstrsSet="hop_rom" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hop_rom_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hop_rom_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hop_rom_synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="dds_32b_8b_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="dds_32b_8b" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dds_32b_8b_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dds_32b_8b_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dds_32b_8b_impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="hrc_64_12_025_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="hrc_64_12_025" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hrc_64_12_025_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="cmpy_18x8_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="cmpy_18x8" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="cmpy_18x8_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_18x8_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_18x8_impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="hop_rom_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="hop_rom" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hop_rom_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hop_rom_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hop_rom_impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
</Runs>
|
||||||
|
<Board/>
|
||||||
|
<DashboardSummary Version="1" Minor="0">
|
||||||
|
<Dashboards>
|
||||||
|
<Dashboard Name="default_dashboard">
|
||||||
|
<Gadgets>
|
||||||
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||||
|
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||||
|
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
</Gadgets>
|
||||||
|
</Dashboard>
|
||||||
|
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||||
|
</Dashboards>
|
||||||
|
</DashboardSummary>
|
||||||
|
</Project>
|
||||||
Binary file not shown.
|
@@ -0,0 +1,94 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Company:
|
||||||
|
// Engineer:
|
||||||
|
//
|
||||||
|
// Create Date: 06/11/2023 03:49:38 PM
|
||||||
|
// Design Name:
|
||||||
|
// Module Name: tb_var_cal
|
||||||
|
// Project Name:
|
||||||
|
// Target Devices:
|
||||||
|
// Tool Versions:
|
||||||
|
// Description:
|
||||||
|
//
|
||||||
|
// Dependencies:
|
||||||
|
//
|
||||||
|
// Revision:
|
||||||
|
// Revision 0.01 - File Created
|
||||||
|
// Additional Comments:
|
||||||
|
//
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
|
module tb_var_cal;
|
||||||
|
|
||||||
|
localparam DATA_I_WIDTH = 30;
|
||||||
|
|
||||||
|
reg clk = 1'b1;
|
||||||
|
reg clk_init = 1'b1;
|
||||||
|
reg rst = 1'b1;
|
||||||
|
|
||||||
|
reg cal_start = 1'b0;
|
||||||
|
reg cal_auto_en = 1'b0;
|
||||||
|
wire cal_busy;
|
||||||
|
|
||||||
|
reg din_valid = 1'b0;
|
||||||
|
reg [29:0] din_file_real = 'b0;
|
||||||
|
reg [29:0] din_file_imag = 'b0;
|
||||||
|
wire [DATA_I_WIDTH-1:0] din_real;
|
||||||
|
wire [DATA_I_WIDTH-1:0] din_imag;
|
||||||
|
|
||||||
|
assign din_real = din_file_real[29 -: DATA_I_WIDTH];
|
||||||
|
assign din_imag = din_file_imag[29 -: DATA_I_WIDTH];
|
||||||
|
|
||||||
|
wire var_valid;
|
||||||
|
wire [31:0] var;
|
||||||
|
|
||||||
|
var_cal #(
|
||||||
|
.ACCUM_NUM (16384 ),
|
||||||
|
.DATA_I_WIDTH (DATA_I_WIDTH ),
|
||||||
|
.DATA_O_WIDTH (32 )
|
||||||
|
) u_var_cal
|
||||||
|
(
|
||||||
|
.clk (clk ),
|
||||||
|
.rst (rst ),
|
||||||
|
|
||||||
|
.cal_start (cal_start ),
|
||||||
|
.cal_auto_en(cal_auto_en),
|
||||||
|
.cal_busy (cal_busy ),
|
||||||
|
|
||||||
|
.din_valid (din_valid ),
|
||||||
|
.din_real (din_real ),
|
||||||
|
.din_imag (din_imag ),
|
||||||
|
|
||||||
|
.var_valid (var_valid ),
|
||||||
|
.var (var )
|
||||||
|
);
|
||||||
|
|
||||||
|
integer i;
|
||||||
|
integer r_file;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
#102
|
||||||
|
rst = 1'b0;
|
||||||
|
#100
|
||||||
|
din_valid = 1'b1;
|
||||||
|
// cal_start = 1'b1;
|
||||||
|
cal_auto_en = 1'b1;
|
||||||
|
|
||||||
|
r_file = $fopen("./../../../../../testbenches/singletone.csv","r");
|
||||||
|
for (i = 0; i <= 32768; i = i + 1) begin
|
||||||
|
@(posedge clk)
|
||||||
|
$fscanf(r_file,"%d,%d",din_file_real,din_file_imag);
|
||||||
|
end
|
||||||
|
$fclose(r_file);
|
||||||
|
$stop;
|
||||||
|
end
|
||||||
|
|
||||||
|
always #10 clk_init = ~clk_init;
|
||||||
|
|
||||||
|
always @(posedge clk_init) begin
|
||||||
|
clk <= ~clk;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
+212
@@ -0,0 +1,212 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "cmpy_18x18_mult",
|
||||||
|
"component_reference": "xilinx.com:ip:cmpy:6.0",
|
||||||
|
"ip_revision": "22",
|
||||||
|
"gen_directory": "../../../../var_cal.gen/sources_1/ip/cmpy_18x18_mult",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"Component_Name": [ { "value": "cmpy_18x18_mult", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"APortWidth": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"HasATLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"HasATUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"ATUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"BPortWidth": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"HasBTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"HasBTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"BTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"MultType": [ { "value": "Use_Mults", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"OptimizeGoal": [ { "value": "Resources", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"FlowControl": [ { "value": "NonBlocking", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"RoundMode": [ { "value": "Truncate", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"OutputWidth": [ { "value": "37", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"HasCTRLTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"HasCTRLTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CTRLTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"OutTLASTBehv": [ { "value": "Null", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"LatencyConfig": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"MinimumLatency": [ { "value": "6", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"ARESETN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_XDEVICEFAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_XDEVICE": [ { "value": "xc7k410t", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_A_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_B_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_OUT_WIDTH": [ { "value": "37", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LATENCY": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MULT_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_OPTIMIZE_GOAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"HAS_NEGATE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"SINGLE_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"ROUND": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"USE_DSP_CASCADES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_THROTTLE_SCHEME": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_ARESETN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_S_AXIS_A_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_S_AXIS_A_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_S_AXIS_B_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_S_AXIS_B_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_S_AXIS_CTRL_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_S_AXIS_CTRL_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_TLAST_RESOLUTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXIS_A_TDATA_WIDTH": [ { "value": "48", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXIS_A_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXIS_B_TDATA_WIDTH": [ { "value": "48", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXIS_B_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXIS_CTRL_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXIS_CTRL_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXIS_DOUT_TDATA_WIDTH": [ { "value": "80", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXIS_DOUT_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "kintex7" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xc7k410t" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffg900" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||||
|
"IPREVISION": [ { "value": "22" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../var_cal.gen/sources_1/ip/cmpy_18x18_mult" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "." } ],
|
||||||
|
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axis_a_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axis_a_tdata": [ { "direction": "in", "size_left": "47", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"s_axis_b_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axis_b_tdata": [ { "direction": "in", "size_left": "47", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"m_axis_dout_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||||
|
"m_axis_dout_tdata": [ { "direction": "out", "size_left": "79", "size_right": "0", "driver_value": "0" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"M_AXIS_DOUT": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "10", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "m_axis_dout_tdata" } ],
|
||||||
|
"TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"aclk_intf": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CTRL:S_AXIS_B:S_AXIS_A:M_AXIS_DOUT", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "aclk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"aresetn_intf": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"aclken_intf": {
|
||||||
|
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"S_AXIS_A": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "6", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "s_axis_a_tdata" } ],
|
||||||
|
"TVALID": [ { "physical_name": "s_axis_a_tvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"S_AXIS_B": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "6", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "s_axis_b_tdata" } ],
|
||||||
|
"TVALID": [ { "physical_name": "s_axis_b_tvalid" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,258 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Company:
|
||||||
|
// Engineer:
|
||||||
|
// _ _ ____
|
||||||
|
// | | ___ ___| |__ / ___| __ _ ___
|
||||||
|
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||||
|
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||||
|
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||||
|
//
|
||||||
|
// Create Date: 06/11/2023 02:41:47 PM
|
||||||
|
// Design Name:
|
||||||
|
// Module Name: var_cal
|
||||||
|
// Project Name:
|
||||||
|
// Target Devices:
|
||||||
|
// Tool Versions:
|
||||||
|
// Description:
|
||||||
|
//
|
||||||
|
// Dependencies:
|
||||||
|
//
|
||||||
|
// Revision:
|
||||||
|
// Revision 0.01 - File Created
|
||||||
|
// 20230730-1427 - 修改输入位宽小于乘法器位宽时的处理，由补零变为符号位扩展；
|
||||||
|
// 修改；修改累加和输出截位方式，依托原始数据位宽进行处理。
|
||||||
|
// Additional Comments:
|
||||||
|
//
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
|
module var_cal
|
||||||
|
#(
|
||||||
|
parameter ACCUM_NUM = 16384,
|
||||||
|
parameter DATA_I_WIDTH = 30,
|
||||||
|
parameter DATA_O_WIDTH = 32,
|
||||||
|
parameter CMPY_I_WIDTH = 18
|
||||||
|
)
|
||||||
|
(
|
||||||
|
input clk ,
|
||||||
|
input rst ,
|
||||||
|
|
||||||
|
input cal_start ,
|
||||||
|
input cal_auto_en ,
|
||||||
|
output cal_busy ,
|
||||||
|
|
||||||
|
input din_valid ,
|
||||||
|
input [DATA_I_WIDTH-1 : 0] din_real ,
|
||||||
|
input [DATA_I_WIDTH-1 : 0] din_imag ,
|
||||||
|
|
||||||
|
output var_valid ,
|
||||||
|
output [DATA_O_WIDTH-1 : 0] var
|
||||||
|
);
|
||||||
|
|
||||||
|
integer i;
|
||||||
|
|
||||||
|
localparam CMPY_P_WIDTH = 2*CMPY_I_WIDTH+1;
|
||||||
|
localparam AXIS_CMPY_I_WIDTH = 8*((CMPY_I_WIDTH-1)/8+1) ; // axis data width of input real/image data
|
||||||
|
localparam AXIS_CMPY_P_WIDTH = 8*((CMPY_P_WIDTH-1)/8+1); // axis data width of cmpy output real/image data
|
||||||
|
localparam CMPY_P_VALID_WIDTH = (DATA_I_WIDTH > CMPY_I_WIDTH) ? 2*CMPY_I_WIDTH : 2*DATA_I_WIDTH;
|
||||||
|
|
||||||
|
|
||||||
|
localparam ACCUM_WIDTH = CMPY_P_VALID_WIDTH + $clog2(ACCUM_NUM);
|
||||||
|
|
||||||
|
// status control
|
||||||
|
reg cal_start_auto = 'b0;
|
||||||
|
reg cal_start_d1 = 'b0;
|
||||||
|
reg cal_start_d2 = 'b0;
|
||||||
|
reg cal_busy_buf = 'b0;
|
||||||
|
reg [$clog2(ACCUM_NUM)-1 : 0] cnt_accum = 'b0;
|
||||||
|
reg last_data = 'b0;
|
||||||
|
reg [6:0] last_data_d = 'b0; // 1 for register input, 6 for cmpy, 1 for register output
|
||||||
|
|
||||||
|
assign cal_busy = cal_busy_buf;
|
||||||
|
assign var_valid = last_data_d[6];
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
cal_start_auto <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
if (cal_auto_en) begin
|
||||||
|
if (~cal_busy_buf) begin
|
||||||
|
cal_start_auto <= ~cal_start_auto;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cal_start_auto <= cal_start_auto;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cal_start_auto <= 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
cal_start_d1 <= cal_auto_en ? cal_start_auto : cal_start;
|
||||||
|
cal_start_d2 <= cal_start_d1;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
cal_busy_buf <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
if ((cal_start_d1 ^ cal_start_d2) && din_valid) begin
|
||||||
|
cal_busy_buf <= 1'b1;
|
||||||
|
end
|
||||||
|
else if (cnt_accum == ACCUM_NUM-1) begin
|
||||||
|
cal_busy_buf <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cal_busy_buf <= cal_busy_buf;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
cnt_accum <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cnt_accum <= cal_busy ? (cnt_accum + 1'b1) : 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
last_data <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
last_data <= (cnt_accum == ACCUM_NUM-1) ? 1'b1 : 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
last_data_d[6:0] <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
last_data_d[6:0] <= {last_data_d[5:0],last_data};
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
// cmpy
|
||||||
|
reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_a_real = 'b0;
|
||||||
|
reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_a_imag = 'b0;
|
||||||
|
reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_b_real = 'b0;
|
||||||
|
reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_b_imag = 'b0;
|
||||||
|
wire [AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p_raw_real;
|
||||||
|
wire [AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p_raw_imag;
|
||||||
|
wire [CMPY_P_VALID_WIDTH-1 : 0] cmpy_p_real;
|
||||||
|
wire [CMPY_P_VALID_WIDTH-1 : 0] cmpy_p_imag;
|
||||||
|
|
||||||
|
if (CMPY_I_WIDTH > DATA_I_WIDTH) begin
|
||||||
|
// sign-bit extension to fit cmpy input data width
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
cmpy_a_real <= 'b0;
|
||||||
|
cmpy_a_imag <= 'b0;
|
||||||
|
cmpy_b_real <= 'b0;
|
||||||
|
cmpy_b_imag <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cmpy_a_real <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real};
|
||||||
|
cmpy_a_imag <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag};
|
||||||
|
cmpy_b_real <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real};
|
||||||
|
cmpy_b_imag <= (din_imag == {1'b1,{(DATA_I_WIDTH-1){1'b0}}}) ? {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH+1){1'b0}},{(DATA_I_WIDTH-1){1'b1}}} : -{{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag};
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
// truncate msb
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
cmpy_a_real <= 'b0;
|
||||||
|
cmpy_a_imag <= 'b0;
|
||||||
|
cmpy_b_real <= 'b0;
|
||||||
|
cmpy_b_imag <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cmpy_a_real <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
|
||||||
|
cmpy_a_imag <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
|
||||||
|
cmpy_b_real <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
|
||||||
|
cmpy_b_imag <= (din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH] == {1'b1,{(CMPY_I_WIDTH-1){1'b0}}}) ? {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH+1){1'b0}},{(CMPY_I_WIDTH-1){1'b1}}} : -{{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// truncate valid bits
|
||||||
|
assign cmpy_p_real = cmpy_p_raw_real[0 +: CMPY_P_VALID_WIDTH];
|
||||||
|
assign cmpy_p_imag = cmpy_p_raw_imag[0 +: CMPY_P_VALID_WIDTH];
|
||||||
|
|
||||||
|
|
||||||
|
wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_a;
|
||||||
|
wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_b;
|
||||||
|
wire [2*AXIS_CMPY_P_WIDTH-1:0] cmpy_p;
|
||||||
|
wire cmpy_p_vld;
|
||||||
|
|
||||||
|
assign cmpy_a = {cmpy_a_imag,cmpy_a_real};
|
||||||
|
assign cmpy_b = {cmpy_b_imag,cmpy_b_real};
|
||||||
|
assign {cmpy_p_raw_imag,cmpy_p_raw_real} = cmpy_p;
|
||||||
|
|
||||||
|
cmpy_18x18_mult u_cmpy_18x18
|
||||||
|
(
|
||||||
|
.aclk (clk ), // input wire aclk
|
||||||
|
.s_axis_a_tvalid (cal_busy ), // input wire s_axis_a_tvalid
|
||||||
|
.s_axis_a_tdata (cmpy_a ), // input wire [31 : 0] s_axis_a_tdata
|
||||||
|
.s_axis_b_tvalid (cal_busy ), // input wire s_axis_b_tvalid
|
||||||
|
.s_axis_b_tdata (cmpy_b ), // input wire [31 : 0] s_axis_b_tdata
|
||||||
|
.m_axis_dout_tvalid (cmpy_p_vld ), // output wire m_axis_dout_tvalid
|
||||||
|
.m_axis_dout_tdata (cmpy_p ) // output wire [63 : 0] m_axis_dout_tdata
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
// accumulation
|
||||||
|
reg [ACCUM_WIDTH-1 : 0] accum = 'b0;
|
||||||
|
reg [DATA_O_WIDTH-1 : 0] var_buf = 'b0;
|
||||||
|
|
||||||
|
assign var = var_buf;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
accum <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
if (cmpy_p_vld) begin
|
||||||
|
accum <= accum + cmpy_p_real;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
accum <= 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
if (DATA_O_WIDTH > ACCUM_WIDTH) begin
|
||||||
|
// sign-bit extension to fit output data width
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
var_buf <= 'b0;
|
||||||
|
end
|
||||||
|
else if (last_data_d[5]) begin
|
||||||
|
var_buf <= {{(DATA_O_WIDTH-ACCUM_WIDTH){accum[ACCUM_WIDTH-1]}},accum};
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
// truncate msb
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (rst) begin
|
||||||
|
var_buf <= 'b0;
|
||||||
|
end
|
||||||
|
else if (last_data_d[5]) begin
|
||||||
|
var_buf <= accum[ACCUM_WIDTH-1 -: DATA_O_WIDTH];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,271 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||||
|
<!-- -->
|
||||||
|
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||||
|
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||||
|
|
||||||
|
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/Workspace/vivado/vivado_pub/modules/xc7k410tffg900-2/var_cal/var_cal.xpr">
|
||||||
|
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||||
|
<Configuration>
|
||||||
|
<Option Name="Id" Val="50c9ae21b7244457977e96017e983c18"/>
|
||||||
|
<Option Name="Part" Val="xc7k410tffg900-2"/>
|
||||||
|
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||||
|
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||||
|
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||||
|
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||||
|
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||||
|
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||||
|
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||||
|
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||||
|
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||||
|
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||||
|
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||||
|
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||||
|
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||||
|
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||||
|
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||||
|
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||||
|
<Option Name="BoardPart" Val=""/>
|
||||||
|
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||||
|
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="ProjectType" Val="Default"/>
|
||||||
|
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||||
|
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||||
|
<Option Name="IPCachePermission" Val="read"/>
|
||||||
|
<Option Name="IPCachePermission" Val="write"/>
|
||||||
|
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||||
|
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||||
|
<Option Name="SimCompileState" Val="TRUE"/>
|
||||||
|
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||||
|
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||||
|
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||||
|
<Option Name="EnableBDX" Val="FALSE"/>
|
||||||
|
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||||
|
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTXSimExportSim" Val="1"/>
|
||||||
|
<Option Name="WTModelSimExportSim" Val="1"/>
|
||||||
|
<Option Name="WTQuestaExportSim" Val="1"/>
|
||||||
|
<Option Name="WTIesExportSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsExportSim" Val="1"/>
|
||||||
|
<Option Name="WTRivieraExportSim" Val="1"/>
|
||||||
|
<Option Name="WTActivehdlExportSim" Val="1"/>
|
||||||
|
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||||
|
<Option Name="XSimRadix" Val="hex"/>
|
||||||
|
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||||
|
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||||
|
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||||
|
<Option Name="SimTypes" Val="rtl"/>
|
||||||
|
<Option Name="SimTypes" Val="bfm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||||
|
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||||
|
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||||
|
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||||
|
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||||
|
</Configuration>
|
||||||
|
<FileSets Version="1" Minor="32">
|
||||||
|
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||||
|
<Filter Type="Srcs"/>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/var_cal.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="var_cal"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||||
|
<Filter Type="Constrs"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="ConstrsType" Val="XDC"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||||
|
<File Path="$PSRCDIR/sim_1/new/tb_var_cal.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="AutoDisabled" Val="1"/>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="var_cal"/>
|
||||||
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
<Option Name="TransportPathDelay" Val="0"/>
|
||||||
|
<Option Name="TransportIntDelay" Val="0"/>
|
||||||
|
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||||
|
<Option Name="PamDesignTestbench" Val=""/>
|
||||||
|
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||||
|
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||||
|
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||||
|
<Option Name="SrcSet" Val="sources_1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||||
|
<Filter Type="Utils"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="cmpy_18x18_mult" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_18x18_mult" RelGenDir="$PGENDIR/cmpy_18x18_mult">
|
||||||
|
<File Path="$PSRCDIR/sources_1/ip/cmpy_18x18_mult/cmpy_18x18_mult.xci">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopModule" Val="cmpy_18x18_mult"/>
|
||||||
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
</FileSets>
|
||||||
|
<Simulators>
|
||||||
|
<Simulator Name="XSim">
|
||||||
|
<Option Name="Description" Val="Vivado Simulator"/>
|
||||||
|
<Option Name="CompiledLib" Val="0"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ModelSim">
|
||||||
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Questa">
|
||||||
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Xcelium">
|
||||||
|
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="VCS">
|
||||||
|
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Riviera">
|
||||||
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
</Simulators>
|
||||||
|
<Runs Version="1" Minor="21">
|
||||||
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="cmpy_18x18_mult_synth_1" Type="Ft3:Synth" SrcSet="cmpy_18x18_mult" Part="xc7k410tffg900-2" ConstrsSet="cmpy_18x18_mult" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/cmpy_18x18_mult_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_18x18_mult_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_18x18_mult_synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="cmpy_18x18_mult_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="cmpy_18x18_mult" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="cmpy_18x18_mult_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_18x18_mult_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_18x18_mult_impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
</Runs>
|
||||||
|
<Board/>
|
||||||
|
<DashboardSummary Version="1" Minor="0">
|
||||||
|
<Dashboards>
|
||||||
|
<Dashboard Name="default_dashboard">
|
||||||
|
<Gadgets>
|
||||||
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||||
|
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||||
|
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
</Gadgets>
|
||||||
|
</Dashboard>
|
||||||
|
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||||
|
</Dashboards>
|
||||||
|
</DashboardSummary>
|
||||||
|
</Project>
|
||||||
Reference in New Issue
Block a user