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3
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a8ea62ab3d
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ca75a51f75
| Author | SHA1 | Date | |
|---|---|---|---|
 josh
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ca75a51f75 | ||
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josh
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8a5c992b1c | ||
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josh
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eb40f1ba27 |
+3080
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+6152
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+776
@@ -0,0 +1,776 @@
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; XILINX CORE Generator v1.0
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; Copyright 2023 Gatsby Van <[email protected]>
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; generated by MATLAB 23.2 (R2023b)
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; generated at: 15-Jan-2024 11:07:53 +0800
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||||
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|
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
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|
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|
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|
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|
||||
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|
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|
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|
||||
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|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
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|
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|
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||||
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|
||||
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|
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|
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|
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"mode": "master",
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||||
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|
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|
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|
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|
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|
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+349
@@ -0,0 +1,349 @@
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||||
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||||
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|
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+627
@@ -0,0 +1,627 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/03/23 20:17:56
|
||||
// Last Modified Date: 2023/03/10 15:41
|
||||
// Design Name:
|
||||
// Module Name: tx_qpsk_poly
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// 20230228-1541 - 修改不扫频、无基带频偏时 [baseband_i/q] 的数据输出，原来从
|
||||
// 乘法器引出，会导致频率为 0 时输出数据错误，现在直接从基带数据引出。
|
||||
// 20230310-1542 - 增加输入参数，发送数据更改为直接由参数输入，发送方波改为 8
|
||||
// 倍过采样，发送双音信号中 1MHz 信号的频率控制字可以根据参数中的时钟频率计
|
||||
// 算得出。
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module tx_qpsk_poly
|
||||
#(
|
||||
parameter DATA_WIDTH = 12, // need to be <= 16
|
||||
parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
|
||||
parameter BIT_DATA_LEN = 128,
|
||||
parameter SQUARE_INTERP = 8,
|
||||
parameter CLK_FREQ = 245_760_000*8, // in Hertz
|
||||
parameter PARALLEL_NUM = 8
|
||||
)
|
||||
(
|
||||
input clk ,
|
||||
input rst ,
|
||||
output [DATA_WIDTH-1:0] tx_data_i ,
|
||||
output [DATA_WIDTH-1:0] tx_data_q ,
|
||||
// debug ports
|
||||
input [ 1:0] waveform_sel ,
|
||||
input sweep_on ,
|
||||
input [31:0] freq_set ,
|
||||
input [ 1:0] iq_sel ,
|
||||
input [ 3:0] bb_rshift
|
||||
);
|
||||
|
||||
localparam RCOS_INTERP = 64*PARALLEL_NUM;
|
||||
localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP;
|
||||
localparam FREQ_WORD_1M = (64'd2)**(64'd16)*(64'd1_000_000)/CLK_FREQ;
|
||||
|
||||
integer i;
|
||||
genvar m;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
///////////////////////////////// Data Counter /////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// symbol & interpolation counter
|
||||
reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0] cnt = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt <= 'b0;
|
||||
end
|
||||
else begin
|
||||
cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// address
|
||||
reg [$clog2(BIT_DATA_LEN)-1 : 0] bit_data_addr_i = 'b0;
|
||||
reg [$clog2(BIT_DATA_LEN)-1 : 0] bit_data_addr_q = 'b1;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
bit_data_addr_i <= 'b0;
|
||||
bit_data_addr_q <= 'b1;
|
||||
end
|
||||
else begin
|
||||
bit_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0};
|
||||
bit_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1};
|
||||
end
|
||||
end
|
||||
|
||||
// bit data
|
||||
reg bit_data_i = 'b0;
|
||||
reg bit_data_q = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
bit_data_i <= 'b0;
|
||||
bit_data_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
bit_data_i <= BIT_DATA[bit_data_addr_i];
|
||||
bit_data_q <= BIT_DATA[bit_data_addr_q];
|
||||
end
|
||||
end
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////// Root-Rasied Cosine Shaping Filter ///////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// polarization
|
||||
wire [7:0] hrc_data_polar_i;
|
||||
wire [7:0] hrc_data_polar_q;
|
||||
|
||||
assign hrc_data_polar_i = {{7{bit_data_i}},1'b1};
|
||||
assign hrc_data_polar_q = {{7{bit_data_q}},1'b1};
|
||||
|
||||
// root raised cosine shaping-filter
|
||||
wire [24*PARALLEL_NUM-1 : 0] hrc_wave_i;
|
||||
wire [24*PARALLEL_NUM-1 : 0] hrc_wave_q;
|
||||
|
||||
wire [23:0] hrc_wave_i_par [0 : PARALLEL_NUM-1];
|
||||
wire [23:0] hrc_wave_q_par [0 : PARALLEL_NUM-1];
|
||||
|
||||
generate
|
||||
|
||||
for (m = 0; m < PARALLEL_NUM; m = m + 1) begin
|
||||
assign hrc_wave_i_par[m] = hrc_wave_i[24*m +: 24];
|
||||
assign hrc_wave_q_par[m] = hrc_wave_q[24*m +: 24];
|
||||
end
|
||||
|
||||
case (PARALLEL_NUM)
|
||||
1: begin
|
||||
hrc_64_12_025 u_hrc_i
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready ( ), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (hrc_wave_i ) // output wire [23 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
hrc_64_12_025 u_hrc_q
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready ( ), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (hrc_wave_q ) // output wire [23 : 0] m_axis_data_tdata
|
||||
);
|
||||
end
|
||||
4: begin
|
||||
hrc_256_12_025 u_hrc_i
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready ( ), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (hrc_wave_i ) // output wire [95 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
hrc_256_12_025 u_hrc_q
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready ( ), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (hrc_wave_q ) // output wire [95 : 0] m_axis_data_tdata
|
||||
);
|
||||
end
|
||||
8: begin
|
||||
hrc_512_12_025 u_hrc_i
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready ( ), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (hrc_wave_i ) // output wire [191 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
hrc_512_12_025 u_hrc_q
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready ( ), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (hrc_wave_q ) // output wire [191 : 0] m_axis_data_tdata
|
||||
);
|
||||
end
|
||||
default: begin
|
||||
hrc_64_12_025 u_hrc_i
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready ( ), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (hrc_wave_i ) // output wire [23 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
hrc_64_12_025 u_hrc_q
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready ( ), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (hrc_wave_q ) // output wire [23 : 0] m_axis_data_tdata
|
||||
);
|
||||
end
|
||||
endcase
|
||||
|
||||
endgenerate
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////// Square Shaping Filter /////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// square shaping-filter
|
||||
reg [17:0] hsq_wave_i ='b0;
|
||||
reg [17:0] hsq_wave_q ='b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
hsq_wave_i <= 'b0;
|
||||
hsq_wave_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
hsq_wave_i <= bit_data_i ? 18'b01_1111_1111_1111_1111 : 18'b10_0000_0000_0000_0001;
|
||||
hsq_wave_q <= bit_data_q ? 18'b10_0000_0000_0000_0001 : 18'b01_1111_1111_1111_1111;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////// Two Tone Signal ////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// cosine wave with freq of 1 MHz
|
||||
wire signed [16*PARALLEL_NUM-1 : 0] cos_1m;
|
||||
wire signed [16*PARALLEL_NUM-1 : 0] sin_1m;
|
||||
|
||||
wire signed [15 : 0] cos_1m_par [0 : PARALLEL_NUM-1];
|
||||
wire signed [15 : 0] sin_1m_par [0 : PARALLEL_NUM-1];
|
||||
|
||||
generate
|
||||
for (m = 0; m < PARALLEL_NUM; m = m + 1) begin
|
||||
assign cos_1m_par[m] = cos_1m[16*m +: 16];
|
||||
assign sin_1m_par[m] = sin_1m[16*m +: 16];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
dds_par #(
|
||||
.PHASE_WIDTH (16 ),
|
||||
.WAVE_WIDTH (16 ),
|
||||
.PARALLEL_NUM (PARALLEL_NUM )
|
||||
)
|
||||
(
|
||||
.clk (clk ),
|
||||
.rst (rst ),
|
||||
|
||||
.phase_inc(FREQ_WORD_1M ),
|
||||
|
||||
.cos_wave (cos_1m ),
|
||||
.sin_wave (sin_1m )
|
||||
);
|
||||
|
||||
// two-tone signal
|
||||
reg signed [15:0] two_tone_wave_i [0 : PARALLEL_NUM-1];
|
||||
reg signed [15:0] two_tone_wave_q [0 : PARALLEL_NUM-1];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
for (i = 0; i < PARALLEL_NUM; i = i + 1) begin
|
||||
two_tone_wave_i[i] <= 'b0;
|
||||
two_tone_wave_q[i] <= 'b0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
for (i = 0; i < PARALLEL_NUM; i = i + 1) begin
|
||||
two_tone_wave_i[i] <= (cos_1m[i] >>> 1) + 16'h3fff;
|
||||
two_tone_wave_q[i] <= (sin_1m[i] >>> 1) + 16'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
///////////////////// Waveform Selection & Hopping Control /////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// baseband signal select
|
||||
reg [15:0] baseband_sel_i [0 : PARALLEL_NUM-1];
|
||||
reg [15:0] baseband_sel_q [0 : PARALLEL_NUM-1];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
for (i = 0; i < PARALLEL_NUM; i = i + 1) begin
|
||||
baseband_sel_i[i] <= 'b0;
|
||||
baseband_sel_q[i] <= 'b0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
for (i = 0; i < PARALLEL_NUM; i = i + 1) begin
|
||||
case (waveform_sel[1:0])
|
||||
2'd0: begin
|
||||
baseband_sel_i[i] <= hrc_wave_i_par[i][0 +: 16];
|
||||
baseband_sel_q[i] <= hrc_wave_q_par[i][0 +: 16];
|
||||
end
|
||||
2'd1: begin
|
||||
baseband_sel_i[i] <= hsq_wave_i[17:0];
|
||||
baseband_sel_q[i] <= hsq_wave_q[17:0];
|
||||
end
|
||||
2'd2: begin
|
||||
baseband_sel_i[i] <= 16'h7fff;
|
||||
baseband_sel_q[i] <= 16'b0;
|
||||
end
|
||||
2'd3: begin
|
||||
baseband_sel_i[i] <= two_tone_wave_i[i];
|
||||
baseband_sel_q[i] <= two_tone_wave_q[i];
|
||||
end
|
||||
default: begin
|
||||
baseband_sel_i[i] <= hrc_wave_i_par[i][0 +: 16];
|
||||
baseband_sel_q[i] <= hrc_wave_q_par[i][0 +: 16];
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// hopping control, 3750hop/s
|
||||
reg [23:0] sweep_rom_addr = 'b0;
|
||||
wire [31:0] freq_sweep;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
sweep_rom_addr <= 'b0;
|
||||
end
|
||||
else if (sweep_on) begin
|
||||
sweep_rom_addr <= sweep_rom_addr + 24'b1;
|
||||
end
|
||||
else begin
|
||||
sweep_rom_addr <= 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
hop_rom u_sweep_rom
|
||||
(
|
||||
.clka (clk ), // input wire clka
|
||||
.addra (sweep_rom_addr[23:16] ), // input wire [7 : 0] addra
|
||||
.douta (freq_sweep ) // output wire [31 : 0] douta
|
||||
);
|
||||
|
||||
// choose the actual frequency word
|
||||
reg [31:0] freq_word = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
freq_word <= 'b0;
|
||||
end
|
||||
else if (sweep_on) begin
|
||||
// frequency sweep
|
||||
freq_word <= freq_sweep;
|
||||
end
|
||||
else begin
|
||||
// normal operation
|
||||
freq_word <= freq_set;
|
||||
end
|
||||
end
|
||||
|
||||
// baseband frequency shift carrier generation
|
||||
wire [ 7:0] cos_dds;
|
||||
wire [ 7:0] sin_dds;
|
||||
reg [ 7:0] cos = 'b0;
|
||||
reg [ 7:0] sin = 'b0;
|
||||
|
||||
dds_32b_8b u_dds_bb_shift (
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_config_tvalid (~rst ), // input wire s_axis_config_tvalid
|
||||
.s_axis_config_tdata (freq_word ), // input wire [31 : 0] s_axis_config_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata ({sin_dds,cos_dds}) // output wire [31 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cos <= 'b0;
|
||||
sin <= 'b0;
|
||||
end
|
||||
else if (freq_word == 'b0) begin
|
||||
// to make sure the carriers stay at the right position when freq = 0
|
||||
cos <= 8'b0111_1111;
|
||||
sin <= 8'b0111_1111;
|
||||
end
|
||||
else begin
|
||||
cos <= cos_dds;
|
||||
sin <= sin_dds;
|
||||
end
|
||||
end
|
||||
|
||||
// baseband frequency shift modulation
|
||||
wire [47:0] mod_cmpy_a;
|
||||
wire [15:0] mod_cmpy_b;
|
||||
wire [63:0] mod_cmpy_out;
|
||||
|
||||
wire [26:0] baseband_mult_i;
|
||||
wire [26:0] baseband_mult_q;
|
||||
|
||||
assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i};
|
||||
assign mod_cmpy_b = {-sin,cos};
|
||||
|
||||
assign baseband_mult_i = mod_cmpy_out[58:32];
|
||||
assign baseband_mult_q = mod_cmpy_out[26: 0];
|
||||
|
||||
cmpy_18x8 u_cmpy_18x8
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_a_tvalid (1'b1 ), // input wire s_axis_a_tvalid
|
||||
.s_axis_a_tdata (mod_cmpy_a ), // input wire [47 : 0] s_axis_a_tdata
|
||||
.s_axis_b_tvalid (1'b1 ), // input wire s_axis_b_tvalid
|
||||
.s_axis_b_tdata (mod_cmpy_b ), // input wire [15 : 0] s_axis_b_tdata
|
||||
.m_axis_dout_tvalid ( ), // output wire m_axis_dout_tvalid
|
||||
.m_axis_dout_tdata (mod_cmpy_out ) // output wire [63 : 0] m_axis_dout_tdata
|
||||
);
|
||||
|
||||
// truncate to 16-bit
|
||||
reg signed [15:0] baseband_i = 'b0;
|
||||
reg signed [15:0] baseband_q = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
baseband_i <= 'b0;
|
||||
baseband_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
case (waveform_sel[1:0])
|
||||
2'd0: begin
|
||||
// scale rasied-cosine-shaped bpsk signal by 1.125 or 1.625
|
||||
baseband_i <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_i[17 -: 16] + {{3{baseband_sel_i[17]}},baseband_sel_i[17 -: 13]}) : (baseband_mult_i[25:10] + {baseband_mult_i[25],baseband_mult_i[25:11]} + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]});
|
||||
baseband_q <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_q[17 -: 16] + {{3{baseband_sel_q[17]}},baseband_sel_q[17 -: 13]}) : (baseband_mult_q[25:10] + {baseband_mult_q[25],baseband_mult_q[25:11]} + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]});
|
||||
end
|
||||
2'd1: begin
|
||||
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : (baseband_mult_i[25:10] + {{2{baseband_mult_i[25]}},baseband_mult_i[25:12]});
|
||||
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : (baseband_mult_q[25:10] + {{2{baseband_mult_q[25]}},baseband_mult_q[25:12]});
|
||||
end
|
||||
2'd2: begin
|
||||
baseband_i <= baseband_mult_i[24:9];
|
||||
baseband_q <= baseband_mult_q[24:9];
|
||||
end
|
||||
2'd3: begin
|
||||
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9];
|
||||
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9];
|
||||
end
|
||||
default: begin
|
||||
// scale rasied-cosine-shaped bpsk signal by 1.125
|
||||
baseband_i <= baseband_mult_i[25:10] + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]};
|
||||
baseband_q <= baseband_mult_q[25:10] + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// iq selection & baseband right shift
|
||||
reg signed [15:0] baseband_data_i = 'b0;
|
||||
reg signed [15:0] baseband_data_q = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
baseband_data_i <= 'b0;
|
||||
baseband_data_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
// inphase selection
|
||||
if (iq_sel[1]) begin
|
||||
baseband_data_i <= baseband_i >>> bb_rshift;
|
||||
end
|
||||
else begin
|
||||
baseband_data_i <= 'b0;
|
||||
end
|
||||
// quadrature selection
|
||||
if (iq_sel[0]) begin
|
||||
baseband_data_q <= baseband_q >>> bb_rshift;
|
||||
end
|
||||
else begin
|
||||
baseband_data_q <= 'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// output data to ports
|
||||
assign tx_data_i = baseband_data_i[15 -: DATA_WIDTH];
|
||||
assign tx_data_q = baseband_data_q[15 -: DATA_WIDTH];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2020/12/08 12:43:46
|
||||
// Design Name:
|
||||
// Module Name: tb_tx_qpsk
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
// module tb_tx_qpsk;
|
||||
|
||||
// reg clk = 1'b0 ;
|
||||
// reg rst = 1'b1 ;
|
||||
// reg tx_on = 1'b1 ;
|
||||
// reg [31:0] freq_set ;
|
||||
// reg [ 1:0] waveform_sel = 2'b00;
|
||||
// reg [ 1:0] iq_sel = 2'b11 ;
|
||||
// wire [11:0] tx_data_i ;
|
||||
// wire [11:0] tx_data_q ;
|
||||
// reg [ 3:0] bb_rshift = 5'b0 ;
|
||||
|
||||
// tx_qpsk u_tx_qpsk
|
||||
// (
|
||||
// .clk (clk ),
|
||||
// .rst (rst ),
|
||||
// .tx_data_i (tx_data_i ),
|
||||
// .tx_data_q (tx_data_q ),
|
||||
// .waveform_sel (waveform_sel ),
|
||||
// .sweep_on (1'b0 ),
|
||||
// // .freq_set (32'd447392426 ),
|
||||
// .freq_set (32'd0 ),
|
||||
// .iq_sel (iq_sel ),
|
||||
// .bb_rshift (bb_rshift )
|
||||
// );
|
||||
|
||||
// initial begin
|
||||
// #102
|
||||
// rst = 1'b0;
|
||||
// // freq_set = 32'd873813333;
|
||||
// // waveform_sel = 2'b00;
|
||||
// // bb_rshift = 5'd0;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd1;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd2;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd3;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd4;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd5;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd6;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd7;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd8;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd9;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd14;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd15;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd16;
|
||||
// // freq_set = 32'd0;
|
||||
// // func_sel = 3'b010;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // func_sel = 3'b100;
|
||||
// // #7777
|
||||
// // freq_set = 32'd0;
|
||||
// // func_sel = 3'b100;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // func_sel = 3'b010;
|
||||
// // #7777
|
||||
// // freq_set = 32'd0;
|
||||
// // func_sel = 3'b010;
|
||||
// // freq_set = 32'd536870912;
|
||||
// // iq_sel = 2'b00;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // iq_sel = 2'b01;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // iq_sel = 2'b10;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // iq_sel = 2'b11;
|
||||
// end
|
||||
|
||||
// always #5 clk = ~clk;
|
||||
|
||||
// // integer i;
|
||||
// // integer w_file;
|
||||
|
||||
// // initial begin
|
||||
// // w_file = $fopen("D:\\qpsk_josh.txt","w");
|
||||
// // for (i = 0; i <= 35000; i = i + 1) begin
|
||||
// // wait(clk);
|
||||
// // #10;
|
||||
// // $fdisplay(w_file,"%d %d",$signed(tx_data_i),
|
||||
// // $signed(tx_data_q));
|
||||
// // if (i == 35000) begin
|
||||
// // $fclose(w_file);
|
||||
// // $stop;
|
||||
// // end
|
||||
// // end
|
||||
// // end
|
||||
|
||||
// endmodule
|
||||
@@ -0,0 +1,395 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/Workspace/vivado-git-new/modules/xczu48dr-fsvg1517-2-i/tx_qpsk_poly/tx_qpsk_poly.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="fe1ad6990cf04f9197091f4875cffe86"/>
|
||||
<Option Name="Part" Val="xczu48dr-fsvg1517-2-i"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="5"/>
|
||||
<Option Name="WTModelSimExportSim" Val="5"/>
|
||||
<Option Name="WTQuestaExportSim" Val="5"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="5"/>
|
||||
<Option Name="WTRivieraExportSim" Val="5"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="5"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../dds_par/dds_par.srcs/sources_1/ip/cos_16384_16b/cos_16384_16b.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../dds_par/dds_par.srcs/sources_1/new/addr_to_wave.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../dds_par/dds_par.srcs/sources_1/new/dds_par.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/tx_qpsk_poly.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/ip/coe/hrc_64_12_025.coe">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/ip/coe/hrc_256_12_025.coe">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/ip/coe/hrc_512_12_025.coe">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../dds_par/dds_par.srcs/sources_1/ip/coe/cos_16384_16b.coe">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="tx_qpsk_poly"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="tx_qpsk_poly"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="hrc_64_12_025" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_64_12_025" RelGenDir="$PGENDIR/hrc_64_12_025">
|
||||
<File Path="$PSRCDIR/sources_1/ip/hrc_64_12_025/hrc_64_12_025.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="hrc_64_12_025"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="hrc_256_12_025" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_256_12_025" RelGenDir="$PGENDIR/hrc_256_12_025">
|
||||
<File Path="$PSRCDIR/sources_1/ip/hrc_256_12_025/hrc_256_12_025.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="hrc_256_12_025"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="hrc_512_12_025" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_512_12_025" RelGenDir="$PGENDIR/hrc_512_12_025">
|
||||
<File Path="$PSRCDIR/sources_1/ip/hrc_512_12_025/hrc_512_12_025.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="hrc_512_12_025"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="hrc_64_12_025_synth_1" Type="Ft3:Synth" SrcSet="hrc_64_12_025" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="hrc_64_12_025" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hrc_64_12_025_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="hrc_256_12_025_synth_1" Type="Ft3:Synth" SrcSet="hrc_256_12_025" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="hrc_256_12_025" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hrc_256_12_025_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_256_12_025_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_256_12_025_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="hrc_512_12_025_synth_1" Type="Ft3:Synth" SrcSet="hrc_512_12_025" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="hrc_512_12_025" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hrc_512_12_025_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_512_12_025_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_512_12_025_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="hrc_64_12_025_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="hrc_64_12_025" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hrc_64_12_025_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="hrc_256_12_025_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="hrc_256_12_025" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hrc_256_12_025_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_256_12_025_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_256_12_025_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="hrc_512_12_025_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="hrc_512_12_025" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hrc_512_12_025_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_512_12_025_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_512_12_025_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -1,3 +1,3 @@
|
||||
version https://git-lfs.github.com/spec/v1
|
||||
oid sha256:947ec7e9dc96ab17f03fe3a4c3f0deebd51bf1ef3d6930694a97405465be017e
|
||||
size 1086030
|
||||
oid sha256:fb8b4c535ad8d52382fab27f69421ec5552cdc509ed9af9b661da148fe2ef6d5
|
||||
size 1071933
|
||||
|
||||
@@ -1,3 +1,3 @@
|
||||
version https://git-lfs.github.com/spec/v1
|
||||
oid sha256:a90a219463fc6463674d91246b22f422d23c3bdcef4f6dd37a75f2d261b3d5ca
|
||||
oid sha256:7945df8e1e7bb83e4729a18293fbba31c53a298e36013b1aad73acff107a9109
|
||||
size 13321510
|
||||
|
||||
+11
-11
@@ -135,7 +135,7 @@
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "12", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -213,7 +213,7 @@
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -222,15 +222,15 @@
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -272,7 +272,7 @@
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
||||
-376
@@ -1,376 +0,0 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_axi_gpio_0_0",
|
||||
"cell_name": "axi_gpio_hop",
|
||||
"component_reference": "xilinx.com:ip:axi_gpio:2.0",
|
||||
"ip_revision": "33",
|
||||
"gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_axi_gpio_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_TRI_DEFAULT": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_GPIO_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_GPIO2_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_IS_DUAL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_INPUTS": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_TRI_DEFAULT_2": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_DOUT_DEFAULT_2": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_DOUT_DEFAULT": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_ALL_INPUTS_2": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_INTERRUPT_PRESENT": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_axi_gpio_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"GPIO_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"GPIO2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_ALL_OUTPUTS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_ALL_OUTPUTS_2": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "9", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||
"C_GPIO_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_GPIO2_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_INPUTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_INPUTS_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_OUTPUTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_OUTPUTS_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INTERRUPT_PRESENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DOUT_DEFAULT": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_TRI_DEFAULT": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_IS_DUAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DOUT_DEFAULT_2": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_TRI_DEFAULT_2": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "33" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_axi_gpio_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"ip2intc_irpt": [ { "direction": "out" } ],
|
||||
"gpio_io_i": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "9", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"IP2INTC_IRQ": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"INTERRUPT": [ { "physical_name": "ip2intc_irpt" } ]
|
||||
}
|
||||
},
|
||||
"GPIO": {
|
||||
"vlnv": "xilinx.com:interface:gpio:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:gpio_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "GPIO_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TRI_I": [ { "physical_name": "gpio_io_i" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI",
|
||||
"address_blocks": {
|
||||
"Reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Reg",
|
||||
"description": "Register Block",
|
||||
"usage": "register",
|
||||
"access": "read-write",
|
||||
"registers": {
|
||||
"GPIO_DATA": {
|
||||
"address_offset": "0x0",
|
||||
"size": 1,
|
||||
"display_name": "Channel_1_GPIO_DATA",
|
||||
"description": "Channel-1 AXI GPIO Data register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"CH1_DATA": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_1_GPIO_DATA",
|
||||
"description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"GPIO_TRI": {
|
||||
"address_offset": "0x4",
|
||||
"size": 1,
|
||||
"display_name": "Channel_1_GPIO_TRI",
|
||||
"description": "Channel-1 AXI GPIO 3-State Control register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"CH1_TRI": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_1_GPIO_DATA",
|
||||
"description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"GPIO2_DATA": {
|
||||
"address_offset": "0x8",
|
||||
"size": 32,
|
||||
"display_name": "Channel_2_GPIO_DATA",
|
||||
"description": "Channel-2 AXI GPIO Data register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"CH2_DATA": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Channel_2_GPIO_DATA",
|
||||
"description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"GPIO2_TRI": {
|
||||
"address_offset": "0xC",
|
||||
"size": 32,
|
||||
"display_name": "Channel_2_GPIO_TRI",
|
||||
"description": "Channel-2 AXI GPIO 3-State Control register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"CH2_TRI": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Channel_2_GPIO_DATA",
|
||||
"description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"GIER": {
|
||||
"address_offset": "0x11C",
|
||||
"size": 32,
|
||||
"display_name": "Global_Interrupt_Enable register",
|
||||
"description": "Global_Interrupt_Enable register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"INT_EN": {
|
||||
"bit_offset": 31,
|
||||
"bit_width": 1,
|
||||
"display_name": "Global_Interrupt_Enable",
|
||||
"description": "Master enable for the device interrupt output\n 0 - Disabled\n 1 - Enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"IP_IER": {
|
||||
"address_offset": "0x128",
|
||||
"size": 32,
|
||||
"display_name": "IP Interrupt Enable register",
|
||||
"description": "IP Interrupt Enable register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"CH1_INT_EN": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_1_Interrupt_Enable",
|
||||
"description": "Enable Channel 1 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"CH2_INT_EN": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_2_Interrupt_Enable",
|
||||
"description": "Enable Channel 2 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"IP_ISR": {
|
||||
"address_offset": "0x120",
|
||||
"size": 32,
|
||||
"display_name": "IP Interrupt Status register",
|
||||
"description": "IP Interrupt Status register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"CH1_INT_S": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_1_Interrupt_Status",
|
||||
"description": "Channel 1 Interrupt Status\n 0 - No Channel 1 input interrupt\n 1 - Channel 1 input interrupt\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"CH2_INT_S": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_2_Interrupt_Status",
|
||||
"description": "Channel 2 Interrupt Status\n 0 - No Channel 2 input interrupt\n 1 - Channel 2 input interrupt\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"NUM_SI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_MI": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_MI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"STRATEGY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_ADVANCED_OPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_PROTOCOL_CHECKERS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
|
||||
+5
-5
@@ -109,7 +109,7 @@
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
@@ -133,8 +133,8 @@
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
@@ -215,7 +215,7 @@
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "spi_engine_ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "spi_resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
@@ -243,7 +243,7 @@
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "spi_engine_offload_ctrl0:s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
|
||||
+7
-7
@@ -255,7 +255,7 @@
|
||||
"PCW_USE_S_AXI_HP1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_S_AXI_HP2": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_S_AXI_HP3": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_FREQMHZ": [ { "value": "50", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_FREQMHZ": [ { "value": "50.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP1_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_GP0_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_GP1_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
@@ -326,7 +326,7 @@
|
||||
"PCW_S_AXI_HP2_DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_S_AXI_HP3_ID_WIDTH": [ { "value": "6", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_HP3_DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_NUM_F2P_INTR_INPUTS": [ { "value": "2", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_NUM_F2P_INTR_INPUTS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_DDR": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_SMC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_QSPI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -919,7 +919,7 @@
|
||||
"C_S_AXI_HP3_DATA_WIDTH": [ { "value": "64", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_GP0_THREAD_ID_WIDTH": [ { "value": "12", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_GP1_THREAD_ID_WIDTH": [ { "value": "12", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_F2P_INTR_INPUTS": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_F2P_INTR_INPUTS": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_IRQ_F2P_MODE": [ { "value": "DIRECT", "resolve_type": "dependent", "usage": "all" } ],
|
||||
"C_DQ_WIDTH": [ { "value": "32", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_DQS_WIDTH": [ { "value": "4", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
@@ -1020,7 +1020,7 @@
|
||||
"M_AXI_GP0_BRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXI_GP0_RRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXI_GP0_RDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"IRQ_F2P": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"IRQ_F2P": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"FCLK_CLK0": [ { "direction": "out" } ],
|
||||
"FCLK_CLK1": [ { "direction": "out" } ],
|
||||
"FCLK_RESET0_N": [ { "direction": "out" } ],
|
||||
@@ -1132,7 +1132,7 @@
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "12", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
@@ -1250,7 +1250,7 @@
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH:NULL", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"PortWidth": [ { "value": "2", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ]
|
||||
"PortWidth": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"INTERRUPT": [ { "physical_name": "IRQ_F2P" } ]
|
||||
@@ -1262,7 +1262,7 @@
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_GP0", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
|
||||
+1
-1
@@ -76,7 +76,7 @@
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
||||
+1
-1
@@ -143,7 +143,7 @@
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "spi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
|
||||
-1523
File diff suppressed because it is too large
Load Diff
+5
-6
@@ -9,7 +9,7 @@
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_bd_xlconcat_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN0_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN1_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN2_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -138,7 +138,7 @@
|
||||
"IN125_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN126_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN127_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"dout_width": [ { "value": "2", "value_src": "user", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
"dout_width": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"IN0_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@@ -269,8 +269,8 @@
|
||||
"IN125_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN126_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN127_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"dout_width": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
"dout_width": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
@@ -300,8 +300,7 @@
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"In0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"In1": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"dout": [ { "direction": "out", "size_left": "1", "size_right": "0" } ]
|
||||
"dout": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
+25
-272
@@ -1,7 +1,7 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0x8931701A97E97C15",
|
||||
"boundary_crc": "0x6563BD50C34E7A74",
|
||||
"device": "xc7z045ffg900-2",
|
||||
"gen_directory": "../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd",
|
||||
"name": "system_bd",
|
||||
@@ -18,15 +18,11 @@
|
||||
},
|
||||
"rst_ps7_50M": "",
|
||||
"axi_interconnect": {
|
||||
"xbar": "",
|
||||
"s00_couplers": {
|
||||
"auto_pc": ""
|
||||
},
|
||||
"m00_couplers": {},
|
||||
"m01_couplers": {}
|
||||
}
|
||||
},
|
||||
"xlconcat_irq": "",
|
||||
"axi_gpio_hop": ""
|
||||
"xlconcat_irq": ""
|
||||
},
|
||||
"interface_ports": {
|
||||
"ddr": {
|
||||
@@ -231,19 +227,6 @@
|
||||
"right": "0"
|
||||
}
|
||||
}
|
||||
},
|
||||
"gpio_hop": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:gpio:1.0",
|
||||
"vlnv": "xilinx.com:interface:gpio_rtl:1.0",
|
||||
"port_maps": {
|
||||
"TRI_I": {
|
||||
"physical_name": "gpio_hop_tri_i",
|
||||
"direction": "I",
|
||||
"left": "0",
|
||||
"right": "0"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
@@ -1446,7 +1429,7 @@
|
||||
"xci_name": "system_bd_axi_interconnect_0_0",
|
||||
"parameters": {
|
||||
"NUM_MI": {
|
||||
"value": "2"
|
||||
"value": "1"
|
||||
}
|
||||
},
|
||||
"interface_ports": {
|
||||
@@ -1459,11 +1442,6 @@
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
||||
},
|
||||
"M01_AXI": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
@@ -1511,53 +1489,9 @@
|
||||
"M00_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
},
|
||||
"M01_ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "M01_AXI"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "M01_ARESETN"
|
||||
}
|
||||
}
|
||||
},
|
||||
"M01_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"xbar": {
|
||||
"vlnv": "xilinx.com:ip:axi_crossbar:2.1",
|
||||
"ip_revision": "32",
|
||||
"xci_name": "system_bd_xbar_0",
|
||||
"xci_path": "ip/system_bd_xbar_0/system_bd_xbar_0.xci",
|
||||
"inst_hier_path": "axi_interconnect/xbar",
|
||||
"parameters": {
|
||||
"NUM_MI": {
|
||||
"value": "2"
|
||||
},
|
||||
"NUM_SI": {
|
||||
"value": "1"
|
||||
},
|
||||
"STRATEGY": {
|
||||
"value": "0"
|
||||
}
|
||||
},
|
||||
"interface_ports": {
|
||||
"S00_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "Slave",
|
||||
"bridges": [
|
||||
"M00_AXI",
|
||||
"M01_AXI"
|
||||
]
|
||||
}
|
||||
}
|
||||
},
|
||||
"s00_couplers": {
|
||||
"interface_ports": {
|
||||
"M_AXI": {
|
||||
@@ -1659,118 +1593,6 @@
|
||||
]
|
||||
}
|
||||
}
|
||||
},
|
||||
"m00_couplers": {
|
||||
"interface_ports": {
|
||||
"M_AXI": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
||||
},
|
||||
"S_AXI": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"M_ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "M_AXI"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "M_ARESETN"
|
||||
}
|
||||
}
|
||||
},
|
||||
"M_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
},
|
||||
"S_ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "S_AXI"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "S_ARESETN"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"m00_couplers_to_m00_couplers": {
|
||||
"interface_ports": [
|
||||
"S_AXI",
|
||||
"M_AXI"
|
||||
]
|
||||
}
|
||||
}
|
||||
},
|
||||
"m01_couplers": {
|
||||
"interface_ports": {
|
||||
"M_AXI": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
||||
},
|
||||
"S_AXI": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"M_ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "M_AXI"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "M_ARESETN"
|
||||
}
|
||||
}
|
||||
},
|
||||
"M_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
},
|
||||
"S_ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "S_AXI"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "S_ARESETN"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"m01_couplers_to_m01_couplers": {
|
||||
"interface_ports": [
|
||||
"S_AXI",
|
||||
"M_AXI"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
@@ -1780,60 +1602,36 @@
|
||||
"s00_couplers/S_AXI"
|
||||
]
|
||||
},
|
||||
"m00_couplers_to_axi_interconnect": {
|
||||
"interface_ports": [
|
||||
"m00_couplers/M_AXI",
|
||||
"M00_AXI"
|
||||
]
|
||||
},
|
||||
"m01_couplers_to_axi_interconnect": {
|
||||
"interface_ports": [
|
||||
"m01_couplers/M_AXI",
|
||||
"M01_AXI"
|
||||
]
|
||||
},
|
||||
"s00_couplers_to_xbar": {
|
||||
"s00_couplers_to_axi_interconnect": {
|
||||
"interface_ports": [
|
||||
"s00_couplers/M_AXI",
|
||||
"xbar/S00_AXI"
|
||||
]
|
||||
},
|
||||
"xbar_to_m00_couplers": {
|
||||
"interface_ports": [
|
||||
"xbar/M00_AXI",
|
||||
"m00_couplers/S_AXI"
|
||||
]
|
||||
},
|
||||
"xbar_to_m01_couplers": {
|
||||
"interface_ports": [
|
||||
"xbar/M01_AXI",
|
||||
"m01_couplers/S_AXI"
|
||||
"M00_AXI"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"S00_ACLK_1": {
|
||||
"ports": [
|
||||
"S00_ACLK",
|
||||
"s00_couplers/S_ACLK"
|
||||
]
|
||||
},
|
||||
"S00_ARESETN_1": {
|
||||
"ports": [
|
||||
"S00_ARESETN",
|
||||
"s00_couplers/S_ARESETN"
|
||||
]
|
||||
},
|
||||
"axi_interconnect_ACLK_net": {
|
||||
"ports": [
|
||||
"ACLK",
|
||||
"xbar/aclk",
|
||||
"s00_couplers/S_ACLK",
|
||||
"s00_couplers/M_ACLK",
|
||||
"m00_couplers/M_ACLK",
|
||||
"m01_couplers/M_ACLK",
|
||||
"m00_couplers/S_ACLK",
|
||||
"m01_couplers/S_ACLK"
|
||||
"M00_ACLK",
|
||||
"s00_couplers/M_ACLK"
|
||||
]
|
||||
},
|
||||
"axi_interconnect_ARESETN_net": {
|
||||
"ports": [
|
||||
"ARESETN",
|
||||
"xbar/aresetn",
|
||||
"s00_couplers/S_ARESETN",
|
||||
"s00_couplers/M_ARESETN",
|
||||
"m00_couplers/M_ARESETN",
|
||||
"m01_couplers/M_ARESETN",
|
||||
"m00_couplers/S_ARESETN",
|
||||
"m01_couplers/S_ARESETN"
|
||||
"M00_ARESETN",
|
||||
"s00_couplers/M_ARESETN"
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -1846,51 +1644,21 @@
|
||||
"inst_hier_path": "xlconcat_irq",
|
||||
"parameters": {
|
||||
"NUM_PORTS": {
|
||||
"value": "2"
|
||||
"value": "1"
|
||||
},
|
||||
"dout_width": {
|
||||
"value": "2"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axi_gpio_hop": {
|
||||
"vlnv": "xilinx.com:ip:axi_gpio:2.0",
|
||||
"ip_revision": "33",
|
||||
"xci_name": "system_bd_axi_gpio_0_0",
|
||||
"xci_path": "ip/system_bd_axi_gpio_0_0/system_bd_axi_gpio_0_0.xci",
|
||||
"inst_hier_path": "axi_gpio_hop",
|
||||
"parameters": {
|
||||
"C_ALL_INPUTS": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_GPIO_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_INTERRUPT_PRESENT": {
|
||||
"value": "1"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"axi_gpio_hop_GPIO": {
|
||||
"interface_ports": [
|
||||
"gpio_hop",
|
||||
"axi_gpio_hop/GPIO"
|
||||
]
|
||||
},
|
||||
"axi_interconnect_0_M00_AXI": {
|
||||
"interface_ports": [
|
||||
"axi_interconnect/M00_AXI",
|
||||
"axi_spi_engine/s_axi"
|
||||
]
|
||||
},
|
||||
"axi_interconnect_M01_AXI": {
|
||||
"interface_ports": [
|
||||
"axi_interconnect/M01_AXI",
|
||||
"axi_gpio_hop/S_AXI"
|
||||
]
|
||||
},
|
||||
"axi_spi_engine_spi_0": {
|
||||
"interface_ports": [
|
||||
"spi",
|
||||
@@ -1923,12 +1691,6 @@
|
||||
"processing_system7/GPIO_I"
|
||||
]
|
||||
},
|
||||
"axi_gpio_hop_ip2intc_irpt": {
|
||||
"ports": [
|
||||
"axi_gpio_hop/ip2intc_irpt",
|
||||
"xlconcat_irq/In1"
|
||||
]
|
||||
},
|
||||
"axi_spi_engine_active_0": {
|
||||
"ports": [
|
||||
"axi_spi_engine/active",
|
||||
@@ -1950,9 +1712,7 @@
|
||||
"axi_interconnect/ACLK",
|
||||
"axi_interconnect/S00_ACLK",
|
||||
"axi_interconnect/M00_ACLK",
|
||||
"rst_ps7_50M/slowest_sync_clk",
|
||||
"axi_gpio_hop/s_axi_aclk",
|
||||
"axi_interconnect/M01_ACLK"
|
||||
"rst_ps7_50M/slowest_sync_clk"
|
||||
]
|
||||
},
|
||||
"processing_system7_FCLK_CLK1": {
|
||||
@@ -1985,9 +1745,7 @@
|
||||
"axi_spi_engine/s_axi_aresetn",
|
||||
"axi_interconnect/ARESETN",
|
||||
"axi_interconnect/S00_ARESETN",
|
||||
"axi_interconnect/M00_ARESETN",
|
||||
"axi_gpio_hop/s_axi_aresetn",
|
||||
"axi_interconnect/M01_ARESETN"
|
||||
"axi_interconnect/M00_ARESETN"
|
||||
]
|
||||
},
|
||||
"xlconcat_irq_dout": {
|
||||
@@ -2002,11 +1760,6 @@
|
||||
"address_spaces": {
|
||||
"Data": {
|
||||
"segments": {
|
||||
"SEG_axi_gpio_hop_Reg": {
|
||||
"address_block": "/axi_gpio_hop/S_AXI/Reg",
|
||||
"offset": "0x41200000",
|
||||
"range": "64K"
|
||||
},
|
||||
"SEG_axi_spi_engine_axi_lite": {
|
||||
"address_block": "/axi_spi_engine/axi_spi_engine/s_axi/axi_lite",
|
||||
"offset": "0x43C00000",
|
||||
|
||||
-23
@@ -189,24 +189,6 @@
|
||||
"TU": "active"
|
||||
},
|
||||
"V3": {
|
||||
"VT": "AC",
|
||||
"BA": "0x41200000",
|
||||
"HA": "0x4120FFFF",
|
||||
"BP": "C_BASEADDR",
|
||||
"HP": "C_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_axi_gpio_hop_Reg",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/axi_gpio_hop",
|
||||
"SI": "S_AXI",
|
||||
"SS": "Reg",
|
||||
"SV": "xilinx.com:ip:axi_gpio:2.0",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
},
|
||||
"V4": {
|
||||
"VT": "AC",
|
||||
"BA": "0x43C00000",
|
||||
"HA": "0x43C0FFFF",
|
||||
@@ -238,11 +220,6 @@
|
||||
"src": "V3",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V4",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
}
|
||||
]
|
||||
}
|
||||
|
||||
+25
-30
@@ -1,45 +1,40 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"0.969231",
|
||||
"Default View_TopLeft":"-420,3",
|
||||
"Default View_ScaleFactor":"0.971598",
|
||||
"Default View_TopLeft":"-432,3",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port ddr -pg 1 -lvl 3 -x 900 -y 140 -defaultsOSRD
|
||||
preplace port fixed_io -pg 1 -lvl 3 -x 900 -y 160 -defaultsOSRD
|
||||
preplace port spi -pg 1 -lvl 3 -x 900 -y 750 -defaultsOSRD
|
||||
preplace port gpio_hop -pg 1 -lvl 3 -x 900 -y 580 -defaultsOSRD
|
||||
preplace port port-id_spi_active -pg 1 -lvl 3 -x 900 -y 770 -defaultsOSRD
|
||||
preplace port port-id_ps_clk_200M -pg 1 -lvl 3 -x 900 -y 180 -defaultsOSRD
|
||||
preplace portBus gpio_i -pg 1 -lvl 3 -x 900 -y 80 -defaultsOSRD -right
|
||||
preplace portBus gpio_o -pg 1 -lvl 3 -x 900 -y 100 -defaultsOSRD
|
||||
preplace portBus gpio_t -pg 1 -lvl 3 -x 900 -y 120 -defaultsOSRD
|
||||
preplace port ddr -pg 1 -lvl 3 -x 870 -y 140 -defaultsOSRD
|
||||
preplace port fixed_io -pg 1 -lvl 3 -x 870 -y 160 -defaultsOSRD
|
||||
preplace port spi -pg 1 -lvl 3 -x 870 -y 750 -defaultsOSRD
|
||||
preplace port port-id_spi_active -pg 1 -lvl 3 -x 870 -y 770 -defaultsOSRD
|
||||
preplace port port-id_ps_clk_200M -pg 1 -lvl 3 -x 870 -y 240 -defaultsOSRD
|
||||
preplace portBus gpio_i -pg 1 -lvl 3 -x 870 -y 80 -defaultsOSRD -right
|
||||
preplace portBus gpio_o -pg 1 -lvl 3 -x 870 -y 100 -defaultsOSRD
|
||||
preplace portBus gpio_t -pg 1 -lvl 3 -x 870 -y 120 -defaultsOSRD
|
||||
preplace inst processing_system7 -pg 1 -lvl 1 -x 260 -y 190 -defaultsOSRD
|
||||
preplace inst axi_spi_engine -pg 1 -lvl 1 -x 260 -y 770 -defaultsOSRD
|
||||
preplace inst rst_ps7_50M -pg 1 -lvl 2 -x 690 -y 290 -defaultsOSRD
|
||||
preplace inst axi_interconnect -pg 1 -lvl 1 -x 260 -y 560 -defaultsOSRD
|
||||
preplace inst xlconcat_irq -pg 1 -lvl 2 -x 690 -y 440 -defaultsOSRD -orient R180
|
||||
preplace inst axi_gpio_hop -pg 1 -lvl 2 -x 690 -y 590 -defaultsOSRD
|
||||
preplace netloc axi_spi_engine_active_0 1 1 2 N 770 N
|
||||
preplace netloc processing_system7_FCLK_CLK0 1 0 2 20 380 510
|
||||
preplace netloc processing_system7_FCLK_RESET0_N 1 1 1 500 270n
|
||||
preplace netloc rst_ps7_50M_peripheral_aresetn 1 0 3 40 410 490J 190 880
|
||||
preplace netloc axi_spi_engine_irq 1 1 2 N 790 870
|
||||
preplace netloc xlconcat_irq_dout 1 0 2 50 390 480
|
||||
preplace netloc processing_system7_FCLK_CLK1 1 1 2 480J 180 NJ
|
||||
preplace inst rst_ps7_50M -pg 1 -lvl 2 -x 670 -y 340 -defaultsOSRD
|
||||
preplace inst axi_interconnect -pg 1 -lvl 1 -x 260 -y 580 -defaultsOSRD
|
||||
preplace inst xlconcat_irq -pg 1 -lvl 2 -x 670 -y 500 -defaultsOSRD -orient R180
|
||||
preplace netloc GPIO_I_0_1 1 1 2 N 80 N
|
||||
preplace netloc axi_spi_engine_active_0 1 1 2 N 770 N
|
||||
preplace netloc axi_spi_engine_irq 1 1 2 N 790 850
|
||||
preplace netloc processing_system7_FCLK_CLK0 1 0 2 20 380 490
|
||||
preplace netloc processing_system7_FCLK_CLK1 1 1 2 480J 240 NJ
|
||||
preplace netloc processing_system7_FCLK_RESET0_N 1 1 1 N 320
|
||||
preplace netloc processing_system7_GPIO_O 1 1 2 NJ 100 NJ
|
||||
preplace netloc processing_system7_GPIO_T 1 1 2 NJ 120 NJ
|
||||
preplace netloc axi_gpio_hop_ip2intc_irpt 1 2 1 880 430n
|
||||
preplace netloc processing_system7_M_AXI_GP0 1 0 2 30 400 470
|
||||
preplace netloc processing_system7_DDR 1 1 2 NJ 140 N
|
||||
preplace netloc axi_interconnect_0_M00_AXI 1 0 2 50 420 470
|
||||
preplace netloc rst_ps7_50M_peripheral_aresetn 1 0 3 40 440 NJ 440 850
|
||||
preplace netloc xlconcat_irq_dout 1 0 2 50 450 490
|
||||
preplace netloc axi_interconnect_0_M00_AXI 1 0 2 50 460 470
|
||||
preplace netloc axi_spi_engine_spi_0 1 1 2 N 750 N
|
||||
preplace netloc processing_system7_DDR 1 1 2 NJ 140 N
|
||||
preplace netloc processing_system7_FIXED_IO 1 1 2 NJ 160 N
|
||||
preplace netloc axi_interconnect_M01_AXI 1 1 1 N 570
|
||||
preplace netloc axi_gpio_hop_GPIO 1 2 1 N 580
|
||||
levelinfo -pg 1 0 260 690 900
|
||||
pagesize -pg 1 -db -bbox -sgen 0 0 1070 850
|
||||
preplace netloc processing_system7_M_AXI_GP0 1 0 2 30 390 470
|
||||
levelinfo -pg 1 0 260 670 870
|
||||
pagesize -pg 1 -db -bbox -sgen 0 0 1010 850
|
||||
"
|
||||
}
|
||||
{
|
||||
|
||||
+3
-2
@@ -123,7 +123,9 @@ assign cx9261a_mclk_delay_ctrl1 = gpio_o[13];
|
||||
assign cx9261a_mclk_delay_ctrl2 = gpio_o[14];
|
||||
assign hop_en = gpio_o[15];
|
||||
|
||||
assign gpio_i[31:16] = gpio_o[31:16];
|
||||
assign gpio_i[16] = gpio_hop_flag;
|
||||
|
||||
assign gpio_i[31:17] = gpio_o[31:17];
|
||||
|
||||
// spi interface
|
||||
wire spi_sclk ;
|
||||
@@ -174,7 +176,6 @@ system_bd_wrapper system_bd
|
||||
.gpio_i (gpio_i ), // input [31:0]gpio_i
|
||||
.gpio_o (gpio_o ), // output [31:0]gpio_o
|
||||
.gpio_t (gpio_t ), // output [31:0]gpio_t
|
||||
.gpio_hop_tri_i (gpio_hop_flag ), // input [0:0]gpio_hop_tri_i
|
||||
|
||||
// spi interface
|
||||
.spi_sclk (spi_sclk ), // output spi_sclk
|
||||
|
||||
@@ -100,9 +100,6 @@
|
||||
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci">
|
||||
<Proxy FileSetName="system_bd_auto_pc_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_axi_gpio_0_0/system_bd_axi_gpio_0_0.xci">
|
||||
<Proxy FileSetName="system_bd_axi_gpio_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci">
|
||||
<Proxy FileSetName="system_bd_axi_spi_engine_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
@@ -115,9 +112,6 @@
|
||||
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci">
|
||||
<Proxy FileSetName="system_bd_spi_engine_execution_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_xbar_0/system_bd_xbar_0.xci">
|
||||
<Proxy FileSetName="system_bd_xbar_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/cx9261a_if.v">
|
||||
<FileInfo>
|
||||
@@ -349,24 +343,6 @@
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_bd_auto_pc_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_auto_pc_0" RelGenDir="$PGENDIR/system_bd_auto_pc_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_bd_auto_pc_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_bd_xbar_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_xbar_0" RelGenDir="$PGENDIR/system_bd_xbar_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_bd_xbar_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_bd_axi_gpio_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_axi_gpio_0_0" RelGenDir="$PGENDIR/system_bd_axi_gpio_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_bd_axi_gpio_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="vio_hop_int" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_hop_int" RelGenDir="$PGENDIR/vio_hop_int">
|
||||
<File Path="$PSRCDIR/sources_1/ip/vio_hop_int/vio_hop_int.xci">
|
||||
<FileInfo>
|
||||
@@ -380,6 +356,12 @@
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_bd_auto_pc_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_auto_pc_0" RelGenDir="$PGENDIR/system_bd_auto_pc_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_bd_auto_pc_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
@@ -533,37 +515,17 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_auto_pc_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_auto_pc_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_auto_pc_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_auto_pc_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_auto_pc_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_auto_pc_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_xbar_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_xbar_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_xbar_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_xbar_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_axi_gpio_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_axi_gpio_0_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_axi_gpio_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_axi_gpio_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_gpio_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_gpio_0_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="vio_hop_int_synth_1" Type="Ft3:Synth" SrcSet="vio_hop_int" Part="xc7z045ffg900-2" ConstrsSet="vio_hop_int" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_hop_int_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_hop_int_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_hop_int_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_auto_pc_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_auto_pc_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_auto_pc_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_auto_pc_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_auto_pc_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_auto_pc_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
@@ -575,7 +537,7 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 18 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 16 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<Step Id="init_design"/>
|
||||
@@ -797,58 +759,24 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_auto_pc_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_auto_pc_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_auto_pc_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_auto_pc_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_auto_pc_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_xbar_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_xbar_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_xbar_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_axi_gpio_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_axi_gpio_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_axi_gpio_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_gpio_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_gpio_0_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="vio_hop_int_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="vio_hop_int" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_hop_int_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_hop_int_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_hop_int_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_auto_pc_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_auto_pc_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_auto_pc_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_auto_pc_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_auto_pc_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
|
||||
Reference in New Issue
Block a user