add var_cal module for xc7k410tffg900-2

refer to projects/ax7020/ax7020_spi_loopback/README.md for detailed information

.gitattributes

@@ -0,0 +1,3 @@
+*.xsa filter=lfs diff=lfs merge=lfs -text
+*.csv filter=lfs diff=lfs merge=lfs -text
+*.bit filter=lfs diff=lfs merge=lfs -text

.gitignore

@@ -20,8 +20,78 @@
 !/.gitignore
 !/README.md
 
+
 ################################################################################
-############################# Vivado & SDK Common ##############################
+############################### Vivado Specific ################################
+################################################################################
+
+# exclude
+.metadata
+*.cache/
+*.gen/
+*.hw/
+*.ip_user_files/
+*.runs/**/*
+*.sim/
+
+# include xpr
+!*.xpr
+
+# include hardware (Xilinx support archive) file
+!/projects/*/*/*.xsa
+!/projects/*/*/*.md
+
+# include board preset tcl (be careful about the path)
+!/projects/*/*.tcl
+
+# include design source
+!**/*.srcs/**/*
+
+# include design run results
+!**/*.runs/impl_*/*.bit
+!**/*.runs/impl_*/*.ltx
+
+
+################################################################################
+################################ Vitis Specific ################################
+################################################################################
+
+# include sdk directory and everything in it
+!/projects/*/*/vitis/
+!/projects/*/*/vitis/**
+/projects/*/*/vitis/**.log
+/projects/*/*/vitis/.analytics
+
+# exclude some obscure hidden SDK folders
+/projects/*/*/vitis/.metadata/
+/projects/*/*/vitis/.sdk/
+/projects/*/*/vitis/RemoteSystemsTempFiles/
+/projects/*/*/vitis/webtalk/
+
+# hw_platform: exclude the entire hw_platform folder, as everything can be
+# generated from the .hdf file. Make sure to include the bitstream in the .hdf
+# file when exporting from Vivado!
+/projects/*/*/vitis/*_hw_platform_*/
+
+# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
+# Makefile, ps lib files are regenerated automatically
+/projects/*/*/vitis/*_bsp/*
+!/projects/*/*/vitis/*_bsp/*.cproject
+!/projects/*/*/vitis/*_bsp/*.project
+!/projects/*/*/vitis/*_bsp/*.sdkproject
+!/projects/*/*/vitis/*_bsp/system.mss
+!/projects/*/*/vitis/*_bsp/Makefile
+
+# Application: ignored file patterns, exclude Debug & Release folders
+/projects/*/*/vitis/**/*.o
+/projects/*/*/vitis/**/*.d
+/projects/*/*/vitis/**/*.a
+/projects/*/*/vitis/*/Debug/
+/projects/*/*/vitis/*/Release/
+
+
+################################################################################
+############################ Vivado & Vitis Common #############################
 ################################################################################
 
 # folders (and all of their contents) that should always be ignored, anywhere
@@ -43,62 +113,3 @@ vivado_pid*
 # vivado workspace files
 xsim.dir/
 xvlog.pb
-
-################################################################################
-############################### Vivado Specific ################################
-################################################################################
-
-# exclude
-.metadata
-*.cache/
-*.gen/
-*.hw/
-*.ip_user_files/
-*.runs/**/*
-*.sim/
-
-# include xpr
-!*.xpr
-
-# include design source
-!**/*.srcs/**/*
-
-# include design run results
-!*.runs/impl_*/*.bit
-!*.runs/impl_*/*.ltx
-
-################################################################################
-################################# SDK Specific #################################
-################################################################################
-
-# include sdk directory and everything in it
-!*.sdk/
-!*.sdk/**
-*.sdk/**.log
-
-# exclude some obscure hidden SDK folders
-*.sdk/.metadata/
-*.sdk/.sdk/
-*.sdk/RemoteSystemsTempFiles/
-*.sdk/webtalk/
-
-# hw_platform: exclude the entire hw_platform folder, as everything can be
-# generated from the .hdf file. Make sure to include the bitstream in the .hdf
-# file when exporting from Vivado!
-*.sdk/*_hw_platform_*/
-
-# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
-# Makefile, ps lib files are regenerated automatically
-*.sdk/*_bsp/*
-!*.sdk/*_bsp/*.cproject
-!*.sdk/*_bsp/*.project
-!*.sdk/*_bsp/*.sdkproject
-!*.sdk/*_bsp/system.mss
-!*.sdk/*_bsp/Makefile
-
-# Application: ignored file patterns, exclude Debug & Release folders
-*.sdk/**/*.o
-*.sdk/**/*.d
-*.sdk/**/*.a
-*.sdk/*/Debug/
-*.sdk/*/Release/

README.md

@@ -0,0 +1,3 @@
+# Vivado Git Repository
+
+This repository includes all the design sources and third-party reference used in my Vivado project.

modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/ip/ad9361_fifo/ad9361_fifo.xci

@@ -0,0 +1,479 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "ad9361_fifo",
+    "component_reference": "xilinx.com:ip:fifo_generator:13.2",
+    "ip_revision": "9",
+    "gen_directory": "../../../../ad9361_mapping.gen/sources_1/ip/ad9361_fifo",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "ad9361_fifo", "resolve_type": "user", "usage": "all" } ],
+        "Fifo_Implementation": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "synchronization_stages": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
+        "asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Data_Width": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Input_Depth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Output_Data_Width": [ { "value": "12", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Depth": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Type": [ { "value": "Asynchronous_Reset", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Flags_Reset_Value": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
+        "Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Data_Count_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Write_Data_Count_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Read_Data_Count_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Full_Threshold_Assert_Value": [ { "value": "13", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Negate_Value": [ { "value": "12", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
+        "HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
+        "ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
+        "TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_rdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_axis": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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+        "C_WR_PNTR_WIDTH_WACH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_WDCH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_WRCH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_RACH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_RDCH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_AXIS": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_WACH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_WDCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_WRCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_RACH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_RDCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_AXIS": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintex7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7k410t" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "9" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../ad9361_mapping.gen/sources_1/ip/ad9361_fifo" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "rst": [ { "direction": "in", "driver_value": "0" } ],
+        "wr_clk": [ { "direction": "in", "driver_value": "0" } ],
+        "rd_clk": [ { "direction": "in", "driver_value": "0" } ],
+        "din": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
+        "wr_en": [ { "direction": "in", "driver_value": "0" } ],
+        "rd_en": [ { "direction": "in", "driver_value": "0" } ],
+        "dout": [ { "direction": "out", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
+        "full": [ { "direction": "out", "driver_value": "0x0" } ],
+        "empty": [ { "direction": "out", "driver_value": "0x1" } ]
+      },
+      "interfaces": {
+        "write_clk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "wr_clk" } ]
+          }
+        },
+        "read_clk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "rd_clk" } ]
+          }
+        },
+        "FIFO_WRITE": {
+          "vlnv": "xilinx.com:interface:fifo_write:1.0",
+          "abstraction_type": "xilinx.com:interface:fifo_write_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "FULL": [ { "physical_name": "full" } ],
+            "WR_DATA": [ { "physical_name": "din" } ],
+            "WR_EN": [ { "physical_name": "wr_en" } ]
+          }
+        },
+        "FIFO_READ": {
+          "vlnv": "xilinx.com:interface:fifo_read:1.0",
+          "abstraction_type": "xilinx.com:interface:fifo_read_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "EMPTY": [ { "physical_name": "empty" } ],
+            "RD_DATA": [ { "physical_name": "dout" } ],
+            "RD_EN": [ { "physical_name": "rd_en" } ]
+          }
+        }
+      }
+    }
+  }
+}

modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_dual.v

@@ -0,0 +1,196 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/07/01 17:37:27
+// Last Modified Date: 2023/03/06 11:26
+// Design Name:
+// Module Name: ad9361_rx_map_cmos_dual
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ad9361_rx_map_cmos_dual
+(
+    input           clk_2x_in       ,
+    input           clk_in_rst      ,
+
+    input           rx_data_clk     , // sync to output data
+    input           rx_data_clk_rst ,
+
+    input           rx_fifo_rst     ,  // async fifo reset
+
+    input           rx_frame        ,
+    input   [11:0]  rx_data         ,
+
+    output  [11:0]  rx_ch1_i        ,
+    output  [11:0]  rx_ch1_q        ,
+    output  [11:0]  rx_ch2_i        ,
+    output  [11:0]  rx_ch2_q
+);
+
+genvar          m;
+
+// rx data
+wire [11:0] rx_data_i, rx_data_q;
+
+generate
+for (m=0; m<12; m=m+1) begin : rx_data_iddr
+
+IDDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .INIT_Q1        (1'b0           ),
+    .INIT_Q2        (1'b0           ),
+    .SRTYPE         ("ASYNC"        )
+) i_rx_data_iddr (
+    .CE             (1'b1           ),
+    .R              (1'b0           ),
+    .S              (1'b0           ),
+    .C              (clk_2x_in      ),
+    .D              (rx_data[m]     ),
+    .Q1             (rx_data_q[m]   ),
+    .Q2             (rx_data_i[m]   )
+);
+
+end
+endgenerate
+
+// rx frame
+wire        rx_frame_i;
+wire        rx_frame_q;
+
+IDDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .INIT_Q1        (1'b0           ),
+    .INIT_Q2        (1'b0           ),
+    .SRTYPE         ("ASYNC"        )
+) i_rx_frame_iddr (
+    .CE             (1'b1           ),
+    .R              (1'b0           ),
+    .S              (1'b0           ),
+    .C              (clk_2x_in      ),
+    .D              (rx_frame       ),
+    .Q1             (rx_frame_q     ),
+    .Q2             (rx_frame_i     )
+);
+
+// divide rx_data to dual channel
+reg     [11:0]  rx1_data_i = 'b0;
+reg     [11:0]  rx1_data_q = 'b0;
+reg     [11:0]  rx2_data_i = 'b0;
+reg     [11:0]  rx2_data_q = 'b0;
+
+wire            rx_fifo_wr_en;
+reg             rx_fifo_rd_en = 'b0;
+
+wire            rx_fifo_empty_1;
+wire            rx_fifo_empty_2;
+wire            rx_fifo_empty_3;
+wire            rx_fifo_empty_4;
+
+assign rx_fifo_wr_en = rx_frame_i; // align data & write enable
+
+always @ (posedge clk_2x_in) begin
+    if (clk_in_rst) begin
+        rx1_data_i <= 'b0;
+        rx2_data_i <= 'b0;
+    end
+    else if(rx_frame_i) begin
+        rx1_data_i <= rx_data_i;
+    end
+    else begin
+        rx2_data_i <= rx_data_i;
+    end
+end
+
+always @ (posedge clk_2x_in) begin
+    if (clk_in_rst) begin
+        rx1_data_q <= 'b0;
+        rx2_data_q <= 'b0;
+    end
+    else if(rx_frame_q) begin
+        rx1_data_q <= rx_data_q;
+    end
+    else begin
+        rx2_data_q <= rx_data_q;
+    end
+end
+
+always @(posedge rx_data_clk) begin
+    if (rx_data_clk_rst) begin
+        rx_fifo_rd_en <= 'b0;
+    end
+    else begin
+        rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4};
+    end
+end
+
+ad9361_fifo u_rx_fifo_ch1_i
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_2x_in      ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx1_data_i     ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en  ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (rx_ch1_i       ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_1)  // output wire empty
+);
+
+ad9361_fifo u_rx_fifo_ch1_q
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_2x_in      ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx1_data_q     ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en  ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (rx_ch1_q       ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_2)  // output wire empty
+);
+
+ad9361_fifo u_rx_fifo_ch2_i
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_2x_in      ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx2_data_i     ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en  ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (rx_ch2_i       ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_3)  // output wire empty
+);
+
+ad9361_fifo u_rx_fifo_ch2_q
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_2x_in      ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx2_data_q     ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en  ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (rx_ch2_q       ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_4)  // output wire empty
+);
+
+endmodule

modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_single.v

@@ -0,0 +1,124 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/07/01 17:37:27
+// Last Modified Date: 2023/03/03 13:01
+// Design Name:
+// Module Name: ad9361_rx_map_cmos_single
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ad9361_rx_map_cmos_single
+(
+    input           clk_in          ,
+    input           clk_in_rst      ,
+
+    input           rx_data_clk     ,
+    input           rx_data_clk_rst ,
+
+    input           rx_fifo_rst     ,
+
+    input           rx_frame        ,
+    input   [11:0]  rx_data         ,
+
+    output  [11:0]  rx_data_i       ,
+    output  [11:0]  rx_data_q
+);
+
+genvar          m;
+
+// rx data
+wire [11:0] rx_raw_i, rx_raw_q;
+
+generate
+for (m=0; m<12; m=m+1) begin : rx_data_iddr
+
+IDDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .INIT_Q1        (1'b0           ),
+    .INIT_Q2        (1'b0           ),
+    .SRTYPE         ("ASYNC"        )
+) i_rx_data_iddr (
+    .CE             (1'b1           ),
+    .R              (1'b0           ),
+    .S              (1'b0           ),
+    .C              (clk_in         ),
+    .D              (rx_data[m]     ),
+    .Q1             (rx_raw_q[m]    ),
+    .Q2             (rx_raw_i[m]    )
+);
+
+end
+endgenerate
+
+
+// divide rx_data to dual channel
+reg             rx_fifo_wr_en = 1'b0;
+reg             rx_fifo_rd_en = 'b0;
+
+wire            rx_fifo_empty_1;
+wire            rx_fifo_empty_2;
+
+always @(posedge clk_in) begin
+    if (clk_in_rst) begin
+        rx_fifo_wr_en <= 1'b0;
+    end
+    else begin
+        rx_fifo_wr_en <= 1'b1;
+    end
+end
+
+always @(posedge rx_data_clk) begin
+    if (rx_data_clk_rst) begin
+        rx_fifo_rd_en <= 'b0;
+    end
+    else begin
+        rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2};
+    end
+end
+
+ad9361_fifo u_rx_fifo_i
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_in         ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx_raw_i       ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en  ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (rx_data_i      ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_1)  // output wire empty
+);
+
+ad9361_fifo u_rx_fifo_q
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_in         ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx_raw_q       ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en  ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (rx_data_q      ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_2)  // output wire empty
+);
+
+endmodule

modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_dual.v

@@ -0,0 +1,277 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/07/01 17:37:27
+// Last Modified Date: 2023/03/06 10:54
+// Design Name:
+// Module Name: ad9361_rx_mapping_dual
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ad9361_rx_map_lvds_dual
+(
+    input           clk_4x_in       , // sync to input data
+    input           clk_in_rst      ,
+
+    input           rx_data_clk     , // sync to output data
+    input           rx_data_clk_rst ,
+
+    input           rx_fifo_rst     , // async fifo reset
+
+    input           rx_frame_p      ,
+    input           rx_frame_n      ,
+    input   [ 5:0]  rx_data_p       , // data from ad9361 p1 port
+    input   [ 5:0]  rx_data_n       ,
+
+    output  [11:0]  rx_ch1_i        ,
+    output  [11:0]  rx_ch1_q        ,
+    output  [11:0]  rx_ch2_i        ,
+    output  [11:0]  rx_ch2_q
+);
+
+genvar          m;
+
+// rx data
+wire [5:0] rx_data;
+wire [5:0] rx_data_i, rx_data_q;
+
+generate
+for (m=0; m<6; m=m+1) begin : rx_data_iddr
+
+IBUFDS #(
+    .DIFF_TERM  ("TRUE"         )
+) u_ibufds_rx_data
+(
+    .I          (rx_data_p[m]   ),
+    .IB         (rx_data_n[m]   ),
+    .O          (rx_data[m]     )
+);
+
+IDDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .INIT_Q1        (1'b0           ),
+    .INIT_Q2        (1'b0           ),
+    .SRTYPE         ("ASYNC"        )
+) u_rx_data_iddr (
+    .CE             (1'b1           ), // clock enable
+    .R              (1'b0           ), // iddr reset
+    .S              (1'b0           ), // iddr set
+    .C              (clk_4x_in      ), // iddr clock
+    .D              (rx_data[m]     ), // ddr data
+    .Q1             (rx_data_q[m]   ), // sdr data at rising edge
+    .Q2             (rx_data_i[m]   )  // sdr data at falling edge
+);
+
+end
+endgenerate
+
+// rx frame
+wire            rx_frame;
+wire            rx_frame_i;
+wire            rx_frame_q;
+
+IBUFDS #(
+    .DIFF_TERM  ("TRUE"     )
+) u_ibufds_rx_frame
+(
+    .I          (rx_frame_p ),
+    .IB         (rx_frame_n ),
+    .O          (rx_frame   )
+);
+
+IDDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .INIT_Q1        (1'b0           ),
+    .INIT_Q2        (1'b0           ),
+    .SRTYPE         ("ASYNC"        )
+) u_rx_frame_iddr (
+    .CE             (1'b1           ), // clock enable
+    .R              (1'b0           ), // iddr reset
+    .S              (1'b0           ), // iddr set
+    .C              (clk_4x_in      ), // iddr clock
+    .D              (rx_frame       ), // ddr data
+    .Q1             (rx_frame_q     ), // sdr data at rising edge
+    .Q2             (rx_frame_i     )  // sdr data at falling edge
+);
+
+// unpack rx frame & data
+reg             rx_frame_i_d1   = 'b0;
+reg     [ 5:0]  rx_data_i_d1    = 'b0;
+reg     [ 5:0]  rx_data_q_d1    = 'b0;
+reg             rx_flag         = 'b0; // rx frame rising edge indicator
+reg     [ 1:0]  rx_cnt          = 'b0; // unpack stage counter
+
+always @(posedge clk_4x_in) begin
+    // wait for [rx_flag]
+    rx_frame_i_d1 <= rx_frame_i;
+     rx_data_i_d1 <=  rx_data_i;
+     rx_data_q_d1 <=  rx_data_q;
+end
+
+always @(posedge clk_4x_in) begin
+    if (clk_in_rst) begin
+        rx_flag <= 'b0;
+    end
+    else if (~rx_frame_i_d1 & rx_frame_i) begin
+        // assert when rising edge of rx frame is detected
+        rx_flag <= 'b1;
+    end
+    else begin
+        rx_flag <= rx_flag;
+    end
+end
+
+always @(posedge clk_4x_in) begin
+    if (clk_in_rst) begin
+        rx_cnt <= 'b0;
+    end
+    else begin
+        rx_cnt <= (rx_flag) ? rx_cnt + 1'b1 : rx_cnt;
+    end
+end
+
+reg     [11:0]  rx1_data_i = 'b0;
+reg     [11:0]  rx1_data_q = 'b0;
+reg     [11:0]  rx2_data_i = 'b0;
+reg     [11:0]  rx2_data_q = 'b0;
+
+always @(posedge clk_4x_in) begin
+    if (clk_in_rst) begin
+        rx1_data_i <= 'b0;
+        rx1_data_q <= 'b0;
+        rx2_data_i <= 'b0;
+        rx2_data_q <= 'b0;
+    end
+    else begin
+        case (rx_cnt)
+            3'd0: begin
+                // 1st clock cycle: upper 6-bit of rx ch1 inphase/quadrature data
+                rx1_data_i[11:6] <= rx_data_i_d1;
+                rx1_data_q[11:6] <= rx_data_q_d1;
+            end
+            3'd1: begin
+                // 2nd clock cycle: lower 6-bit of rx ch1 inphase/quadrature data
+                rx1_data_i[ 5:0] <= rx_data_i_d1;
+                rx1_data_q[ 5:0] <= rx_data_q_d1;
+            end
+            3'd2: begin
+                // 3rd clock cycle: upper 6-bit of rx ch2 inphase/quadrature data
+                rx2_data_i[11:6] <= rx_data_i_d1;
+                rx2_data_q[11:6] <= rx_data_q_d1;
+            end
+            3'd3: begin
+                // 4th clock cycle: lower 6-bit of rx ch2 inphase/quadrature data
+                rx2_data_i[ 5:0] <= rx_data_i_d1;
+                rx2_data_q[ 5:0] <= rx_data_q_d1;
+            end
+            default: begin
+                rx1_data_i <= 'b0;
+                rx1_data_q <= 'b0;
+                rx2_data_i <= 'b0;
+                rx2_data_q <= 'b0;
+            end
+        endcase
+    end
+end
+
+// write fifo when rx1/2_data_i/q are all prepared with 192MHz clock
+// read fifo at every clock cycle with 48MHz clock
+reg fifo_wr_en = 'b0;
+reg fifo_rd_en = 'b0;
+wire rx_fifo_empty_1;
+wire rx_fifo_empty_2;
+wire rx_fifo_empty_3;
+wire rx_fifo_empty_4;
+
+always @(posedge clk_4x_in) begin
+    if (clk_in_rst) begin
+        fifo_wr_en <= 'b0;
+    end
+    else if (rx_cnt == 2'd3) begin
+        fifo_wr_en <= 1'b1;
+    end
+    else begin
+        fifo_wr_en <= 'b0;
+    end
+end
+
+always @(posedge rx_data_clk) begin
+    if (rx_data_clk_rst) begin
+        fifo_rd_en <= 1'b0;
+    end
+    else begin
+        fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4};
+    end
+end
+
+ad9361_fifo u_rx_fifo_ch1_i
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_4x_in      ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx1_data_i     ), // input wire [11 : 0] din
+    .wr_en      (fifo_wr_en     ), // input wire wr_en
+    .rd_en      (fifo_rd_en     ), // input wire rd_en
+    .dout       (rx_ch1_i       ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_1)  // output wire empty
+);
+
+ad9361_fifo u_rx_fifo_ch1_q
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_4x_in      ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx1_data_q     ), // input wire [11 : 0] din
+    .wr_en      (fifo_wr_en     ), // input wire wr_en
+    .rd_en      (fifo_rd_en     ), // input wire rd_en
+    .dout       (rx_ch1_q       ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_2)  // output wire empty
+);
+
+ad9361_fifo u_rx_fifo_ch2_i
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_4x_in      ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx2_data_i     ), // input wire [11 : 0] din
+    .wr_en      (fifo_wr_en     ), // input wire wr_en
+    .rd_en      (fifo_rd_en     ), // input wire rd_en
+    .dout       (rx_ch2_i       ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_3)  // output wire empty
+);
+
+ad9361_fifo u_rx_fifo_ch2_q
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_4x_in      ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx2_data_q     ), // input wire [11 : 0] din
+    .wr_en      (fifo_wr_en     ), // input wire wr_en
+    .rd_en      (fifo_rd_en     ), // input wire rd_en
+    .dout       (rx_ch2_q       ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_4)  // output wire empty
+);
+
+endmodule

modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v

@@ -0,0 +1,183 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/07/01 16:39:19
+// Last Modified Date: 2023/03/06 11:45
+// Design Name:
+// Module Name: ad9361_tx_map_cmos_dual
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ad9361_tx_map_cmos_dual
+(
+    input           clk_2x_in       ,
+    input           clk_in_rst      ,
+
+    input           tx_data_clk     ,
+    input           tx_data_clk_rst ,
+
+    input   [11:0]  tx_ch1_i        ,
+    input   [11:0]  tx_ch1_q        ,
+    input   [11:0]  tx_ch2_i        ,
+    input   [11:0]  tx_ch2_q        ,
+
+    output          clk_out         ,
+    output          tx_frame        ,
+    output  [11:0]  tx_data
+);
+
+genvar m;
+
+// input data fifo
+reg rx_fifo_rd_en = 'b0;
+wire [11:0] tx_fifo_ch1_i;
+wire [11:0] tx_fifo_ch1_q;
+wire [11:0] tx_fifo_ch2_i;
+wire [11:0] tx_fifo_ch2_q;
+
+always @(posedge clk_2x_in) begin
+    if (clk_in_rst) begin
+        rx_fifo_rd_en <= 'b0;
+    end
+    else begin
+        rx_fifo_rd_en <= ~rx_fifo_rd_en;
+    end
+end
+
+ad9361_fifo u_tx_fifo_ch1_i
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_2x_in      ), // input wire rd_clk
+    .din        (tx_ch1_i       ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_ch1_i  ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+ad9361_fifo u_tx_fifo_ch1_q
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_2x_in      ), // input wire rd_clk
+    .din        (tx_ch1_q       ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_ch1_q  ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+ad9361_fifo u_tx_fifo_ch2_i
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_2x_in      ), // input wire rd_clk
+    .din        (tx_ch2_i       ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_ch2_i  ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+ad9361_fifo u_tx_fifo_ch2_q
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_2x_in      ), // input wire rd_clk
+    .din        (tx_ch2_q       ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_ch2_q  ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+// frame and data control
+reg tx_frame_i = 'b0;
+reg tx_frame_q = 'b0;
+reg [11:0] tx_data_i = 'b0;
+reg [11:0] tx_data_q = 'b0;
+
+always @(posedge clk_2x_in) begin
+    if (clk_in_rst) begin
+        tx_frame_i <= 'b0;
+        tx_frame_q <= 'b0;
+        tx_data_i <= 'b0;
+        tx_data_q <= 'b0;
+    end
+    else if (rx_fifo_rd_en == 1'b0) begin
+        tx_frame_i <= 1'b1;
+        tx_frame_q <= 1'b1;
+        tx_data_i <= tx_fifo_ch1_i;
+        tx_data_q <= tx_fifo_ch1_q;
+    end
+    else begin
+        tx_frame_i <= 1'b0;
+        tx_frame_q <= 1'b0;
+        tx_data_i <= tx_fifo_ch2_i;
+        tx_data_q <= tx_fifo_ch2_q;
+    end
+end
+
+// output clock to port
+assign clk_out = clk_2x_in;
+
+// output tx frame to port
+ODDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .INIT           (1'b0           ),
+    .SRTYPE         ("ASYNC"        )
+) u_tx_frame_oddr (
+    .CE             (1'b1           ),
+    .R              (1'b0           ),
+    .S              (1'b0           ),
+    .C              (clk_2x_in      ),
+    .D1             (tx_frame_i     ),
+    .D2             (tx_frame_q     ),
+    .Q              (tx_frame       )
+);
+
+// output tx data to port
+generate
+for (m=0; m<12; m=m+1) begin: tx_data_oddr
+
+ODDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"   ),
+    .INIT           (1'b0          ),
+    .SRTYPE         ("ASYNC"       )
+) u_tx_data_oddr  (
+    .CE             (1'b1          ),
+    .R              (1'b0          ),
+    .S              (1'b0          ),
+    .C              (clk_2x_in     ),
+    .D1             (tx_data_i[m]  ),
+    .D2             (tx_data_q[m]  ),
+    .Q              (tx_data[m]    )
+);
+
+end
+endgenerate
+
+endmodule

modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_single.v

@@ -0,0 +1,119 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/07/01 16:39:19
+// Design Name:
+// Module Name: ad9361_tx_mapping_single
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ad9361_tx_map_cmos_single
+(
+    input           clk_in          ,
+    input           clk_in_rst      ,
+
+    input           tx_data_clk     ,
+    input           tx_data_clk_rst ,
+
+    input   [11:0]  tx_data_i       ,
+    input   [11:0]  tx_data_q       ,
+
+    output          clk_out         ,
+    output          tx_frame        ,
+    output  [11:0]  tx_data
+);
+
+genvar m;
+
+// inout data fifo
+wire [11:0] tx_fifo_i;
+wire [11:0] tx_fifo_q;
+
+ad9361_fifo u_tx_fifo_i
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_in         ), // input wire rd_clk
+    .din        (tx_data_i      ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (1'b1           ), // input wire rd_en
+    .dout       (tx_fifo_i      ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+ad9361_fifo u_tx_fifo_q
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_in         ), // input wire rd_clk
+    .din        (tx_data_q      ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (1'b1           ), // input wire rd_en
+    .dout       (tx_fifo_q      ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+// frame and data control
+assign tx_frame_i = 1'b1;
+assign tx_frame_q = 1'b0;
+
+// output clock to port
+assign clk_out = clk_in;
+
+// output tx frame to port
+ODDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .INIT           (1'b0           ),
+    .SRTYPE         ("ASYNC"        )
+) u_tx_frame_oddr (
+    .CE             (1'b1           ),
+    .R              (1'b0           ),
+    .S              (1'b0           ),
+    .C              (clk_in         ),
+    .D1             (tx_frame_i     ),
+    .D2             (tx_frame_q     ),
+    .Q              (tx_frame       )
+);
+
+// output tx data to port
+generate
+for (m=0; m<12; m=m+1) begin: tx_data_oddr
+
+ODDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"   ),
+    .INIT           (1'b0          ),
+    .SRTYPE         ("ASYNC"       )
+) u_tx_data_oddr  (
+    .CE             (1'b1          ),
+    .R              (1'b0          ),
+    .S              (1'b0          ),
+    .C              (clk_in        ),
+    .D1             (tx_fifo_i[m]  ),
+    .D2             (tx_fifo_q[m]  ),
+    .Q              (tx_data[m]    )
+);
+
+end
+endgenerate
+
+endmodule

modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_dual.v

@@ -0,0 +1,246 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2023/03/05 23:21:27
+// Last Modified Date: 2023/03/06 11:01
+// Design Name:
+// Module Name: ad9361_tx_map_lvds_dual
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ad9361_tx_map_lvds_dual
+(
+    input           clk_4x_in       ,
+    input           clk_in_rst      ,
+
+    input           tx_data_clk     ,
+    input           tx_data_clk_rst ,
+
+    input   [11:0]  tx_ch1_i        ,
+    input   [11:0]  tx_ch1_q        ,
+    input   [11:0]  tx_ch2_i        ,
+    input   [11:0]  tx_ch2_q        ,
+
+    output          clk_out_p       ,
+    output          clk_out_n       ,
+    output          tx_frame_p      ,
+    output          tx_frame_n      ,
+    output  [ 5:0]  tx_data_p       ,
+    output  [ 5:0]  tx_data_n
+);
+
+genvar m;
+
+// input data fifo
+reg [1:0] tx_control_cnt = 'b0;
+reg rx_fifo_rd_en = 'b0;
+wire [11:0] tx_fifo_ch1_i;
+wire [11:0] tx_fifo_ch1_q;
+wire [11:0] tx_fifo_ch2_i;
+wire [11:0] tx_fifo_ch2_q;
+
+always @(posedge clk_4x_in) begin
+    if (clk_in_rst) begin
+        tx_control_cnt <= 'b0;
+    end
+    else begin
+        tx_control_cnt <= tx_control_cnt + 1'b1;
+    end
+end
+
+always @(posedge clk_4x_in) begin
+    if (clk_in_rst) begin
+        rx_fifo_rd_en <= 'b0;
+    end
+    else if (tx_control_cnt == 2'd2) begin
+        rx_fifo_rd_en <= 1'b1;
+    end
+    else begin
+        rx_fifo_rd_en <= 'b0;
+    end
+end
+
+ad9361_fifo u_tx_fifo_ch1_i
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_4x_in      ), // input wire rd_clk
+    .din        (tx_ch1_i       ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_ch1_i  ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+ad9361_fifo u_tx_fifo_ch1_q
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_4x_in      ), // input wire rd_clk
+    .din        (tx_ch1_q       ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_ch1_q  ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+ad9361_fifo u_tx_fifo_ch2_i
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_4x_in      ), // input wire rd_clk
+    .din        (tx_ch2_i       ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_ch2_i  ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+ad9361_fifo u_tx_fifo_ch2_q
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_4x_in      ), // input wire rd_clk
+    .din        (tx_ch2_q       ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_ch2_q  ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+
+// frame and data control
+reg tx_frame_r = 'b0; // rising edge data
+reg tx_frame_f = 'b0; // falling edge data
+reg [5:0] tx_data_r = 'b0;
+reg [5:0] tx_data_f = 'b0;
+
+always @(posedge clk_4x_in) begin
+    if (clk_in_rst) begin
+        tx_frame_r <= 'b0;
+        tx_frame_f <= 'b0;
+        tx_data_r <= 'b0;
+        tx_data_f <= 'b0;
+    end
+    else begin
+        case (tx_control_cnt)
+            2'd0: begin
+                tx_frame_r <= 1'b1;
+                tx_frame_f <= 1'b1;
+                tx_data_r <= tx_fifo_ch1_i[11: 6];
+                tx_data_f <= tx_fifo_ch1_q[11: 6];
+            end
+            2'd1: begin
+                tx_frame_r <= 1'b1;
+                tx_frame_f <= 1'b1;
+                tx_data_r <= tx_fifo_ch1_i[5:0];
+                tx_data_f <= tx_fifo_ch1_q[5:0];
+            end
+            2'd2: begin
+                tx_frame_r <= 1'b0;
+                tx_frame_f <= 1'b0;
+                tx_data_r <= tx_fifo_ch2_i[11:6];
+                tx_data_f <= tx_fifo_ch2_q[11:6];
+            end
+            2'd3: begin
+                tx_frame_r <= 1'b0;
+                tx_frame_f <= 1'b0;
+                tx_data_r <= tx_fifo_ch2_i[5:0];
+                tx_data_f <= tx_fifo_ch2_q[5:0];
+            end
+            default: begin
+                tx_frame_r <= 'b0;
+                tx_frame_f <= 'b0;
+                tx_data_r <= 'b0;
+                tx_data_f <= 'b0;
+            end
+        endcase
+    end
+end
+
+// output clock to port
+wire clk_out;
+assign clk_out = clk_4x_in;
+
+OBUFDS u_obufds_clk_out
+(
+    .I  (clk_out    ),
+    .O  (clk_out_p  ),
+    .OB (clk_out_n  )
+);
+
+// output tx frame to port
+ODDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .INIT           (1'b0           ),
+    .SRTYPE         ("ASYNC"        )
+) u_tx_frame_oddr (
+    .CE             (1'b1           ),
+    .R              (1'b0           ),
+    .S              (1'b0           ),
+    .C              (clk_4x_in      ),
+    .D1             (tx_frame_r     ),
+    .D2             (tx_frame_f     ),
+    .Q              (tx_frame       )
+);
+
+OBUFDS u_obufds_tx_frame
+(
+    .I  (tx_frame   ),
+    .O  (tx_frame_p ),
+    .OB (tx_frame_n )
+);
+
+// output tx data to port
+wire [5:0] tx_data;
+
+generate
+for (m=0; m<6; m=m+1) begin: tx_data_oddr
+
+ODDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"   ),
+    .INIT           (1'b0          ),
+    .SRTYPE         ("ASYNC"       )
+) u_tx_data_oddr  (
+    .CE             (1'b1          ),
+    .R              (1'b0          ),
+    .S              (1'b0          ),
+    .C              (clk_4x_in     ),
+    .D1             (tx_data_r[m]  ),
+    .D2             (tx_data_f[m]  ),
+    .Q              (tx_data[m]    )
+);
+
+OBUFDS u_obufds_tx_data
+(
+    .I  (tx_data[m]     ),
+    .O  (tx_data_p[m]   ),
+    .OB (tx_data_n[m]   )
+);
+
+end
+endgenerate
+
+endmodule

modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.xpr

@@ -0,0 +1,303 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!--                                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
+<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+
+<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/Workspace/vivado/vivado_pub/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="6455237789e34802b5930fcc12496fe7"/>
+    <Option Name="Part" Val="xc7k410tffg900-2"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
+    <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
+    <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
+    <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
+    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
+    <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="SimCompileState" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="1"/>
+    <Option Name="WTModelSimExportSim" Val="1"/>
+    <Option Name="WTQuestaExportSim" Val="1"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="1"/>
+    <Option Name="WTRivieraExportSim" Val="1"/>
+    <Option Name="WTActivehdlExportSim" Val="1"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+  </Configuration>
+  <FileSets Version="1" Minor="32">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_cmos_dual.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_lvds_dual.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_cmos_single.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_cmos_single.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_lvds_dual.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_cmos_dual.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="ad9361_rx_map_cmos_dual"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="ad9361_rx_map_cmos_dual"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="ad9361_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ad9361_fifo" RelGenDir="$PGENDIR/ad9361_fifo">
+      <File Path="$PSRCDIR/sources_1/ip/ad9361_fifo/ad9361_fifo.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="ad9361_fifo"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="21">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="ad9361_fifo_synth_1" Type="Ft3:Synth" SrcSet="ad9361_fifo" Part="xc7k410tffg900-2" ConstrsSet="ad9361_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ad9361_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ad9361_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ad9361_fifo_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="ad9361_fifo_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ad9361_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ad9361_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ad9361_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ad9361_fifo_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board/>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>

modules/xc7k410tffg900-2/multi_ch_cal/multi_ch_cal.srcs/sim_1/new/multi_ch_cal_1bit.m

@@ -0,0 +1,118 @@
+%% File Header/文件说明
+%
+% 调零算法对幅相一致性的要求较高，且 AD9361 多片同步的精度随机性较大，因此需要对
+% AD9361 多片同步误差进行精细校准。采用收发扩频码的方式在校准过程中对两片 AD9361
+% 的两个接收通道进行幅相测量，在接收端使用加法器进行非相干相关峰累积，累积 N 个
+% 符号后出峰，根据相关峰的高度差和相位差，在接收端对信号的幅度和相位进行补偿。
+%
+clc; clear; close all;
+%% initial system parameters/初始系统参数
+rng(0);
+Eb_N0 = 30; % energy per bit to noise power spectral density ratio
+interp = 8; % interpolation factor
+SNR = 10*log10(2/interp) + Eb_N0; % signal-to-noise power ration
+channelNum = 2;
+deltaAmp = 1-(2*rand-1)*0.05;     % random amplitude error, range: [0.95,1.05]
+deltaAngRad = (2*rand-1)*pi;      % random phase error, range: [-pi,pi]
+deltaAngDeg = deltaAngRad/pi*180;
+angleInit = 20/pi*180;
+
+% standard pn sequence
+pnSequence = comm.PNSequence('Polynomial','x^7+x^6+1', ...
+  'InitialConditions',[zeros(1,6),1],'SamplesPerFrame',2^7-1);
+PRBS7 = pnSequence();
+PRBS7_polar = 1-2*[PRBS7;0];
+
+chipLen = length(PRBS7_polar);      % pn chip length
+accumSymbolNum = 16;
+totalSymbolNum = accumSymbolNum+1;
+
+randomChipIndex_ch1 = randi(chipLen*interp*2-1)-chipLen*interp;   % random rx chip index
+randomChipIndex_ch2 = randomChipIndex_ch1 + (randi(2*interp-1)-interp);   % random rx chip index
+% randomChipIndex_ch1 = -2;   % random rx chip index
+% randomChipIndex_ch2 = 5;   % random rx chip index
+
+%%
+% 发送信号：方波成型
+seqTx = kron(repmat(PRBS7_polar,totalSymbolNum,1),ones(interp,1));
+
+% 接收信号：随机初始相位，加噪，随机幅度误差，随机相位误差
+seqRx = awgn(seqTx,SNR,'measured').*[1,deltaAmp].*[exp(1i*angleInit),...
+  exp(1i*(angleInit+deltaAngRad))];
+seqRx(:,1) = circshift(seqRx(:,1),randomChipIndex_ch1);
+seqRx(:,2) = circshift(seqRx(:,2),randomChipIndex_ch2);
+
+% 降采样，与 Verilog 实现一样在码片中心采样
+seqRxDown = zeros(chipLen*accumSymbolNum,channelNum,interp);
+
+for i = 0:interp-1
+  % 补偿 Verilog 模块的读数延迟
+  seqRxDown(:,:,i+1) = downsample(seqRx((1:accumSymbolNum*chipLen*interp)+2,:),interp,i);
+end
+
+% 取符号位
+seqRxMsbReal = zeros(size(seqRxDown));
+seqRxMsbImag = zeros(size(seqRxDown));
+seqRxMsbReal(real(seqRxDown)>0) = 1;
+seqRxMsbReal(real(seqRxDown)<0) = -1;
+seqRxMsbImag(imag(seqRxDown)>0) = 1;
+seqRxMsbImag(imag(seqRxDown)<0) = -1;
+
+% 符号位累积
+seqRxMsbRealAccum = zeros(chipLen,channelNum,interp);
+seqRxMsbImagAccum = zeros(chipLen,channelNum,interp);
+
+for i = 0:chipLen-1
+  % PN 码圆周移位，遍历所有 PN 码相位
+  PRBS7_cshift = circshift(repmat(PRBS7_polar,accumSymbolNum,1),-i); % 负号为了和 Verilog 程序对应
+  % 累积，若当前比特与 PN 码相同，结果 +1；否则结果 -1
+  seqRxMsbRealAccum(i+1,:,:) = sum(PRBS7_cshift==seqRxMsbReal)-...
+    sum(PRBS7_cshift~=seqRxMsbReal);
+  seqRxMsbImagAccum(i+1,:,:) = sum(PRBS7_cshift==seqRxMsbImag)-...
+    sum(PRBS7_cshift~=seqRxMsbImag);
+end
+
+seqRxMsbAccum = seqRxMsbRealAccum+1i*seqRxMsbImagAccum;
+
+% 通过相关峰位置判断目标信号位置
+maxPeakIndex = zeros(2,interp);
+
+for i = 1:2
+  for j = 1:interp
+    maxPeakIndex(i,j) = find(abs(seqRxMsbAccum(:,i,j))==max(abs(seqRxMsbAccum(:,i,j))),1); % PN 码相位
+  end
+end
+
+maxPeakIndexDiff = zeros(channelNum,1); % 相位差
+
+for i = 1:channelNum
+  for j = 1:interp
+    if (maxPeakIndex(i,j)==maxPeakIndex(i,1))
+      maxPeakIndexDiff(i) = j;
+    end
+  end
+end
+
+% 以下条件仅对双通道有效
+if (maxPeakIndex(1,1) == maxPeakIndex(2,1))
+  relativeDelay = maxPeakIndexDiff(2) - maxPeakIndexDiff(1);
+  desiredPointIndex = [1,1]+[0,chipLen];
+elseif (mod(maxPeakIndex(1,1)-1,chipLen) == mod(maxPeakIndex(2,1),chipLen))
+  relativeDelay = maxPeakIndexDiff(2) - maxPeakIndexDiff(1) + interp;
+  desiredPointIndex = [1,2]+[0,chipLen];
+elseif (mod(maxPeakIndex(1,1)+1,chipLen) == mod(maxPeakIndex(2,1),chipLen))
+  relativeDelay = maxPeakIndexDiff(2) - maxPeakIndexDiff(1) - interp;
+  desiredPointIndex = [2,1]+[0,chipLen];
+end
+
+% 输入信号累加
+seqRxDownAccum = squeeze(sum(reshape(seqRxDown(:,:,1),128,[],2),2));
+% 取目标位置信号
+desiredPoint = seqRxDownAccum(desiredPointIndex);
+
+ampEst = abs(desiredPoint)./abs(desiredPoint(1));
+angleEst = (angle(desiredPoint) - angle(desiredPoint(1)))/pi*180;
+
+seqRxExport = round([real(seqRx(:,1)),imag(seqRx(:,1)),real(seqRx(:,2)),...
+  imag(seqRx(:,2))]/max(abs(seqRx),[],'all')*(2^11-1));
+writematrix(seqRxExport,'./fine_cal_data.txt');

modules/xc7k410tffg900-2/multi_ch_cal/multi_ch_cal.srcs/sim_1/new/tb_multi_ch_cal.v

@@ -0,0 +1,168 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2023/02/17 16:51:52
+// Design Name:
+// Module Name: tb
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description: testbench for [multi_ch_cal]
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_multi_ch_cal;
+
+localparam DATA_FILE_PATH = "../fine_cal_data.txt";
+localparam DATA_LEN = 16384;
+localparam DATA_WIDTH = 12;
+localparam ACCUM_SYMBOL_NUM = 4;
+
+// localparam DATA_FILE_PATH = "D:\\iladata_pn_trx_4.csv";
+// localparam DATA_LEN = 131072;
+// localparam DATA_WIDTH = 12;
+
+reg  clk = 'b0;
+reg  rst = 1'b1;
+
+reg  ad9361_1_cal_start = 'b0;
+wire ad9361_1_cal_done ;
+reg  ad9361_2_cal_start = 'b0;
+wire ad9361_2_cal_done ;
+wire ad9361_cal_result ;
+wire ad9361_cal_valid;
+reg  ad9361_recal       = 'b0;
+
+// phase difference of 180 degree
+reg signed [11:0] rx_ch1_i = 'b0;
+reg signed [11:0] rx_ch1_q = 'b0;
+reg signed [11:0] rx_ch2_i = 'b0;
+reg signed [11:0] rx_ch2_q = 'b0;
+reg signed [11:0] rx_ch3_q = 'b0;
+reg signed [11:0] rx_ch3_i = 'b0;
+reg signed [11:0] rx_ch4_i = 'b0;
+reg signed [11:0] rx_ch4_q = 'b0;
+
+wire [11:0] rx_cal_ch1_i;
+wire [11:0] rx_cal_ch2_i;
+wire [11:0] rx_cal_ch3_i;
+wire [11:0] rx_cal_ch4_i;
+wire [11:0] rx_cal_ch1_q;
+wire [11:0] rx_cal_ch2_q;
+wire [11:0] rx_cal_ch3_q;
+wire [11:0] rx_cal_ch4_q;
+
+integer i = 0;
+integer r_file;
+
+multi_ch_cal #(
+    .ACCUM_SYMBOL_NUM   (ACCUM_SYMBOL_NUM   )
+) u_multi_ch_cal
+(
+    // clock & reset
+    .clk                (clk                ), // input           clk
+    .rst                (rst                ), // input           rst
+    // control interface
+    .ad9361_1_cal_start (ad9361_1_cal_start ), // input           ad9361_1_cal_start
+    .ad9361_1_cal_done  (ad9361_1_cal_done  ), // output          ad9361_1_cal_done
+    .ad9361_2_cal_start (ad9361_2_cal_start ), // input           ad9361_2_cal_start
+    .ad9361_2_cal_done  (ad9361_2_cal_done  ), // output          ad9361_2_cal_done
+    .ad9361_cal_result  (ad9361_cal_result  ), // output          ad9361_cal_result
+    .ad9361_cal_valid   (ad9361_cal_valid   ), // output          ad9361_cal_valid
+    .ad9361_recal       (ad9361_recal       ), // input           ad9361_recal
+    // input data interface
+    .rx_ch1_i           (rx_ch1_i           ), // input   [11:0]  rx_ch1_i
+    .rx_ch2_i           (rx_ch2_i           ), // input   [11:0]  rx_ch2_i
+    .rx_ch3_i           (rx_ch3_i           ), // input   [11:0]  rx_ch3_i
+    .rx_ch4_i           (rx_ch4_i           ), // input   [11:0]  rx_ch4_i
+    .rx_ch1_q           (rx_ch1_q           ), // input   [11:0]  rx_ch1_q
+    .rx_ch2_q           (rx_ch2_q           ), // input   [11:0]  rx_ch2_q
+    .rx_ch3_q           (rx_ch3_q           ), // input   [11:0]  rx_ch3_q
+    .rx_ch4_q           (rx_ch4_q           ), // input   [11:0]  rx_ch4_q
+    // output data interface
+    .rx_cal_ch1_i       (rx_cal_ch1_i       ), // output  [11:0]  rx_cal_ch1_i
+    .rx_cal_ch2_i       (rx_cal_ch2_i       ), // output  [11:0]  rx_cal_ch2_i
+    .rx_cal_ch3_i       (rx_cal_ch3_i       ), // output  [11:0]  rx_cal_ch3_i
+    .rx_cal_ch4_i       (rx_cal_ch4_i       ), // output  [11:0]  rx_cal_ch4_i
+    .rx_cal_ch1_q       (rx_cal_ch1_q       ), // output  [11:0]  rx_cal_ch1_q
+    .rx_cal_ch2_q       (rx_cal_ch2_q       ), // output  [11:0]  rx_cal_ch2_q
+    .rx_cal_ch3_q       (rx_cal_ch3_q       ), // output  [11:0]  rx_cal_ch3_q
+    .rx_cal_ch4_q       (rx_cal_ch4_q       )  // output  [11:0]  rx_cal_ch4_q
+);
+
+initial begin
+    r_file = $fopen(DATA_FILE_PATH,"r");
+    #102
+    rst = 1'b0;
+    #100
+    ad9361_1_cal_start = 1'b1;
+end
+
+always @(posedge clk) begin
+    if (ad9361_1_cal_start) begin
+        if (i == DATA_LEN-1) begin
+            $fscanf(r_file,"%d,%d,%d,%d",
+                rx_ch2_i,
+                rx_ch2_q,
+                rx_ch4_i,
+                rx_ch4_q);
+            $fclose(r_file);
+            r_file = $fopen(DATA_FILE_PATH,"r");
+            i <= 0;
+        end
+        else begin
+            $fscanf(r_file,"%d,%d,%d,%d",
+                rx_ch2_i,
+                rx_ch2_q,
+                rx_ch4_i,
+                rx_ch4_q);
+            i <= i + 1;
+        end
+    end
+end
+
+always begin
+    #10 clk = ~clk;
+end
+
+// initial begin
+//     #10000
+//     ad9361_recal = 1'b1;
+//     #20
+//     ad9361_recal = 1'b0;
+// end
+
+always @(posedge clk) begin
+    if (ad9361_1_cal_done) begin
+        ad9361_2_cal_start <= 1'b1;
+    end
+    else begin
+        ad9361_2_cal_start <= 1'b0;
+    end
+end
+
+always @(posedge clk) begin
+    if (ad9361_2_cal_done) begin
+        #2000
+        ad9361_recal <= 1'b1;
+    end
+    else begin
+        ad9361_recal <= 1'b0;
+    end
+end
+
+endmodule

modules/xc7k410tffg900-2/multi_ch_cal/multi_ch_cal.srcs/sources_1/ip/atan2_16b/atan2_16b.xci

@@ -0,0 +1,188 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "atan2_16b",
+    "component_reference": "xilinx.com:ip:cordic:6.0",
+    "ip_revision": "20",
+    "gen_directory": "../../../../multi_ch_cal.gen/sources_1/ip/atan2_16b",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "atan2_16b", "resolve_type": "user", "usage": "all" } ],
+        "Functional_Selection": [ { "value": "Arc_Tan", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Architectural_Configuration": [ { "value": "Parallel", "resolve_type": "user", "usage": "all" } ],
+        "Pipelining_Mode": [ { "value": "Maximum", "resolve_type": "user", "usage": "all" } ],
+        "Data_Format": [ { "value": "SignedFraction", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Format": [ { "value": "Scaled_Radians", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Input_Width": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Output_Width": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Round_Mode": [ { "value": "Truncate", "resolve_type": "user", "usage": "all" } ],
+        "Iterations": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Precision": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Coarse_Rotation": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Compensation_Scaling": [ { "value": "No_Scale_Compensation", "resolve_type": "user", "usage": "all" } ],
+        "cartesian_has_tuser": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "cartesian_tuser_width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "cartesian_has_tlast": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "phase_has_tuser": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "phase_tuser_width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "phase_has_tlast": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "flow_control": [ { "value": "NonBlocking", "resolve_type": "user", "usage": "all" } ],
+        "optimize_goal": [ { "value": "Performance", "resolve_type": "user", "usage": "all" } ],
+        "out_tready": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "out_tlast_behv": [ { "value": "Null", "resolve_type": "user", "usage": "all" } ],
+        "ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ARESETN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_ARCHITECTURE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CORDIC_FUNCTION": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COARSE_ROTATE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_FORMAT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_XDEVICEFAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ACLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_CARTESIAN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_PHASE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ARESETN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INPUT_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ITERATIONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OUTPUT_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PHASE_FORMAT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PIPELINE_MODE": [ { "value": "-2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRECISION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ROUND_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SCALE_COMP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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modules/xc7k410tffg900-2/multi_ch_cal/multi_ch_cal.srcs/sources_1/ip/rotate_16b/rotate_16b.xci

@@ -0,0 +1,214 @@
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+          }
+        },
+        "aclk_intf": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "M_AXIS_DOUT:S_AXIS_PHASE:S_AXIS_CARTESIAN", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "1000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "aresetn_intf": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclken_intf": {
+          "vlnv": "xilinx.com:signal:clockenable:1.0",
+          "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
+          }
+        },
+        "S_AXIS_PHASE": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_phase_tdata" } ],
+            "TVALID": [ { "physical_name": "s_axis_phase_tvalid" } ]
+          }
+        },
+        "M_AXIS_DOUT": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_dout_tdata" } ],
+            "TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ]
+          }
+        }
+      }
+    }
+  }
+}

modules/xc7k410tffg900-2/multi_ch_cal/multi_ch_cal.srcs/sources_1/new/multi_ch_cal.v

@@ -0,0 +1,893 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2023/02/15 17:47:17
+// Last Modified Date: 2023/03/04 12:30:00
+// Design Name:
+// Module Name: multi_ch_cal
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description: 本程序用于
+//
+// Dependencies:
+//
+// Revision:
+//   Revision 0.01 - File Created
+//   20230304-1230
+//     1. 修改相位差计算结果，原计算结果可能超出 [-pi,pi] 范围，现在会进行修正；
+//     2. 修改 CORDIC IP 核相位输入输出为 Scaled Radians 模式；
+//     3. 修改 [cnt_decim] 在校准完成状态下的值为 0；
+//     4. 通道间相对延迟计算不正确，修改 [peak_index_num] 为无符号数即可；
+//     5. 修改 [atan2_data_xxxx] 在累积结果长度小于 CORDIC AXIS 位宽时的符号位扩展方法。
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module multi_ch_cal
+#(
+    parameter ADC_DATA_WIDTH = 12,
+    parameter PRBS = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
+    parameter PRBS_LEN = 128, // length of pseudorandom bit sequence
+    parameter INTERP_FACTOR = 8, // interpolation factor, max inter-channel delay ranges in [-INTERP_FACTOR+1,INTERP_FACTOR-1]
+    parameter ACCUM_SYMBOL_NUM = 16,
+    parameter CORDIC_WIDTH = 16, // input and output data width of cordic-ip-based atan2 and rotation operation
+    parameter CHANNEL_NUM = 2 // the channel number of current algorithm is LIMITED to 2
+)
+(
+    // clock & reset
+    input           clk                         ,
+    input           rst                         ,
+    // control interface
+    input           ad9361_1_cal_start          ,
+    output          ad9361_1_cal_done           ,
+    input           ad9361_2_cal_start          ,
+    output          ad9361_2_cal_done           ,
+    output          ad9361_cal_result           ,
+    output          ad9361_cal_valid            ,
+    input           ad9361_recal                ,
+    // input data interface
+    input [ADC_DATA_WIDTH-1 : 0] rx_ch1_i       ,
+    input [ADC_DATA_WIDTH-1 : 0] rx_ch1_q       ,
+    input [ADC_DATA_WIDTH-1 : 0] rx_ch2_i       ,
+    input [ADC_DATA_WIDTH-1 : 0] rx_ch2_q       ,
+    input [ADC_DATA_WIDTH-1 : 0] rx_ch3_i       ,
+    input [ADC_DATA_WIDTH-1 : 0] rx_ch3_q       ,
+    input [ADC_DATA_WIDTH-1 : 0] rx_ch4_i       ,
+    input [ADC_DATA_WIDTH-1 : 0] rx_ch4_q       ,
+    // output data interface
+    output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch1_i  ,
+    output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch1_q  ,
+    output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch2_i  ,
+    output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch2_q  ,
+    output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch3_i  ,
+    output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch3_q  ,
+    output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch4_i  ,
+    output [ADC_DATA_WIDTH-1 : 0] rx_cal_ch4_q
+);
+
+localparam STATE_IDLE = 2'd0; // idle state
+localparam STATE_CAL_1 = 2'd1; // correlation, accumulation and peak finding
+localparam STATE_CAL_2 = 2'd2; // phase calculation, rotation and delay compensation
+localparam STATE_DONE = 2'd3; // done state
+
+localparam signed POS_PI_2Q13_SCALED = 16'b001_00000_00000_000;
+localparam signed NEG_PI_2Q13_SCALED = 16'b111_00000_00000_000;
+
+integer i, j;
+genvar m, n;
+
+////////////////////////////////////////////////////////////////////////////////
+///////////////////////////// Center State Machine /////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// buffer input control signals (clock domain crossing from ps to pl clock domain)
+reg ad9361_1_cal_start_d1 = 'b0;
+reg ad9361_1_cal_start_d2 = 'b0;
+reg ad9361_2_cal_start_d1 = 'b0;
+reg ad9361_2_cal_start_d2 = 'b0;
+reg ad9361_recal_d1 = 'b0;
+reg ad9361_recal_d2 = 'b0;
+
+always @(posedge clk) begin
+    ad9361_1_cal_start_d1 <= ad9361_1_cal_start;
+    ad9361_1_cal_start_d2 <= ad9361_1_cal_start_d1;
+
+    ad9361_2_cal_start_d1 <= ad9361_2_cal_start;
+    ad9361_2_cal_start_d2 <= ad9361_2_cal_start_d1;
+
+    ad9361_recal_d1 <= ad9361_recal;
+    ad9361_recal_d2 <= ad9361_recal_d1;
+end
+
+// center state machine
+reg     [ 1:0]  curr_state = STATE_IDLE;
+
+always @(posedge clk) begin
+    if (rst) begin
+        curr_state <= STATE_IDLE;
+    end
+    else begin
+    case (curr_state)
+        STATE_IDLE: begin
+            // move to next state when [ad9361_1_cal_start] asserts
+            curr_state <= ad9361_1_cal_start_d2 ? STATE_CAL_1 : STATE_IDLE;
+        end
+        STATE_CAL_1: begin
+            // move to next state when 1st cal finishes and [ad9361_2_cal_start] asserts
+            curr_state <= ad9361_1_cal_done ? STATE_CAL_2 : STATE_CAL_1;
+        end
+        STATE_CAL_2: begin
+            // move to next state when 2nd cal finishes
+            curr_state <= ad9361_2_cal_done ? STATE_DONE : STATE_CAL_2;
+        end
+        STATE_DONE: begin
+            // move to IDLE state when it needs to recal
+            curr_state <= (ad9361_recal_d2) ? STATE_IDLE : STATE_DONE;
+        end
+        default: begin
+            curr_state <= STATE_IDLE;
+        end
+    endcase
+    end
+end
+
+////////////////////////////////////////////////////////////////////////////////
+///////////////////////////////// Accumulation /////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// state counter
+reg [$clog2(INTERP_FACTOR)-1    : 0] cnt_decim    = 'b0; // downsample counter, mod [INTERP_FACTOR]
+reg [$clog2(PRBS_LEN)-1         : 0] cnt_chip_in  = 'b0; // input chip counter, mod [PRBS_LEN]
+reg [$clog2(PRBS_LEN)-1         : 0] pn_curr_addr = 'b0; // current local pn address, mod [PRBS_LEN]
+reg [$clog2(ACCUM_SYMBOL_NUM)-1 : 0] cnt_symbol   = 'b0; // accumulation symbol counter, mod [ACCUM_SYMBOL_NUM]
+reg [$clog2(PRBS_LEN)-1         : 0] cnt_accum    = 'b0; // accumulation result index indicator, mod [PRBS_LEN]
+
+always @(posedge clk) begin
+    // downsample counter, each clock cycles increase by 1 during calibration state
+    if (rst) begin
+        cnt_decim <= 'b0;
+    end
+    else begin
+    case (curr_state)
+        STATE_IDLE : cnt_decim <= 'b0;
+        STATE_CAL_1: cnt_decim <= cnt_decim + 1'b1;
+        STATE_CAL_2: cnt_decim <= cnt_decim + 1'b1;
+        STATE_DONE : cnt_decim <= 'b0;
+        default    : cnt_decim <= 'b0;
+    endcase
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        cnt_chip_in <= 'b0;
+    end
+    else if (curr_state == STATE_IDLE) begin
+        // reset at IDLE state
+        cnt_chip_in <= 'b0;
+    end
+    else if (cnt_decim == INTERP_FACTOR-1) begin
+        // each time the number of samples received is [INTERP_FACTOR], increase the counter by 1,
+        // indicating a new chip is received
+        cnt_chip_in <= cnt_chip_in + 1'b1;
+    end
+    else begin
+        cnt_chip_in <= cnt_chip_in;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        pn_curr_addr <= 'b0;
+    end
+    else if (curr_state == STATE_IDLE) begin
+        // reset at IDLE state
+        pn_curr_addr <= 'b0;
+    end
+    else if (cnt_decim == INTERP_FACTOR-1) begin
+        // each time the number of samples received is [INTERP_FACTOR], if the number of complete symbols
+        // accumulated is [ACCUM_SYMBOL_NUM], increase the address by 2; otherwise by 1. The increasing-by-2
+        // behaviour is analogous to `circshift` operation in MATLAB.
+        pn_curr_addr <= (cnt_symbol == ACCUM_SYMBOL_NUM-1 && cnt_chip_in == PRBS_LEN-1) ? pn_curr_addr + 2'd2 : pn_curr_addr + 2'd1;
+    end
+    else begin
+        pn_curr_addr <= pn_curr_addr;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        cnt_symbol <= 'b0;
+    end
+    else if (curr_state == STATE_IDLE) begin
+        // reset at IDLE state
+        cnt_symbol <= 'b0;
+    end
+    else if (cnt_chip_in == PRBS_LEN-1 && cnt_decim == INTERP_FACTOR-1) begin
+        // each time the number of complete chips received is [PRBS_LEN], increase the counter by 1,
+        // indicating a complete symbol is received
+        cnt_symbol <= cnt_symbol + 1'b1;
+    end
+    else begin
+        cnt_symbol <= cnt_symbol;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        cnt_accum <= 'b0;
+    end
+    else if (curr_state == STATE_IDLE) begin
+        // reset at IDLE state
+        cnt_accum <= 'b0;
+    end
+    else if (cnt_symbol == ACCUM_SYMBOL_NUM-1 && cnt_chip_in == PRBS_LEN-1 && cnt_decim == INTERP_FACTOR-1) begin
+        // each time the number of complete symbols received is [ACCUM_SYMBOL_NUM], increase the counter by 1,
+        // indicating the accumulation of current pn code phased is finished
+        cnt_accum <= cnt_accum + 1'b1;
+    end
+    else begin
+        cnt_accum <= cnt_accum;
+    end
+end
+
+// accumulate the msb of input data at different sample position
+localparam MSB_ACCUM_LEN = $clog2(PRBS_LEN*ACCUM_SYMBOL_NUM)+2; // extra 2 bits to ensure signed operation and to prevent overflow
+
+reg signed [MSB_ACCUM_LEN-1 : 0] msb_accum_i [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1];
+reg signed [MSB_ACCUM_LEN-1 : 0] msb_accum_q [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1];
+
+always @(posedge clk) begin
+    if (rst) begin
+    for (i = 0; i < CHANNEL_NUM; i = i + 1) begin
+    for (j = 0; j < INTERP_FACTOR; j = j + 1) begin
+        msb_accum_i[i][j] <= 'b0;
+        msb_accum_q[i][j] <= 'b0;
+    end
+    end
+    end
+    else if (curr_state == STATE_CAL_1) begin
+        if (cnt_symbol == 'b0 && cnt_chip_in == 'b0) begin
+            // set the initial value to 1 when msb equals current pn code, otherwise set to -1
+            msb_accum_i[0][cnt_decim] <= (rx_ch2_i[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? 1'b1 : -1'b1;
+            msb_accum_q[0][cnt_decim] <= (rx_ch2_q[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? 1'b1 : -1'b1;
+            msb_accum_i[1][cnt_decim] <= (rx_ch4_i[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? 1'b1 : -1'b1;
+            msb_accum_q[1][cnt_decim] <= (rx_ch4_q[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? 1'b1 : -1'b1;
+        end
+        else begin
+            // increase when msb equals current pn code, otherwise decrease
+            msb_accum_i[0][cnt_decim] <= (rx_ch2_i[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? (msb_accum_i[0][cnt_decim] + 1'b1) : (msb_accum_i[0][cnt_decim] - 1'b1);
+            msb_accum_q[0][cnt_decim] <= (rx_ch2_q[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? (msb_accum_q[0][cnt_decim] + 1'b1) : (msb_accum_q[0][cnt_decim] - 1'b1);
+            msb_accum_i[1][cnt_decim] <= (rx_ch4_i[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? (msb_accum_i[1][cnt_decim] + 1'b1) : (msb_accum_i[1][cnt_decim] - 1'b1);
+            msb_accum_q[1][cnt_decim] <= (rx_ch4_q[ADC_DATA_WIDTH-1] == PRBS[pn_curr_addr]) ? (msb_accum_q[1][cnt_decim] + 1'b1) : (msb_accum_q[1][cnt_decim] - 1'b1);
+        end
+    end
+    else begin
+    for (i = 0; i < CHANNEL_NUM; i = i + 1) begin
+    for (j = 0; j < INTERP_FACTOR; j = j + 1) begin
+        msb_accum_i[i][j] <= 'b0;
+        msb_accum_q[i][j] <= 'b0;
+    end
+    end
+    end
+end
+
+// flag signal indicating the accumulation within one symbol (i.e. one kind of pn phase) is finished
+reg symbol_msb_accum_valid = 'b0;
+// preserve pn phase index for approximate moduli module
+reg [$clog2(PRBS_LEN)-1 : 0] symbol_msb_accum_index = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        symbol_msb_accum_valid <= 'b0;
+    end
+    else if (cnt_symbol == ACCUM_SYMBOL_NUM-1 && cnt_chip_in == PRBS_LEN-1 && cnt_decim == INTERP_FACTOR-1) begin
+        symbol_msb_accum_valid <= 1'b1;
+    end
+    else begin
+        symbol_msb_accum_valid <= 'b0;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        symbol_msb_accum_index <= 'b0;
+    end
+    else if (curr_state == STATE_IDLE) begin
+        symbol_msb_accum_index <= 'b0;
+    end
+    else if (cnt_symbol == ACCUM_SYMBOL_NUM-1 && cnt_chip_in == PRBS_LEN-1 && cnt_decim == INTERP_FACTOR-1) begin
+        symbol_msb_accum_index <= cnt_accum;
+    end
+    else begin
+        symbol_msb_accum_index <= symbol_msb_accum_index;
+    end
+end
+
+// truncate or shift to fit in 26-bit data format & get the absolute value
+wire [25 : 0] msb_accum_i_26b [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1];
+wire [25 : 0] msb_accum_q_26b [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1];
+wire [25 : 0] msb_accum_abs [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1];
+wire msb_accum_abs_valid [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1];
+
+generate
+for (m = 0; m < CHANNEL_NUM; m = m + 1) begin
+for (n = 0; n < INTERP_FACTOR; n = n + 1) begin
+
+assign msb_accum_i_26b[m][n] = (MSB_ACCUM_LEN > 26) ? msb_accum_i[m][n][MSB_ACCUM_LEN-1 -: 26] : {{(26-MSB_ACCUM_LEN){msb_accum_i[m][n][MSB_ACCUM_LEN-1]}},msb_accum_i[m][n]};
+assign msb_accum_q_26b[m][n] = (MSB_ACCUM_LEN > 26) ? msb_accum_q[m][n][MSB_ACCUM_LEN-1 -: 26] : {{(26-MSB_ACCUM_LEN){msb_accum_q[m][n][MSB_ACCUM_LEN-1]}},msb_accum_q[m][n]};
+
+ApproxModuli_26bit u_msb_accum_abs
+(
+    .clk        (clk                        ),
+    .din_valid  (symbol_msb_accum_valid     ),
+    .din_I      (msb_accum_i_26b[m][n]      ),
+    .din_Q      (msb_accum_q_26b[m][n]      ),
+    .dout_valid (msb_accum_abs_valid[m][n]  ),
+    .dout       (msb_accum_abs[m][n]        )
+);
+
+end
+end
+endgenerate
+
+
+// record the peak index and corresponding value
+reg [25 : 0] msb_accum_abs_peak [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1];
+reg [$clog2(PRBS_LEN)-1 : 0] msb_accum_abs_peak_index [0 : CHANNEL_NUM-1][0 : INTERP_FACTOR-1];
+
+generate
+for (m = 0; m < CHANNEL_NUM; m = m + 1) begin
+for (n = 0; n < INTERP_FACTOR; n = n + 1) begin
+
+always @(posedge clk) begin
+    if (rst) begin
+        msb_accum_abs_peak[m][n] <= 'b0;
+        msb_accum_abs_peak_index[m][n] <= 'b0;
+    end
+    else if (curr_state == STATE_IDLE) begin
+        msb_accum_abs_peak[m][n] <= 'b0;
+        msb_accum_abs_peak_index[m][n] <= 'b0;
+    end
+    else if (msb_accum_abs_valid[m][n]) begin
+        msb_accum_abs_peak[m][n]       <= (msb_accum_abs_peak[m][n] >= msb_accum_abs[m][n]) ? msb_accum_abs_peak[m][n]       : msb_accum_abs[m][n];
+        msb_accum_abs_peak_index[m][n] <= (msb_accum_abs_peak[m][n] >= msb_accum_abs[m][n]) ? msb_accum_abs_peak_index[m][n] : symbol_msb_accum_index;
+    end
+end
+
+end
+end
+endgenerate
+
+
+// accumulate input data at the 1st sample position and the 1st and 2nd chip position
+// during the last msb accumulation cycle
+localparam DATA_ACCUM_LEN = $clog2(ACCUM_SYMBOL_NUM)+ADC_DATA_WIDTH;
+
+reg signed [DATA_ACCUM_LEN-1 : 0] rx_i_accum [0 : CHANNEL_NUM-1][0 : 1];
+reg signed [DATA_ACCUM_LEN-1 : 0] rx_q_accum [0 : CHANNEL_NUM-1][0 : 1];
+
+always @(posedge clk) begin
+    if (rst) begin
+    for(i = 0; i < CHANNEL_NUM; i = i + 1) begin
+    for(j = 0; j < 2; j = j + 1) begin
+        rx_i_accum[i][j] <= 'b0;
+        rx_q_accum[i][j] <= 'b0;
+    end
+    end
+    end
+    else if (curr_state == STATE_IDLE) begin
+    for(i = 0; i < CHANNEL_NUM; i = i + 1) begin
+    for(j = 0; j < 2; j = j + 1) begin
+        // reset at IDLE state
+        rx_i_accum[i][j] <= 'b0;
+        rx_q_accum[i][j] <= 'b0;
+    end
+    end
+    end
+    else if (cnt_accum == PRBS_LEN-1 && cnt_decim == 'b0) begin
+        case (cnt_chip_in)
+            1'b0: begin
+                rx_i_accum[0][0] <= rx_i_accum[0][0] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch2_i[ADC_DATA_WIDTH-1]}},rx_ch2_i};
+                rx_q_accum[0][0] <= rx_q_accum[0][0] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch2_q[ADC_DATA_WIDTH-1]}},rx_ch2_q};
+                rx_i_accum[1][0] <= rx_i_accum[1][0] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch4_i[ADC_DATA_WIDTH-1]}},rx_ch4_i};
+                rx_q_accum[1][0] <= rx_q_accum[1][0] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch4_q[ADC_DATA_WIDTH-1]}},rx_ch4_q};
+            end
+            1'b1: begin
+                rx_i_accum[0][1] <= rx_i_accum[0][1] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch2_i[ADC_DATA_WIDTH-1]}},rx_ch2_i};
+                rx_q_accum[0][1] <= rx_q_accum[0][1] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch2_q[ADC_DATA_WIDTH-1]}},rx_ch2_q};
+                rx_i_accum[1][1] <= rx_i_accum[1][1] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch4_i[ADC_DATA_WIDTH-1]}},rx_ch4_i};
+                rx_q_accum[1][1] <= rx_q_accum[1][1] + {{(DATA_ACCUM_LEN-ADC_DATA_WIDTH){rx_ch4_q[ADC_DATA_WIDTH-1]}},rx_ch4_q};
+            end
+            default: begin
+            for(i = 0; i < CHANNEL_NUM; i = i + 1) begin
+            for(j = 0; j < 2; j = j + 1) begin
+                rx_i_accum[i][j] <= rx_i_accum[i][j];
+                rx_q_accum[i][j] <= rx_q_accum[i][j];
+            end
+            end
+            end
+        endcase
+    end
+    else begin
+    for(i = 0; i < CHANNEL_NUM; i = i + 1) begin
+    for(j = 0; j < 2; j = j + 1) begin
+        rx_i_accum[i][j] <= rx_i_accum[i][j];
+        rx_q_accum[i][j] <= rx_q_accum[i][j];
+    end
+    end
+    end
+end
+
+// flag signal indicating the accumulation stage of calculation is finished
+reg ad9361_1_cal_done_buf = 'b0;
+
+assign ad9361_1_cal_done = ad9361_1_cal_done_buf;
+
+always @(posedge clk) begin
+    if (rst) begin
+        ad9361_1_cal_done_buf <= 'b0;
+    end
+    else if (curr_state == STATE_IDLE) begin
+        // reset at IDLE state
+        ad9361_1_cal_done_buf <= 'b0;
+    end
+    else if (cnt_accum == PRBS_LEN-1 && cnt_symbol == ACCUM_SYMBOL_NUM-1 && cnt_chip_in == PRBS_LEN-1 && cnt_decim == INTERP_FACTOR-1) begin
+        ad9361_1_cal_done_buf <= 1'b1;
+    end
+    else begin
+        ad9361_1_cal_done_buf <= ad9361_1_cal_done_buf;
+    end
+end
+
+
+////////////////////////////////////////////////////////////////////////////////
+///////////////////////////////// Accumulation /////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// indicating the peak finding process is finished
+reg peak_index_valid = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        peak_index_valid <= 'b0;
+    end
+    else if (curr_state == STATE_CAL_2) begin
+        peak_index_valid <= msb_accum_abs_valid[0][0] ? 1'b1 : peak_index_valid;
+    end
+    else begin
+        peak_index_valid <= 'b0;
+    end
+end
+
+// count the number of same peak index
+reg [$clog2(INTERP_FACTOR)-1 : 0] peak_index_num [0 : CHANNEL_NUM-1];
+reg peak_index_num_valid = 'b0;
+
+reg signed [$clog2(INTERP_FACTOR) : 0] peak_index_num_diff = 'b0; // currently limit channel number to 2
+reg peak_index_num_diff_valid = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+    for (i = 0; i < CHANNEL_NUM; i = i + 1) begin
+        peak_index_num[i] <= 'b0;
+    end
+    end
+    else if (curr_state == STATE_CAL_2 && cnt_chip_in == 2'd2) begin
+    for (i = 0; i < CHANNEL_NUM; i = i + 1) begin
+        if (msb_accum_abs_peak_index[i][cnt_decim] == msb_accum_abs_peak_index[i][0]) begin
+            peak_index_num[i] <= cnt_decim;
+        end
+        else begin
+            peak_index_num[i] <= peak_index_num[i];
+        end
+    end
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        peak_index_num_valid <= 'b0;
+    end
+    else if (curr_state == STATE_IDLE) begin
+        peak_index_num_valid <= 'b0;
+    end
+    else if (curr_state == STATE_CAL_2 && cnt_chip_in == 2'd2 && cnt_decim == INTERP_FACTOR-1) begin
+        peak_index_num_valid <= 1'b1;
+    end
+    else begin
+        peak_index_num_valid <= 'b0;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        peak_index_num_diff <= 'b0;
+    end
+    else if (peak_index_num_valid) begin
+        peak_index_num_diff <= peak_index_num[1] - peak_index_num[0];
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        peak_index_num_diff_valid <= 'b0;
+    end
+    else if (curr_state == STATE_IDLE) begin
+        peak_index_num_diff_valid <= 'b0;
+    end
+    else begin
+        peak_index_num_diff_valid <= peak_index_num_valid;
+    end
+end
+
+//
+reg [$clog2(PRBS_LEN)-1 : 0] peak_index_plus_minus [0 : 2];
+
+always @(posedge clk) begin
+    if (rst) begin
+    for (i = 0; i < 3; i = i + 1) begin
+        peak_index_plus_minus[i] <= 'b0;
+    end
+    end
+    else if (curr_state == STATE_CAL_2) begin
+        peak_index_plus_minus[0] <= msb_accum_abs_peak_index[0][0];
+        peak_index_plus_minus[1] <= msb_accum_abs_peak_index[0][0] - 1'b1;
+        peak_index_plus_minus[2] <= msb_accum_abs_peak_index[0][0] + 1'b1;
+    end
+end
+
+// get target downsample position
+localparam CORDIC_LATENCY = 20;
+
+reg target_accum_index [0 : CHANNEL_NUM-1];
+reg target_accum_index_valid = 'b0;
+reg [$clog2(INTERP_FACTOR+CORDIC_LATENCY)-1 : 0] relative_delay = 'b0; // compensate cordic delay
+reg ad9361_cal_result_buf = 'b0;
+
+assign ad9361_cal_result = ad9361_cal_result_buf;
+
+always @(posedge clk) begin
+    if (rst) begin
+    for (i = 0; i < CHANNEL_NUM; i = i + 1) begin
+        target_accum_index[i] <= 'b0;
+    end
+    end
+    else if (peak_index_num_diff_valid) begin
+        if (msb_accum_abs_peak_index[1][0] == peak_index_plus_minus[0]) begin
+            target_accum_index[0] <= 1'b0;
+            target_accum_index[1] <= 1'b0;
+            relative_delay <= peak_index_num_diff + (CORDIC_LATENCY-1);
+            ad9361_cal_result_buf <= 1'b1;
+        end
+        else if (msb_accum_abs_peak_index[1][0] == peak_index_plus_minus[1]) begin
+            target_accum_index[0] <= 1'b0;
+            target_accum_index[1] <= 1'b1;
+            relative_delay <= peak_index_num_diff + INTERP_FACTOR + (CORDIC_LATENCY-1);
+            ad9361_cal_result_buf <= 1'b1;
+        end
+        else if (msb_accum_abs_peak_index[1][0] == peak_index_plus_minus[2]) begin
+            target_accum_index[0] <= 1'b1;
+            target_accum_index[1] <= 1'b0;
+            relative_delay <= peak_index_num_diff - INTERP_FACTOR + (CORDIC_LATENCY-1);
+            ad9361_cal_result_buf <= 1'b1;
+        end
+        else begin
+            target_accum_index[0] <= 1'b0;
+            target_accum_index[1] <= 1'b0;
+            relative_delay <= peak_index_num_diff + (CORDIC_LATENCY-1);
+            ad9361_cal_result_buf <= 1'b0;
+        end
+    end
+    else begin
+    for (i = 0; i < CHANNEL_NUM; i = i + 1) begin
+        target_accum_index[i] <= target_accum_index[i];
+    end
+        relative_delay <= relative_delay;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        target_accum_index_valid <= 'b0;
+    end
+    else if (curr_state == STATE_IDLE) begin
+        target_accum_index_valid <= 'b0;
+    end
+    else begin
+        target_accum_index_valid <= peak_index_num_diff_valid;
+    end
+end
+
+
+// get target data
+reg [DATA_ACCUM_LEN-1 : 0] rx_i_accum_target [0 : CHANNEL_NUM-1];
+reg [DATA_ACCUM_LEN-1 : 0] rx_q_accum_target [0 : CHANNEL_NUM-1];
+reg rx_accum_target_valid = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+    for (i = 0; i < CHANNEL_NUM; i = i + 1) begin
+        rx_i_accum_target[i] <= 'b0;
+        rx_q_accum_target[i] <= 'b0;
+    end
+    end
+    else if (target_accum_index_valid) begin
+    for (i = 0; i < CHANNEL_NUM; i = i + 1) begin
+        rx_i_accum_target[i] <= rx_i_accum[i][target_accum_index[i]];
+        rx_q_accum_target[i] <= rx_q_accum[i][target_accum_index[i]];
+    end
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        rx_accum_target_valid <= 'b0;
+    end
+    else if (curr_state == STATE_IDLE) begin
+        rx_accum_target_valid <= 'b0;
+    end
+    else begin
+        rx_accum_target_valid <= target_accum_index_valid;
+    end
+end
+
+// calculate phase difference
+localparam AXIS_CORDIC_WIDTH = 8*((CORDIC_WIDTH-1)/8+1);
+
+wire [AXIS_CORDIC_WIDTH-1 : 0] atan2_data_real [0 : CHANNEL_NUM-1];
+wire [AXIS_CORDIC_WIDTH-1 : 0] atan2_data_imag [0 : CHANNEL_NUM-1];
+
+wire [2*AXIS_CORDIC_WIDTH-1:0] atan2_data [0 : CHANNEL_NUM-1];
+wire atan2_valid_i [0 : CHANNEL_NUM-1];
+
+wire signed [AXIS_CORDIC_WIDTH-1:0] atan2_phase [0 : CHANNEL_NUM-1];
+wire atan2_valid_o [0 : CHANNEL_NUM-1];
+
+generate
+for (m = 0; m < CHANNEL_NUM; m = m + 1) begin
+
+assign atan2_data_real[m] = (DATA_ACCUM_LEN > AXIS_CORDIC_WIDTH) ? rx_i_accum_target[m][DATA_ACCUM_LEN-1 -: AXIS_CORDIC_WIDTH] : {{(AXIS_CORDIC_WIDTH-DATA_ACCUM_LEN){rx_i_accum_target[m][DATA_ACCUM_LEN-1]}},rx_i_accum_target[m]};
+assign atan2_data_imag[m] = (DATA_ACCUM_LEN > AXIS_CORDIC_WIDTH) ? rx_q_accum_target[m][DATA_ACCUM_LEN-1 -: AXIS_CORDIC_WIDTH] : {{(AXIS_CORDIC_WIDTH-DATA_ACCUM_LEN){rx_q_accum_target[m][DATA_ACCUM_LEN-1]}},rx_q_accum_target[m]};
+
+assign atan2_data[m] = {atan2_data_imag[m],atan2_data_real[m]};
+assign atan2_valid_i[m] = rx_accum_target_valid;
+
+atan2_16b u_atan2
+(
+    .aclk                   (clk                ), // input wire aclk
+    .s_axis_cartesian_tvalid(atan2_valid_i[m]   ), // input wire s_axis_cartesian_tvalid
+    .s_axis_cartesian_tdata (atan2_data[m]      ), // input wire [31 : 0] s_axis_cartesian_tdata
+    .m_axis_dout_tvalid     (atan2_valid_o[m]   ), // output wire m_axis_dout_tvalid
+    .m_axis_dout_tdata      (atan2_phase[m]     )  // output wire [15 : 0] m_axis_dout_tdata
+);
+
+end
+endgenerate
+
+reg signed [AXIS_CORDIC_WIDTH-1:0] phase_diff_raw = 'b0;
+reg phase_diff_raw_valid = 'b0;
+
+reg signed [AXIS_CORDIC_WIDTH-1:0] phase_diff = 'b0;
+reg phase_diff_valid = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        phase_diff_raw <= 'b0;
+    end
+    else if (atan2_valid_o[0]) begin
+        // here calculate the phase difference from target channel to another channel,
+        // then rotate another channel to target channel
+        phase_diff_raw <= atan2_phase[0] - atan2_phase[1];
+    end
+    else begin
+        phase_diff_raw <= phase_diff_raw;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        phase_diff_raw_valid <= 'b0;
+    end
+    else if (curr_state == STATE_IDLE) begin
+        phase_diff_raw_valid <= 'b0;
+    end
+    else if (atan2_valid_o[0]) begin
+        phase_diff_raw_valid <= 1'b1;
+    end
+    else begin
+        phase_diff_raw_valid <= phase_diff_raw_valid;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        phase_diff <= 'b0;
+    end
+    else if (phase_diff_raw_valid) begin
+        if (phase_diff_raw > POS_PI_2Q13_SCALED) begin
+            phase_diff <= phase_diff_raw - (2*POS_PI_2Q13_SCALED);
+        end
+        else if (phase_diff_raw < NEG_PI_2Q13_SCALED) begin
+            phase_diff <= phase_diff_raw + (2*POS_PI_2Q13_SCALED);
+        end
+        else begin
+            phase_diff <= phase_diff_raw;
+        end
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        phase_diff_valid <= 'b0;
+    end
+    else if (curr_state == STATE_IDLE) begin
+        phase_diff_valid <= 'b0;
+    end
+    else begin
+        phase_diff_valid <= phase_diff_raw_valid;
+    end
+end
+
+// rotate the 3rd and 4th channel
+wire rotate_phase_valid;
+wire [AXIS_CORDIC_WIDTH-1 : 0] rotate_phase_data;
+
+wire rotate_cart_valid;
+wire [AXIS_CORDIC_WIDTH-1 : 0] rotate_cart_ch3_data_real;
+wire [AXIS_CORDIC_WIDTH-1 : 0] rotate_cart_ch3_data_imag;
+wire [AXIS_CORDIC_WIDTH-1 : 0] rotate_cart_ch4_data_real;
+wire [AXIS_CORDIC_WIDTH-1 : 0] rotate_cart_ch4_data_imag;
+wire [2*AXIS_CORDIC_WIDTH-1 : 0] rotate_cart_ch3_data;
+wire [2*AXIS_CORDIC_WIDTH-1 : 0] rotate_cart_ch4_data;
+
+wire rotate_dout_ch3_valid;
+wire rotate_dout_ch4_valid;
+wire [2*AXIS_CORDIC_WIDTH-1 : 0] rotate_dout_ch3_data;
+wire [2*AXIS_CORDIC_WIDTH-1 : 0] rotate_dout_ch4_data;
+wire [AXIS_CORDIC_WIDTH-1 : 0] rx_ch3_rotate_i;
+wire [AXIS_CORDIC_WIDTH-1 : 0] rx_ch3_rotate_q;
+wire [AXIS_CORDIC_WIDTH-1 : 0] rx_ch4_rotate_i;
+wire [AXIS_CORDIC_WIDTH-1 : 0] rx_ch4_rotate_q;
+
+assign rotate_phase_valid = phase_diff_valid;
+assign rotate_phase_data = phase_diff;
+
+assign rotate_cart_valid = 1'b1;
+assign rotate_cart_ch3_data_real = (ADC_DATA_WIDTH > AXIS_CORDIC_WIDTH) ? rx_ch3_i[ADC_DATA_WIDTH-1 -: AXIS_CORDIC_WIDTH] : {rx_ch3_i,{(AXIS_CORDIC_WIDTH-ADC_DATA_WIDTH){1'b0}}};
+assign rotate_cart_ch3_data_imag = (ADC_DATA_WIDTH > AXIS_CORDIC_WIDTH) ? rx_ch3_q[ADC_DATA_WIDTH-1 -: AXIS_CORDIC_WIDTH] : {rx_ch3_q,{(AXIS_CORDIC_WIDTH-ADC_DATA_WIDTH){1'b0}}};
+assign rotate_cart_ch4_data_real = (ADC_DATA_WIDTH > AXIS_CORDIC_WIDTH) ? rx_ch4_i[ADC_DATA_WIDTH-1 -: AXIS_CORDIC_WIDTH] : {rx_ch4_i,{(AXIS_CORDIC_WIDTH-ADC_DATA_WIDTH){1'b0}}};
+assign rotate_cart_ch4_data_imag = (ADC_DATA_WIDTH > AXIS_CORDIC_WIDTH) ? rx_ch4_q[ADC_DATA_WIDTH-1 -: AXIS_CORDIC_WIDTH] : {rx_ch4_q,{(AXIS_CORDIC_WIDTH-ADC_DATA_WIDTH){1'b0}}};
+
+assign rotate_cart_ch3_data = {rotate_cart_ch3_data_imag,rotate_cart_ch3_data_real};
+assign rotate_cart_ch4_data = {rotate_cart_ch4_data_imag,rotate_cart_ch4_data_real};
+
+assign {rx_ch3_rotate_q,rx_ch3_rotate_i} = rotate_dout_ch3_data;
+assign {rx_ch4_rotate_q,rx_ch4_rotate_i} = rotate_dout_ch4_data;
+
+rotate_16b u_rotate_16b_ch3
+(
+    .aclk                   (clk                    ), // input wire aclk
+    .s_axis_phase_tvalid    (rotate_phase_valid     ), // input wire s_axis_phase_tvalid
+    .s_axis_phase_tdata     (rotate_phase_data      ), // input wire [15 : 0] s_axis_phase_tdata
+    .s_axis_cartesian_tvalid(rotate_cart_valid      ), // input wire s_axis_cartesian_tvalid
+    .s_axis_cartesian_tdata (rotate_cart_ch3_data   ), // input wire [31 : 0] s_axis_cartesian_tdata
+    .m_axis_dout_tvalid     (rotate_dout_ch3_valid  ), // output wire m_axis_dout_tvalid
+    .m_axis_dout_tdata      (rotate_dout_ch3_data   )  // output wire [31 : 0] m_axis_dout_tdata
+);
+
+rotate_16b u_rotate_16b_ch4
+(
+    .aclk                   (clk                    ), // input wire aclk
+    .s_axis_phase_tvalid    (rotate_phase_valid     ), // input wire s_axis_phase_tvalid
+    .s_axis_phase_tdata     (rotate_phase_data      ), // input wire [15 : 0] s_axis_phase_tdata
+    .s_axis_cartesian_tvalid(rotate_cart_valid      ), // input wire s_axis_cartesian_tvalid
+    .s_axis_cartesian_tdata (rotate_cart_ch4_data   ), // input wire [31 : 0] s_axis_cartesian_tdata
+    .m_axis_dout_tvalid     (rotate_dout_ch4_valid  ), // output wire m_axis_dout_tvalid
+    .m_axis_dout_tdata      (rotate_dout_ch4_data   )  // output wire [31 : 0] m_axis_dout_tdata
+);
+
+
+localparam TOTAL_LATENCY = CORDIC_LATENCY+INTERP_FACTOR-1;
+
+reg [ADC_DATA_WIDTH-1 : 0] rx_ch1_i_delay [0 : TOTAL_LATENCY-1];
+reg [ADC_DATA_WIDTH-1 : 0] rx_ch1_q_delay [0 : TOTAL_LATENCY-1];
+reg [ADC_DATA_WIDTH-1 : 0] rx_ch2_i_delay [0 : TOTAL_LATENCY-1];
+reg [ADC_DATA_WIDTH-1 : 0] rx_ch2_q_delay [0 : TOTAL_LATENCY-1];
+
+always @(posedge clk) begin
+    if (rst) begin
+    for (i = 0; i < TOTAL_LATENCY; i = i + 1) begin
+        rx_ch1_i_delay[i] <= 'b0;
+        rx_ch1_q_delay[i] <= 'b0;
+        rx_ch2_i_delay[i] <= 'b0;
+        rx_ch2_q_delay[i] <= 'b0;
+    end
+    end
+    else begin
+    for (i = 1; i < TOTAL_LATENCY; i = i + 1) begin
+        rx_ch1_i_delay[i] <= rx_ch1_i_delay[i-1];
+        rx_ch1_q_delay[i] <= rx_ch1_q_delay[i-1];
+        rx_ch2_i_delay[i] <= rx_ch2_i_delay[i-1];
+        rx_ch2_q_delay[i] <= rx_ch2_q_delay[i-1];
+    end
+        rx_ch1_i_delay[0] <= rx_ch1_i;
+        rx_ch1_q_delay[0] <= rx_ch1_q;
+        rx_ch2_i_delay[0] <= rx_ch2_i;
+        rx_ch2_q_delay[0] <= rx_ch2_q;
+    end
+end
+
+reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch1_i_buf = 'b0;
+reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch1_q_buf = 'b0;
+reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch2_i_buf = 'b0;
+reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch2_q_buf = 'b0;
+reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch3_i_buf = 'b0;
+reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch3_q_buf = 'b0;
+reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch4_i_buf = 'b0;
+reg [ADC_DATA_WIDTH-1 : 0] rx_cal_ch4_q_buf = 'b0;
+
+assign rx_cal_ch1_i = rx_cal_ch1_i_buf;
+assign rx_cal_ch1_q = rx_cal_ch1_q_buf;
+assign rx_cal_ch2_i = rx_cal_ch2_i_buf;
+assign rx_cal_ch2_q = rx_cal_ch2_q_buf;
+assign rx_cal_ch3_i = rx_cal_ch3_i_buf;
+assign rx_cal_ch3_q = rx_cal_ch3_q_buf;
+assign rx_cal_ch4_i = rx_cal_ch4_i_buf;
+assign rx_cal_ch4_q = rx_cal_ch4_q_buf;
+
+always @(posedge clk) begin
+    if (rst) begin
+        rx_cal_ch1_i_buf <= 'b0;
+        rx_cal_ch1_q_buf <= 'b0;
+        rx_cal_ch2_i_buf <= 'b0;
+        rx_cal_ch2_q_buf <= 'b0;
+        rx_cal_ch3_i_buf <= 'b0;
+        rx_cal_ch3_q_buf <= 'b0;
+        rx_cal_ch4_i_buf <= 'b0;
+        rx_cal_ch4_q_buf <= 'b0;
+    end
+    else if (rotate_dout_ch3_valid) begin
+        rx_cal_ch1_i_buf <=  rx_ch1_i_delay[relative_delay];
+        rx_cal_ch1_q_buf <=  rx_ch1_q_delay[relative_delay];
+        rx_cal_ch2_i_buf <= -rx_ch2_i_delay[relative_delay];
+        rx_cal_ch2_q_buf <= -rx_ch2_q_delay[relative_delay];
+        rx_cal_ch3_i_buf <=  rx_ch3_rotate_i[AXIS_CORDIC_WIDTH-1 -: ADC_DATA_WIDTH];
+        rx_cal_ch3_q_buf <=  rx_ch3_rotate_q[AXIS_CORDIC_WIDTH-1 -: ADC_DATA_WIDTH];
+        rx_cal_ch4_i_buf <= -rx_ch4_rotate_i[AXIS_CORDIC_WIDTH-1 -: ADC_DATA_WIDTH];
+        rx_cal_ch4_q_buf <= -rx_ch4_rotate_q[AXIS_CORDIC_WIDTH-1 -: ADC_DATA_WIDTH];
+    end
+    else begin
+        rx_cal_ch1_i_buf <= rx_ch1_i;
+        rx_cal_ch1_q_buf <= rx_ch1_q;
+        rx_cal_ch2_i_buf <= rx_ch2_i;
+        rx_cal_ch2_q_buf <= rx_ch2_q;
+        rx_cal_ch3_i_buf <= rx_ch3_i;
+        rx_cal_ch3_q_buf <= rx_ch3_q;
+        rx_cal_ch4_i_buf <= rx_ch4_i;
+        rx_cal_ch4_q_buf <= rx_ch4_q;
+    end
+end
+
+//
+reg ad9361_2_cal_done_buf = 'b0;
+
+assign ad9361_2_cal_done = ad9361_2_cal_done_buf;
+assign ad9361_cal_valid = ad9361_2_cal_done_buf;
+
+always @(posedge clk) begin
+    if (rst) begin
+        ad9361_2_cal_done_buf <= 'b0;
+    end
+    else begin
+        ad9361_2_cal_done_buf <= rotate_dout_ch3_valid;
+    end
+end
+
+endmodule

modules/xc7k410tffg900-2/multi_ch_cal/multi_ch_cal.xpr

@@ -0,0 +1,321 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!--                                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
+<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+
+<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/Workspace/vivado/vivado_pub/modules/xc7k410tffg900-2/multi_ch_cal/multi_ch_cal.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="3d8cac293e8046f6ba9154243a7267d4"/>
+    <Option Name="Part" Val="xc7k410tffg900-2"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
+    <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
+    <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
+    <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
+    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
+    <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="SimCompileState" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
+    <Option Name="WTXSimLaunchSim" Val="3"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="2"/>
+    <Option Name="WTModelSimExportSim" Val="2"/>
+    <Option Name="WTQuestaExportSim" Val="2"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="2"/>
+    <Option Name="WTRivieraExportSim" Val="2"/>
+    <Option Name="WTActivehdlExportSim" Val="2"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+  </Configuration>
+  <FileSets Version="1" Minor="32">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../../../common/ApproxModuli_26bit.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/multi_ch_cal.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="multi_ch_cal"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <File Path="$PSRCDIR/sim_1/new/tb_multi_ch_cal.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="tb_multi_ch_cal"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="atan2_16b" Type="BlockSrcs" RelSrcDir="$PSRCDIR/atan2_16b" RelGenDir="$PGENDIR/atan2_16b">
+      <File Path="$PSRCDIR/sources_1/ip/atan2_16b/atan2_16b.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="atan2_16b"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="rotate_16b" Type="BlockSrcs" RelSrcDir="$PSRCDIR/rotate_16b" RelGenDir="$PGENDIR/rotate_16b">
+      <File Path="$PSRCDIR/sources_1/ip/rotate_16b/rotate_16b.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="rotate_16b"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="21">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="atan2_16b_synth_1" Type="Ft3:Synth" SrcSet="atan2_16b" Part="xc7k410tffg900-2" ConstrsSet="atan2_16b" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/atan2_16b_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/atan2_16b_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/atan2_16b_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="rotate_16b_synth_1" Type="Ft3:Synth" SrcSet="rotate_16b" Part="xc7k410tffg900-2" ConstrsSet="rotate_16b" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/rotate_16b_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/rotate_16b_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/rotate_16b_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="atan2_16b_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="atan2_16b" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="atan2_16b_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/atan2_16b_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/atan2_16b_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="rotate_16b_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="rotate_16b" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="rotate_16b_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/rotate_16b_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/rotate_16b_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board/>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>

modules/xc7k410tffg900-2/tx_qpsk/tx_qpsk.srcs/sim_1/new/tb_tx_qpsk.v

@@ -0,0 +1,130 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+
+// Create Date: 2020/12/08 12:43:46
+// Design Name:
+// Module Name: tb_tx_qpsk
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_tx_qpsk;
+
+reg             clk         = 1'b0  ;
+reg             rst         = 1'b1  ;
+reg             tx_on       = 1'b1  ;
+reg     [31:0]  freq_set            ;
+reg     [ 1:0]  waveform_sel = 2'd1 ;
+reg     [ 1:0]  iq_sel      = 2'b11 ;
+wire    [11:0]  tx_data_i           ;
+wire    [11:0]  tx_data_q           ;
+reg     [ 3:0]  bb_rshift   = 5'b0  ;
+
+tx_qpsk u_tx_qpsk
+(
+    .clk            (clk            ),
+    .rst            (rst            ),
+    .tx_data_i      (tx_data_i      ),
+    .tx_data_q      (tx_data_q      ),
+    .waveform_sel   (waveform_sel   ),
+    .sweep_on       (1'b0           ),
+    // .freq_set       (32'd447392426  ),
+    .freq_set       (32'd0          ),
+    .iq_sel         (iq_sel         ),
+    .bb_rshift      (bb_rshift      )
+);
+
+initial begin
+    #102
+    rst = 1'b0;
+    // freq_set = 32'd873813333;
+    // waveform_sel = 2'b00;
+    // bb_rshift = 5'd0;
+    // #5000
+    // bb_rshift = 5'd1;
+    // #5000
+    // bb_rshift = 5'd2;
+    // #5000
+    // bb_rshift = 5'd3;
+    // #5000
+    // bb_rshift = 5'd4;
+    // #5000
+    // bb_rshift = 5'd5;
+    // #5000
+    // bb_rshift = 5'd6;
+    // #5000
+    // bb_rshift = 5'd7;
+    // #5000
+    // bb_rshift = 5'd8;
+    // #5000
+    // bb_rshift = 5'd9;
+    // #5000
+    // bb_rshift = 5'd14;
+    // #5000
+    // bb_rshift = 5'd15;
+    // #5000
+    // bb_rshift = 5'd16;
+    // freq_set = 32'd0;
+    // func_sel = 3'b010;
+    // #7777
+    // freq_set = 32'd536870912;
+    // func_sel = 3'b100;
+    // #7777
+    // freq_set = 32'd0;
+    // func_sel = 3'b100;
+    // #7777
+    // freq_set = 32'd536870912;
+    // func_sel = 3'b010;
+    // #7777
+    // freq_set = 32'd0;
+    // func_sel = 3'b010;
+    // freq_set = 32'd536870912;
+    // iq_sel = 2'b00;
+    // #7777
+    // freq_set = 32'd536870912;
+    // iq_sel = 2'b01;
+    // #7777
+    // freq_set = 32'd536870912;
+    // iq_sel = 2'b10;
+    // #7777
+    // freq_set = 32'd536870912;
+    // iq_sel = 2'b11;
+end
+
+always #5 clk = ~clk;
+
+// integer i;
+// integer w_file;
+
+// initial begin
+//     w_file = $fopen("D:\\qpsk_josh.txt","w");
+//     for (i = 0; i <= 35000; i = i + 1) begin
+//         wait(clk);
+//         #10;
+//         $fdisplay(w_file,"%d    %d",$signed(tx_data_i),
+//                 $signed(tx_data_q));
+//         if (i == 35000) begin
+//             $fclose(w_file);
+//             $stop;
+//         end
+//     end
+// end
+
+endmodule

modules/xc7k410tffg900-2/tx_qpsk/tx_qpsk.srcs/sources_1/ip/cmpy_18x8/cmpy_18x8.xci

@@ -0,0 +1,212 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "cmpy_18x8",
+    "component_reference": "xilinx.com:ip:cmpy:6.0",
+    "ip_revision": "22",
+    "gen_directory": "../../../../tx_qpsk.gen/sources_1/ip/cmpy_18x8",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "cmpy_18x8", "resolve_type": "user", "usage": "all" } ],
+        "APortWidth": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HasATLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HasATUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ATUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "BPortWidth": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HasBTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HasBTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "BTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MultType": [ { "value": "Use_LUTs", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "OptimizeGoal": [ { "value": "Resources", "resolve_type": "user", "usage": "all" } ],
+        "FlowControl": [ { "value": "NonBlocking", "resolve_type": "user", "usage": "all" } ],
+        "RoundMode": [ { "value": "Truncate", "resolve_type": "user", "usage": "all" } ],
+        "OutputWidth": [ { "value": "27", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HasCTRLTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HasCTRLTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CTRLTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "OutTLASTBehv": [ { "value": "Null", "resolve_type": "user", "usage": "all" } ],
+        "LatencyConfig": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "MinimumLatency": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ARESETN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_XDEVICEFAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
+        "C_XDEVICE": [ { "value": "xc7k410t", "resolve_type": "generated", "usage": "all" } ],
+        "C_A_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_B_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OUT_WIDTH": [ { "value": "27", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LATENCY": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MULT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPTIMIZE_GOAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "HAS_NEGATE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SINGLE_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "ROUND": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "USE_DSP_CASCADES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_THROTTLE_SCHEME": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ARESETN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_A_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_A_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_B_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_B_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_CTRL_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_CTRL_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_TLAST_RESOLUTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_A_TDATA_WIDTH": [ { "value": "48", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_A_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_B_TDATA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_B_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_CTRL_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_CTRL_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_DOUT_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_DOUT_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintex7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7k410t" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "22" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../tx_qpsk.gen/sources_1/ip/cmpy_18x8" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_a_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_a_tdata": [ { "direction": "in", "size_left": "47", "size_right": "0", "driver_value": "0" } ],
+        "s_axis_b_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_b_tdata": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_dout_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
+        "m_axis_dout_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "M_AXIS_DOUT": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_dout_tdata" } ],
+            "TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ]
+          }
+        },
+        "aclk_intf": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CTRL:S_AXIS_B:S_AXIS_A:M_AXIS_DOUT", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "aresetn_intf": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclken_intf": {
+          "vlnv": "xilinx.com:signal:clockenable:1.0",
+          "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
+          }
+        },
+        "S_AXIS_A": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "6", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_a_tdata" } ],
+            "TVALID": [ { "physical_name": "s_axis_a_tvalid" } ]
+          }
+        },
+        "S_AXIS_B": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_b_tdata" } ],
+            "TVALID": [ { "physical_name": "s_axis_b_tvalid" } ]
+          }
+        }
+      }
+    }
+  }
+}

modules/xc7k410tffg900-2/tx_qpsk/tx_qpsk.srcs/sources_1/ip/coe/hrc_64_12_025.coe

@@ -0,0 +1,771 @@
+RADIX = 10;
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modules/xc7k410tffg900-2/tx_qpsk/tx_qpsk.srcs/sources_1/ip/coe/sweep_freq.coe

@@ -0,0 +1,258 @@
+MEMORY_INITIALIZATION_RADIX = 10;
+MEMORY_INITIALIZATION_VECTOR = 
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modules/xc7k410tffg900-2/tx_qpsk/tx_qpsk.srcs/sources_1/ip/dds_32b_8b/dds_32b_8b.xci

@@ -0,0 +1,355 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "dds_32b_8b",
+    "component_reference": "xilinx.com:ip:dds_compiler:6.0",
+    "ip_revision": "23",
+    "gen_directory": "../../../../tx_qpsk.gen/sources_1/ip/dds_32b_8b",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "dds_32b_8b", "resolve_type": "user", "usage": "all" } ],
+        "PartsPresent": [ { "value": "Phase_Generator_and_SIN_COS_LUT", "resolve_type": "user", "usage": "all" } ],
+        "DDS_Clock_Rate": [ { "value": "100", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Channels": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
+        "Mode_of_Operation": [ { "value": "Standard", "resolve_type": "user", "usage": "all" } ],
+        "Modulus": [ { "value": "9", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Parameter_Entry": [ { "value": "Hardware_Parameters", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Spurious_Free_Dynamic_Range": [ { "value": "45", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Frequency_Resolution": [ { "value": "0.4", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Noise_Shaping": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Output_Width": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Phase_Increment": [ { "value": "Programmable", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Resync": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Phase_offset": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "Output_Selection": [ { "value": "Sine_and_Cosine", "resolve_type": "user", "usage": "all" } ],
+        "Negative_Sine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Negative_Cosine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Amplitude_Mode": [ { "value": "Full_Range", "resolve_type": "user", "usage": "all" } ],
+        "Memory_Type": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
+        "Optimization_Goal": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
+        "DSP48_Use": [ { "value": "Minimal", "resolve_type": "user", "usage": "all" } ],
+        "Has_Phase_Out": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "DATA_Has_TLAST": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Has_TREADY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "S_PHASE_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "S_PHASE_TUSER_Width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M_DATA_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "M_PHASE_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
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+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
+            "TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
+          }
+        },
+        "S_AXIS_CONFIG": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_config_tdata" } ],
+            "TVALID": [ { "physical_name": "s_axis_config_tvalid" } ]
+          }
+        }
+      }
+    }
+  }
+}

modules/xc7k410tffg900-2/tx_qpsk/tx_qpsk.srcs/sources_1/ip/hop_rom/hop_rom.xci

@@ -0,0 +1,252 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "hop_rom",
+    "component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
+    "ip_revision": "7",
+    "gen_directory": "../../../../tx_qpsk.gen/sources_1/ip/hop_rom",
+    "parameters": {
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+        "Component_Name": [ { "value": "hop_rom", "resolve_type": "user", "usage": "all" } ],
+        "Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
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+        "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Memory_Type": [ { "value": "Single_Port_ROM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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+        "EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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+        "Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Write_Width_B": [ { "value": "32", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Read_Width_B": [ { "value": "32", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_B": [ { "value": "Always_Enabled", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Load_Init_File": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Coe_File": [ { "value": "../coe/sweep_freq.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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+        "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_A_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Clock": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Enable_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ],
+        "MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ],
+        "CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ],
+        "EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
+      },
+      "model_parameters": {
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+        "C_XDEVICEFAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
+        "C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
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+        "C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_32BIT_ADDRESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MEM_TYPE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BYTE_SIZE": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LOAD_INIT_FILE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INIT_FILE_NAME": [ { "value": "hop_rom.mif", "resolve_type": "generated", "usage": "all" } ],
+        "C_INIT_FILE": [ { "value": "hop_rom.mem", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
+        "C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_ENA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BYTE_WEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WEA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
+        "C_WRITE_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_DEPTH_A": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_DEPTH_A": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ADDRA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
+        "C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_ENB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BYTE_WEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WEB_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
+        "C_WRITE_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_DEPTH_B": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_DEPTH_B": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ADDRB_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
+        "C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COUNT_36K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_COUNT_18K_BRAM": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+        "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP     :     3.375199 mW", "resolve_type": "generated", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintex7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7k410t" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "7" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../tx_qpsk.gen/sources_1/ip/hop_rom" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "clka": [ { "direction": "in", "driver_value": "0" } ],
+        "addra": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "douta": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
+      },
+      "interfaces": {
+        "CLK.ACLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "RST.ARESETN": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "BRAM_PORTA": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addra" } ],
+            "CLK": [ { "physical_name": "clka" } ],
+            "DOUT": [ { "physical_name": "douta" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S_1": {
+          "address_blocks": {
+            "Mem0": {
+              "base_address": "0",
+              "range": "4096",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}

modules/xc7k410tffg900-2/tx_qpsk/tx_qpsk.srcs/sources_1/ip/hrc_64_12_025/hrc_64_12_025.xci

@@ -4,7 +4,7 @@
     "xci_name": "hrc_64_12_025",
     "component_reference": "xilinx.com:ip:fir_compiler:7.2",
     "ip_revision": "20",
-    "gen_directory": "../../../../tx_qpsk_poly.gen/sources_1/ip/hrc_64_12_025",
+    "gen_directory": "../../../../tx_qpsk.gen/sources_1/ip/hrc_64_12_025",
     "parameters": {
       "component_parameters": {
         "Component_Name": [ { "value": "hrc_64_12_025", "resolve_type": "user", "usage": "all" } ],
@@ -90,7 +90,7 @@
         "Filter_Selection": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ]
       },
       "model_parameters": {
-        "C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_XDEVICEFAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
         "C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
         "C_COMPONENT_NAME": [ { "value": "hrc_64_12_025", "resolve_type": "generated", "usage": "all" } ],
         "C_COEF_FILE": [ { "value": "hrc_64_12_025.mif", "resolve_type": "generated", "usage": "all" } ],
@@ -162,23 +162,23 @@
         "C_RELOAD_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu48dr" } ],
+        "DEVICE": [ { "value": "xc7k410t" } ],
-        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
         "SPEEDGRADE": [ { "value": "-2" } ],
         "STATIC_POWER": [ { "value": "" } ],
-        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
       },
       "runtime_parameters": {
         "IPCONTEXT": [ { "value": "IP_Flow" } ],
         "IPREVISION": [ { "value": "20" } ],
         "MANAGED": [ { "value": "TRUE" } ],
-        "OUTPUTDIR": [ { "value": "../../../../tx_qpsk_poly.gen/sources_1/ip/hrc_64_12_025" } ],
+        "OUTPUTDIR": [ { "value": "../../../../tx_qpsk.gen/sources_1/ip/hrc_64_12_025" } ],
         "SELECTEDSIMMODEL": [ { "value": "" } ],
         "SHAREDDIR": [ { "value": "." } ],
         "SWVERSION": [ { "value": "2023.2.1" } ],

modules/xc7k410tffg900-2/tx_qpsk/tx_qpsk.srcs/sources_1/new/tx_qpsk.v

@@ -0,0 +1,412 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/03/23 20:17:56
+// Last Modified Date: 2023/03/10 15:41
+// Design Name:
+// Module Name: tx_qpsk
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+//   Revision 0.01 - File Created
+//   20230228-1541 - 修改不扫频、无基带频偏时 [baseband_i/q] 的数据输出，原来从
+//     乘法器引出，会导致频率为 0 时输出数据错误，现在直接从基带数据引出。
+//   20230310-1542 - 增加输入参数，发送数据更改为直接由参数输入，发送方波改为 8
+//     倍过采样，发送双音信号中 1MHz 信号的频率控制字可以根据参数中的时钟频率计
+//     算得出。
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tx_qpsk
+#(
+    parameter DATA_WIDTH = 12, // need to be <= 16
+    parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
+    parameter BIT_DATA_LEN = 128,
+    parameter SQUARE_INTERP = 8,
+    parameter CLK_FREQ = 245760000 // in Hertz
+)
+(
+    input           clk                 ,
+    input           rst                 ,
+    output [DATA_WIDTH-1:0] tx_data_i   ,
+    output [DATA_WIDTH-1:0] tx_data_q   ,
+    // debug ports
+    input   [ 1:0]  waveform_sel        ,
+    input           sweep_on            ,
+    input   [31:0]  freq_set            ,
+    input   [ 1:0]  iq_sel              ,
+    input   [ 3:0]  bb_rshift
+);
+
+localparam RCOS_INTERP = 64;
+localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP;
+localparam FREQ_WORD_1M = 64'd2**64'd32*64'd1000000/CLK_FREQ;
+
+////////////////////////////////////////////////////////////////////////////////
+///////////////////////////////// Data Counter /////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// symbol & interpolation counter
+reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0]  cnt = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        cnt <= 'b0;
+    end
+    else begin
+        cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1;
+    end
+end
+
+////////////////////////////////////////////////////////////////////////////////
+////////////////////// Root-Rasied Cosine Shaping Filter ///////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// address
+reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_i = 'b0;
+reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_q = 'b1;
+
+always @(posedge clk) begin
+    if (rst) begin
+        hrc_data_addr_i <= 'b0;
+        hrc_data_addr_q <= 'b1;
+    end
+    else begin
+        hrc_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0};
+        hrc_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1};
+    end
+end
+
+// bit data
+reg hrc_data_i = 'b0;
+reg hrc_data_q = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        hrc_data_i <= 'b0;
+        hrc_data_q <= 'b0;
+    end
+    else begin
+        hrc_data_i <= BIT_DATA[hrc_data_addr_i];
+        hrc_data_q <= BIT_DATA[hrc_data_addr_q];
+    end
+end
+
+// polarization
+wire    [ 7:0]  hrc_data_polar_i;
+wire    [ 7:0]  hrc_data_polar_q;
+
+assign hrc_data_polar_i = {{7{hrc_data_i}},1'b1};
+assign hrc_data_polar_q = {{7{hrc_data_q}},1'b1};
+
+// root raised cosine shaping-filter
+wire    [23:0]  hrc_wave_i;
+wire    [23:0]  hrc_wave_q;
+
+hrc_64_12_025 u_hrc_i (
+    .aclk               (clk                ), // input wire aclk
+    .s_axis_data_tvalid (~rst               ), // input wire s_axis_data_tvalid
+    .s_axis_data_tready (                   ), // output wire s_axis_data_tready
+    .s_axis_data_tdata  (hrc_data_polar_i   ), // input wire [7 : 0] s_axis_data_tdata
+    .m_axis_data_tvalid (                   ), // output wire m_axis_data_tvalid
+    .m_axis_data_tdata  (hrc_wave_i         )  // output wire [23 : 0] m_axis_data_tdata
+);
+
+hrc_64_12_025 u_hrc_q (
+    .aclk               (clk                ), // input wire aclk
+    .s_axis_data_tvalid (~rst               ), // input wire s_axis_data_tvalid
+    .s_axis_data_tready (                   ), // output wire s_axis_data_tready
+    .s_axis_data_tdata  (hrc_data_polar_q   ), // input wire [7 : 0] s_axis_data_tdata
+    .m_axis_data_tvalid (                   ), // output wire m_axis_data_tvalid
+    .m_axis_data_tdata  (hrc_wave_q         )  // output wire [23 : 0] m_axis_data_tdata
+);
+
+
+////////////////////////////////////////////////////////////////////////////////
+//////////////////////////// Square Shaping Filter /////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// address
+reg [$clog2(BIT_DATA_LEN)-1 : 0] hsq_data_addr = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        hsq_data_addr <= 'b0;
+    end
+    else
+        hsq_data_addr <= {cnt[$clog2(SQUARE_INTERP) +: $clog2(BIT_DATA_LEN)]};
+end
+
+// bit data
+reg hsq_data = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        hsq_data <= 'b0;
+    end
+    else begin
+        hsq_data <= BIT_DATA[hsq_data_addr];
+    end
+end
+
+// square shaping-filter
+reg     [17:0]  hsq_wave_i ='b0;
+reg     [17:0]  hsq_wave_q ='b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        hsq_wave_i <= 'b0;
+        hsq_wave_q <= 'b0;
+    end
+    else begin
+        hsq_wave_i <= hsq_data ? 18'b01_1111_1111_1111_1111 : 18'b10_0000_0000_0000_0001;
+        hsq_wave_q <= hsq_data ? 18'b10_0000_0000_0000_0001 : 18'b01_1111_1111_1111_1111;
+    end
+end
+
+
+////////////////////////////////////////////////////////////////////////////////
+/////////////////////////////// Two Tone Siganl ////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// cosine wave with freq of 1 MHz
+wire signed [7:0] cos_1m;
+wire signed [7:0] sin_1m;
+
+dds_32b_8b u_dds_1m
+(
+    .aclk                 (clk                  ),  // input wire aclk
+    .s_axis_config_tvalid (1'b1                 ),  // input wire s_axis_config_tvalid
+    .s_axis_config_tdata  (FREQ_WORD_1M[31:0]   ),  // input wire [31 : 0] s_axis_config_tdata
+    .m_axis_data_tvalid   (                     ),  // output wire m_axis_data_tvalid
+    .m_axis_data_tdata    ({sin_1m,cos_1m}      )   // output wire [15 : 0] m_axis_data_tdata
+);
+
+// two-tone signal
+reg signed [16:0] two_tone_wave_i = 'b0;
+reg signed [16:0] two_tone_wave_q = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        two_tone_wave_i <= 'b0;
+        two_tone_wave_q <= 'b0;
+    end
+    else begin
+        two_tone_wave_i <= 17'b0_0111_1111_1111_1111 + {cos_1m[7],cos_1m,8'd0};
+        two_tone_wave_q <= 17'b0 + {sin_1m[7],sin_1m,8'd0};
+    end
+end
+
+
+////////////////////////////////////////////////////////////////////////////////
+///////////////////// Waveform Selection & Hopping Control /////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// baseband signal select
+reg [17:0] baseband_sel_i = 'b0;
+reg [17:0] baseband_sel_q = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        baseband_sel_i <= 'b0;
+        baseband_sel_q <= 'b0;
+    end
+    else begin
+        case (waveform_sel[1:0])
+            2'd0: begin
+                baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
+                baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
+            end
+            2'd1: begin
+                baseband_sel_i <= hsq_wave_i[17:0];
+                baseband_sel_q <= hsq_wave_q[17:0];
+            end
+            2'd2: begin
+                baseband_sel_i <= 18'b01_1111_1111_1111_1111;
+                baseband_sel_q <= 18'b0;
+            end
+            2'd3: begin
+                baseband_sel_i <= {two_tone_wave_i[16:0],1'b0};
+                baseband_sel_q <= {two_tone_wave_q[16:0],1'b0};
+            end
+            default: begin
+                baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
+                baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
+            end
+        endcase
+    end
+end
+
+// hopping control, 3750hop/s
+reg     [23:0]  sweep_rom_addr = 'b0;
+wire    [31:0]  freq_sweep;
+
+always @(posedge clk) begin
+    if (rst) begin
+        sweep_rom_addr <= 'b0;
+    end
+    else if (sweep_on) begin
+        sweep_rom_addr <= sweep_rom_addr + 24'b1;
+    end
+    else begin
+        sweep_rom_addr <= 'b0;
+    end
+end
+
+hop_rom u_sweep_rom
+(
+    .clka       (clk                    ), // input wire clka
+    .addra      (sweep_rom_addr[23:16]  ), // input wire [7 : 0] addra
+    .douta      (freq_sweep             )  // output wire [31 : 0] douta
+);
+
+// choose the actual frequency word
+reg     [31:0]  freq_word = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        freq_word <= 'b0;
+    end
+    else if (sweep_on) begin
+        // frequency sweep
+        freq_word <= freq_sweep;
+    end
+    else begin
+        // normal operation
+        freq_word <= freq_set;
+    end
+end
+
+// baseband frequency shift carrier generation
+wire    [ 7:0] cos_dds;
+wire    [ 7:0] sin_dds;
+reg     [ 7:0] cos = 'b0;
+reg     [ 7:0] sin = 'b0;
+
+dds_32b_8b u_dds_bb_shift (
+    .aclk                 (clk              ), // input wire aclk
+    .s_axis_config_tvalid (~rst             ), // input wire s_axis_config_tvalid
+    .s_axis_config_tdata  (freq_word        ), // input wire [31 : 0] s_axis_config_tdata
+    .m_axis_data_tvalid   (                 ), // output wire m_axis_data_tvalid
+    .m_axis_data_tdata    ({sin_dds,cos_dds})  // output wire [31 : 0] m_axis_data_tdata
+);
+
+always @(posedge clk) begin
+    if (rst) begin
+        cos <= 'b0;
+        sin <= 'b0;
+    end
+    else if (freq_word == 'b0) begin
+        // to make sure the carriers stay at the right position when freq = 0
+        cos <= 8'b0111_1111;
+        sin <= 8'b0111_1111;
+    end
+    else begin
+        cos <= cos_dds;
+        sin <= sin_dds;
+    end
+end
+
+// baseband frequency shift modulation
+wire    [47:0]  mod_cmpy_a;
+wire    [15:0]  mod_cmpy_b;
+wire    [63:0]  mod_cmpy_out;
+
+wire    [26:0]  baseband_mult_i;
+wire    [26:0]  baseband_mult_q;
+
+assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i};
+assign mod_cmpy_b = {-sin,cos};
+
+assign baseband_mult_i = mod_cmpy_out[58:32];
+assign baseband_mult_q = mod_cmpy_out[26: 0];
+
+cmpy_18x8 u_cmpy_18x8
+(
+    .aclk               (clk            ), // input wire aclk
+    .s_axis_a_tvalid    (1'b1           ), // input wire s_axis_a_tvalid
+    .s_axis_a_tdata     (mod_cmpy_a     ), // input wire [47 : 0] s_axis_a_tdata
+    .s_axis_b_tvalid    (1'b1           ), // input wire s_axis_b_tvalid
+    .s_axis_b_tdata     (mod_cmpy_b     ), // input wire [15 : 0] s_axis_b_tdata
+    .m_axis_dout_tvalid (               ), // output wire m_axis_dout_tvalid
+    .m_axis_dout_tdata  (mod_cmpy_out   )  // output wire [63 : 0] m_axis_dout_tdata
+);
+
+// truncate to 16-bit
+reg signed  [15:0]  baseband_i = 'b0;
+reg signed  [15:0]  baseband_q = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        baseband_i <= 'b0;
+        baseband_q <= 'b0;
+    end
+    else begin
+        case (waveform_sel[1:0])
+            2'd0: begin
+                // scale rasied-cosine-shaped bpsk signal by 1.125 or 1.625
+                baseband_i <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_i[17 -: 16] + {{3{baseband_sel_i[17]}},baseband_sel_i[17 -: 13]}) : (baseband_mult_i[25:10] + {baseband_mult_i[25],baseband_mult_i[25:11]} + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]});
+                baseband_q <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_q[17 -: 16] + {{3{baseband_sel_q[17]}},baseband_sel_q[17 -: 13]}) : (baseband_mult_q[25:10] + {baseband_mult_q[25],baseband_mult_q[25:11]} + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]});
+            end
+            2'd1: begin
+                baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : (baseband_mult_i[25:10] + {{2{baseband_mult_i[25]}},baseband_mult_i[25:12]});
+                baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : (baseband_mult_q[25:10] + {{2{baseband_mult_q[25]}},baseband_mult_q[25:12]});
+            end
+            2'd2: begin
+                baseband_i <= baseband_mult_i[24:9];
+                baseband_q <= baseband_mult_q[24:9];
+            end
+            2'd3: begin
+                baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9];
+                baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9];
+            end
+            default: begin
+                // scale rasied-cosine-shaped bpsk signal by 1.125
+                baseband_i <= baseband_mult_i[25:10] + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]};
+                baseband_q <= baseband_mult_q[25:10] + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]};
+            end
+        endcase
+    end
+end
+
+// iq selection & baseband right shift
+reg signed [15:0] baseband_data_i = 'b0;
+reg signed [15:0] baseband_data_q = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        baseband_data_i <= 'b0;
+        baseband_data_q <= 'b0;
+    end
+    else begin
+        // inphase selection
+        if (iq_sel[1]) begin
+            baseband_data_i <= baseband_i >>> bb_rshift;
+        end
+        else begin
+            baseband_data_i <= 'b0;
+        end
+        // quadrature selection
+        if (iq_sel[0]) begin
+            baseband_data_q <= baseband_q >>> bb_rshift;
+        end
+        else begin
+            baseband_data_q <= 'b0;
+        end
+    end
+end
+
+// output data to ports
+assign tx_data_i = baseband_data_i[15 -: DATA_WIDTH];
+assign tx_data_q = baseband_data_q[15 -: DATA_WIDTH];
+
+endmodule

modules/xc7k410tffg900-2/tx_qpsk/tx_qpsk.xpr

@@ -0,0 +1,414 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!--                                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
+<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+
+<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/Workspace/vivado/vivado_pub/modules/xc7k410tffg900-2/tx_qpsk/tx_qpsk.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="148f7275fd02472a85da2f9f50b75194"/>
+    <Option Name="Part" Val="xc7k410tffg900-2"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
+    <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
+    <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
+    <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
+    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
+    <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="SimCompileState" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="4"/>
+    <Option Name="WTModelSimExportSim" Val="4"/>
+    <Option Name="WTQuestaExportSim" Val="4"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="4"/>
+    <Option Name="WTRivieraExportSim" Val="4"/>
+    <Option Name="WTActivehdlExportSim" Val="4"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+  </Configuration>
+  <FileSets Version="1" Minor="32">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/new/tx_qpsk.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/ip/coe/hrc_64_12_025.coe">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/ip/coe/sweep_freq.coe">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="tx_qpsk"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <File Path="$PSRCDIR/sim_1/new/tb_tx_qpsk.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="tb_tx_qpsk"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="dds_32b_8b" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dds_32b_8b" RelGenDir="$PGENDIR/dds_32b_8b">
+      <File Path="$PSRCDIR/sources_1/ip/dds_32b_8b/dds_32b_8b.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="dds_32b_8b"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="hrc_64_12_025" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_64_12_025" RelGenDir="$PGENDIR/hrc_64_12_025">
+      <File Path="$PSRCDIR/sources_1/ip/hrc_64_12_025/hrc_64_12_025.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="hrc_64_12_025"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="cmpy_18x8" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_18x8" RelGenDir="$PGENDIR/cmpy_18x8">
+      <File Path="$PSRCDIR/sources_1/ip/cmpy_18x8/cmpy_18x8.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="cmpy_18x8"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="hop_rom" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hop_rom" RelGenDir="$PGENDIR/hop_rom">
+      <File Path="$PSRCDIR/sources_1/ip/hop_rom/hop_rom.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="hop_rom"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="21">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="dds_32b_8b_synth_1" Type="Ft3:Synth" SrcSet="dds_32b_8b" Part="xc7k410tffg900-2" ConstrsSet="dds_32b_8b" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dds_32b_8b_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dds_32b_8b_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dds_32b_8b_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="hrc_64_12_025_synth_1" Type="Ft3:Synth" SrcSet="hrc_64_12_025" Part="xc7k410tffg900-2" ConstrsSet="hrc_64_12_025" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hrc_64_12_025_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="cmpy_18x8_synth_1" Type="Ft3:Synth" SrcSet="cmpy_18x8" Part="xc7k410tffg900-2" ConstrsSet="cmpy_18x8" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/cmpy_18x8_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_18x8_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_18x8_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="hop_rom_synth_1" Type="Ft3:Synth" SrcSet="hop_rom" Part="xc7k410tffg900-2" ConstrsSet="hop_rom" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hop_rom_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hop_rom_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hop_rom_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
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+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
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+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
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+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
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+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="cmpy_18x8_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="cmpy_18x8" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="cmpy_18x8_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_18x8_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_18x8_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="hop_rom_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="hop_rom" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hop_rom_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hop_rom_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hop_rom_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board/>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>

modules/xc7k410tffg900-2/var_cal/var_cal.srcs/sim_1/new/tb_var_cal.v

@@ -0,0 +1,94 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 06/11/2023 03:49:38 PM
+// Design Name:
+// Module Name: tb_var_cal
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_var_cal;
+
+localparam DATA_I_WIDTH = 30;
+
+reg clk = 1'b1;
+reg clk_init = 1'b1;
+reg rst = 1'b1;
+
+reg cal_start = 1'b0;
+reg cal_auto_en = 1'b0;
+wire cal_busy;
+
+reg din_valid = 1'b0;
+reg [29:0] din_file_real = 'b0;
+reg [29:0] din_file_imag = 'b0;
+wire [DATA_I_WIDTH-1:0] din_real;
+wire [DATA_I_WIDTH-1:0] din_imag;
+
+assign din_real = din_file_real[29 -: DATA_I_WIDTH];
+assign din_imag = din_file_imag[29 -: DATA_I_WIDTH];
+
+wire var_valid;
+wire [31:0] var;
+
+var_cal #(
+    .ACCUM_NUM      (16384          ),
+    .DATA_I_WIDTH   (DATA_I_WIDTH   ),
+    .DATA_O_WIDTH   (32             )
+) u_var_cal
+(
+    .clk        (clk        ),
+    .rst        (rst        ),
+
+    .cal_start  (cal_start  ),
+    .cal_auto_en(cal_auto_en),
+    .cal_busy   (cal_busy   ),
+
+    .din_valid  (din_valid  ),
+    .din_real   (din_real   ),
+    .din_imag   (din_imag   ),
+
+    .var_valid  (var_valid  ),
+    .var        (var        )
+);
+
+integer i;
+integer r_file;
+
+initial begin
+    #102
+    rst = 1'b0;
+    #100
+    din_valid = 1'b1;
+    // cal_start = 1'b1;
+    cal_auto_en = 1'b1;
+
+    r_file = $fopen("./../../../../../testbenches/singletone.csv","r");
+    for (i = 0; i <= 32768; i = i + 1) begin
+        @(posedge clk)
+        $fscanf(r_file,"%d,%d",din_file_real,din_file_imag);
+    end
+    $fclose(r_file);
+    $stop;
+end
+
+always #10 clk_init = ~clk_init;
+
+always @(posedge clk_init) begin
+    clk <= ~clk;
+end
+
+endmodule

modules/xc7k410tffg900-2/var_cal/var_cal.srcs/sources_1/ip/cmpy_18x18_mult/cmpy_18x18_mult.xci

@@ -0,0 +1,212 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "cmpy_18x18_mult",
+    "component_reference": "xilinx.com:ip:cmpy:6.0",
+    "ip_revision": "22",
+    "gen_directory": "../../../../var_cal.gen/sources_1/ip/cmpy_18x18_mult",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "cmpy_18x18_mult", "resolve_type": "user", "usage": "all" } ],
+        "APortWidth": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HasATLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HasATUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ATUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "BPortWidth": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HasBTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HasBTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "BTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MultType": [ { "value": "Use_Mults", "resolve_type": "user", "usage": "all" } ],
+        "OptimizeGoal": [ { "value": "Resources", "resolve_type": "user", "usage": "all" } ],
+        "FlowControl": [ { "value": "NonBlocking", "resolve_type": "user", "usage": "all" } ],
+        "RoundMode": [ { "value": "Truncate", "resolve_type": "user", "usage": "all" } ],
+        "OutputWidth": [ { "value": "37", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HasCTRLTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HasCTRLTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CTRLTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "OutTLASTBehv": [ { "value": "Null", "resolve_type": "user", "usage": "all" } ],
+        "LatencyConfig": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "MinimumLatency": [ { "value": "6", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ARESETN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_XDEVICEFAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
+        "C_XDEVICE": [ { "value": "xc7k410t", "resolve_type": "generated", "usage": "all" } ],
+        "C_A_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_B_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OUT_WIDTH": [ { "value": "37", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LATENCY": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MULT_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPTIMIZE_GOAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "HAS_NEGATE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SINGLE_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "ROUND": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "USE_DSP_CASCADES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_THROTTLE_SCHEME": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ARESETN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_A_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_A_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_B_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_B_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_CTRL_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_CTRL_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_TLAST_RESOLUTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_A_TDATA_WIDTH": [ { "value": "48", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_A_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_B_TDATA_WIDTH": [ { "value": "48", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_B_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_CTRL_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_CTRL_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_DOUT_TDATA_WIDTH": [ { "value": "80", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_DOUT_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintex7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7k410t" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "22" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../var_cal.gen/sources_1/ip/cmpy_18x18_mult" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_a_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_a_tdata": [ { "direction": "in", "size_left": "47", "size_right": "0", "driver_value": "0" } ],
+        "s_axis_b_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_b_tdata": [ { "direction": "in", "size_left": "47", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_dout_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
+        "m_axis_dout_tdata": [ { "direction": "out", "size_left": "79", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "M_AXIS_DOUT": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "10", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_dout_tdata" } ],
+            "TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ]
+          }
+        },
+        "aclk_intf": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CTRL:S_AXIS_B:S_AXIS_A:M_AXIS_DOUT", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "aresetn_intf": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclken_intf": {
+          "vlnv": "xilinx.com:signal:clockenable:1.0",
+          "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
+          }
+        },
+        "S_AXIS_A": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "6", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_a_tdata" } ],
+            "TVALID": [ { "physical_name": "s_axis_a_tvalid" } ]
+          }
+        },
+        "S_AXIS_B": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "6", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_b_tdata" } ],
+            "TVALID": [ { "physical_name": "s_axis_b_tvalid" } ]
+          }
+        }
+      }
+    }
+  }
+}

modules/xc7k410tffg900-2/var_cal/var_cal.srcs/sources_1/new/var_cal.v

@@ -0,0 +1,258 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 06/11/2023 02:41:47 PM
+// Design Name:
+// Module Name: var_cal
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+//   Revision 0.01 - File Created
+//   20230730-1427 - 修改输入位宽小于乘法器位宽时的处理，由补零变为符号位扩展；
+//     修改；修改累加和输出截位方式，依托原始数据位宽进行处理。
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module var_cal
+#(
+    parameter ACCUM_NUM = 16384,
+    parameter DATA_I_WIDTH = 30,
+    parameter DATA_O_WIDTH = 32,
+    parameter CMPY_I_WIDTH = 18
+)
+(
+    input clk                           ,
+    input rst                           ,
+
+    input cal_start                     ,
+    input cal_auto_en                   ,
+    output cal_busy                     ,
+
+    input din_valid                     ,
+    input [DATA_I_WIDTH-1 : 0] din_real ,
+    input [DATA_I_WIDTH-1 : 0] din_imag ,
+
+    output var_valid                    ,
+    output [DATA_O_WIDTH-1 : 0] var
+);
+
+integer i;
+
+localparam CMPY_P_WIDTH = 2*CMPY_I_WIDTH+1;
+localparam AXIS_CMPY_I_WIDTH = 8*((CMPY_I_WIDTH-1)/8+1)    ; // axis data width of input real/image data
+localparam AXIS_CMPY_P_WIDTH = 8*((CMPY_P_WIDTH-1)/8+1); // axis data width of cmpy output real/image data
+localparam CMPY_P_VALID_WIDTH = (DATA_I_WIDTH > CMPY_I_WIDTH) ? 2*CMPY_I_WIDTH : 2*DATA_I_WIDTH;
+
+
+localparam ACCUM_WIDTH = CMPY_P_VALID_WIDTH + $clog2(ACCUM_NUM);
+
+// status control
+reg cal_start_auto = 'b0;
+reg cal_start_d1 = 'b0;
+reg cal_start_d2 = 'b0;
+reg cal_busy_buf = 'b0;
+reg [$clog2(ACCUM_NUM)-1 : 0] cnt_accum = 'b0;
+reg last_data = 'b0;
+reg [6:0] last_data_d = 'b0; // 1 for register input, 6 for cmpy, 1 for register output
+
+assign cal_busy = cal_busy_buf;
+assign var_valid = last_data_d[6];
+
+always @(posedge clk) begin
+    if (rst) begin
+        cal_start_auto <= 'b0;
+    end
+    else begin
+        if (cal_auto_en) begin
+            if (~cal_busy_buf) begin
+                cal_start_auto <= ~cal_start_auto;
+            end
+            else begin
+                cal_start_auto <= cal_start_auto;
+            end
+        end
+        else begin
+            cal_start_auto <= 'b0;
+        end
+    end
+end
+
+always @(posedge clk) begin
+    cal_start_d1 <= cal_auto_en ? cal_start_auto : cal_start;
+    cal_start_d2 <= cal_start_d1;
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        cal_busy_buf <= 'b0;
+    end
+    else begin
+        if ((cal_start_d1 ^ cal_start_d2) && din_valid) begin
+            cal_busy_buf <= 1'b1;
+        end
+        else if (cnt_accum == ACCUM_NUM-1) begin
+            cal_busy_buf <= 'b0;
+        end
+        else begin
+            cal_busy_buf <= cal_busy_buf;
+        end
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        cnt_accum <= 'b0;
+    end
+    else begin
+        cnt_accum <= cal_busy ? (cnt_accum + 1'b1) : 'b0;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        last_data <= 'b0;
+    end
+    else begin
+        last_data <= (cnt_accum == ACCUM_NUM-1) ? 1'b1 : 1'b0;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        last_data_d[6:0] <= 'b0;
+    end
+    else begin
+        last_data_d[6:0] <= {last_data_d[5:0],last_data};
+    end
+end
+
+
+// cmpy
+reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_a_real = 'b0;
+reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_a_imag = 'b0;
+reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_b_real = 'b0;
+reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_b_imag = 'b0;
+wire [AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p_raw_real;
+wire [AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p_raw_imag;
+wire [CMPY_P_VALID_WIDTH-1 : 0] cmpy_p_real;
+wire [CMPY_P_VALID_WIDTH-1 : 0] cmpy_p_imag;
+
+if (CMPY_I_WIDTH > DATA_I_WIDTH) begin
+    // sign-bit extension to fit cmpy input data width
+    always @(posedge clk) begin
+        if (rst) begin
+            cmpy_a_real <= 'b0;
+            cmpy_a_imag <= 'b0;
+            cmpy_b_real <= 'b0;
+            cmpy_b_imag <= 'b0;
+        end
+        else begin
+            cmpy_a_real <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real};
+            cmpy_a_imag <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag};
+            cmpy_b_real <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real};
+            cmpy_b_imag <= (din_imag == {1'b1,{(DATA_I_WIDTH-1){1'b0}}}) ? {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH+1){1'b0}},{(DATA_I_WIDTH-1){1'b1}}} : -{{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag};
+        end
+    end
+end
+else begin
+    // truncate msb
+    always @(posedge clk) begin
+        if (rst) begin
+            cmpy_a_real <= 'b0;
+            cmpy_a_imag <= 'b0;
+            cmpy_b_real <= 'b0;
+            cmpy_b_imag <= 'b0;
+        end
+        else begin
+            cmpy_a_real <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
+            cmpy_a_imag <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
+            cmpy_b_real <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
+            cmpy_b_imag <= (din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH] == {1'b1,{(CMPY_I_WIDTH-1){1'b0}}}) ? {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH+1){1'b0}},{(CMPY_I_WIDTH-1){1'b1}}} : -{{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
+        end
+    end
+end
+
+// truncate valid bits
+assign cmpy_p_real = cmpy_p_raw_real[0 +: CMPY_P_VALID_WIDTH];
+assign cmpy_p_imag = cmpy_p_raw_imag[0 +: CMPY_P_VALID_WIDTH];
+
+
+wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_a;
+wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_b;
+wire [2*AXIS_CMPY_P_WIDTH-1:0] cmpy_p;
+wire cmpy_p_vld;
+
+assign cmpy_a = {cmpy_a_imag,cmpy_a_real};
+assign cmpy_b = {cmpy_b_imag,cmpy_b_real};
+assign {cmpy_p_raw_imag,cmpy_p_raw_real} = cmpy_p;
+
+cmpy_18x18_mult u_cmpy_18x18
+(
+    .aclk               (clk        ), // input wire aclk
+    .s_axis_a_tvalid    (cal_busy   ), // input wire s_axis_a_tvalid
+    .s_axis_a_tdata     (cmpy_a     ), // input wire [31 : 0] s_axis_a_tdata
+    .s_axis_b_tvalid    (cal_busy   ), // input wire s_axis_b_tvalid
+    .s_axis_b_tdata     (cmpy_b     ), // input wire [31 : 0] s_axis_b_tdata
+    .m_axis_dout_tvalid (cmpy_p_vld ), // output wire m_axis_dout_tvalid
+    .m_axis_dout_tdata  (cmpy_p     )  // output wire [63 : 0] m_axis_dout_tdata
+);
+
+
+// accumulation
+reg [ACCUM_WIDTH-1 : 0] accum = 'b0;
+reg [DATA_O_WIDTH-1 : 0] var_buf = 'b0;
+
+assign var = var_buf;
+
+always @(posedge clk) begin
+    if (rst) begin
+        accum <= 'b0;
+    end
+    else begin
+        if (cmpy_p_vld) begin
+            accum <= accum + cmpy_p_real;
+        end
+        else begin
+            accum <= 'b0;
+        end
+    end
+end
+
+if (DATA_O_WIDTH > ACCUM_WIDTH) begin
+    // sign-bit extension to fit output data width
+    always @(posedge clk) begin
+        if (rst) begin
+            var_buf <= 'b0;
+        end
+        else if (last_data_d[5]) begin
+            var_buf <= {{(DATA_O_WIDTH-ACCUM_WIDTH){accum[ACCUM_WIDTH-1]}},accum};
+        end
+    end
+end
+else begin
+    // truncate msb
+    always @(posedge clk) begin
+        if (rst) begin
+            var_buf <= 'b0;
+        end
+        else if (last_data_d[5]) begin
+            var_buf <= accum[ACCUM_WIDTH-1 -: DATA_O_WIDTH];
+        end
+    end
+end
+
+endmodule

modules/xc7k410tffg900-2/var_cal/var_cal.xpr

@@ -0,0 +1,271 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!--                                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
+<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+
+<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/Workspace/vivado/vivado_pub/modules/xc7k410tffg900-2/var_cal/var_cal.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="50c9ae21b7244457977e96017e983c18"/>
+    <Option Name="Part" Val="xc7k410tffg900-2"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
+    <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
+    <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
+    <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
+    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
+    <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="SimCompileState" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="1"/>
+    <Option Name="WTModelSimExportSim" Val="1"/>
+    <Option Name="WTQuestaExportSim" Val="1"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="1"/>
+    <Option Name="WTRivieraExportSim" Val="1"/>
+    <Option Name="WTActivehdlExportSim" Val="1"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+  </Configuration>
+  <FileSets Version="1" Minor="32">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/new/var_cal.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="var_cal"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <File Path="$PSRCDIR/sim_1/new/tb_var_cal.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="var_cal"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="cmpy_18x18_mult" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_18x18_mult" RelGenDir="$PGENDIR/cmpy_18x18_mult">
+      <File Path="$PSRCDIR/sources_1/ip/cmpy_18x18_mult/cmpy_18x18_mult.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="cmpy_18x18_mult"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="21">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="cmpy_18x18_mult_synth_1" Type="Ft3:Synth" SrcSet="cmpy_18x18_mult" Part="xc7k410tffg900-2" ConstrsSet="cmpy_18x18_mult" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/cmpy_18x18_mult_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_18x18_mult_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_18x18_mult_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="cmpy_18x18_mult_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="cmpy_18x18_mult" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="cmpy_18x18_mult_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_18x18_mult_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_18x18_mult_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board/>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/ip/ad9361_fifo/ad9361_fifo.xci

@@ -0,0 +1,479 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "ad9361_fifo",
+    "component_reference": "xilinx.com:ip:fifo_generator:13.2",
+    "ip_revision": "9",
+    "gen_directory": "../../../../ad9361_mapping.gen/sources_1/ip/ad9361_fifo",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "ad9361_fifo", "resolve_type": "user", "usage": "all" } ],
+        "Fifo_Implementation": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "synchronization_stages": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
+        "asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Data_Width": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Input_Depth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Output_Data_Width": [ { "value": "12", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Depth": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Type": [ { "value": "Asynchronous_Reset", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Flags_Reset_Value": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
+        "Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Data_Count_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Write_Data_Count_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Read_Data_Count_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Full_Threshold_Assert_Value": [ { "value": "13", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Negate_Value": [ { "value": "12", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
+        "HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
+        "ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
+        "TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
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+        "C_REG_SLICE_MODE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z100" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "9" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../ad9361_mapping.gen/sources_1/ip/ad9361_fifo" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "rst": [ { "direction": "in", "driver_value": "0" } ],
+        "wr_clk": [ { "direction": "in", "driver_value": "0" } ],
+        "rd_clk": [ { "direction": "in", "driver_value": "0" } ],
+        "din": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
+        "wr_en": [ { "direction": "in", "driver_value": "0" } ],
+        "rd_en": [ { "direction": "in", "driver_value": "0" } ],
+        "dout": [ { "direction": "out", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
+        "full": [ { "direction": "out", "driver_value": "0x0" } ],
+        "empty": [ { "direction": "out", "driver_value": "0x1" } ]
+      },
+      "interfaces": {
+        "write_clk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "wr_clk" } ]
+          }
+        },
+        "read_clk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "rd_clk" } ]
+          }
+        },
+        "FIFO_WRITE": {
+          "vlnv": "xilinx.com:interface:fifo_write:1.0",
+          "abstraction_type": "xilinx.com:interface:fifo_write_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "FULL": [ { "physical_name": "full" } ],
+            "WR_DATA": [ { "physical_name": "din" } ],
+            "WR_EN": [ { "physical_name": "wr_en" } ]
+          }
+        },
+        "FIFO_READ": {
+          "vlnv": "xilinx.com:interface:fifo_read:1.0",
+          "abstraction_type": "xilinx.com:interface:fifo_read_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "EMPTY": [ { "physical_name": "empty" } ],
+            "RD_DATA": [ { "physical_name": "dout" } ],
+            "RD_EN": [ { "physical_name": "rd_en" } ]
+          }
+        }
+      }
+    }
+  }
+}

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_dual.v

@@ -0,0 +1,196 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/07/01 17:37:27
+// Last Modified Date: 2023/03/06 11:26
+// Design Name:
+// Module Name: ad9361_rx_map_cmos_dual
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ad9361_rx_map_cmos_dual
+(
+    input           clk_2x_in       ,
+    input           clk_in_rst      ,
+
+    input           rx_data_clk     , // sync to output data
+    input           rx_data_clk_rst ,
+
+    input           rx_fifo_rst     ,  // async fifo reset
+
+    input           rx_frame        ,
+    input   [11:0]  rx_data         ,
+
+    output  [11:0]  rx_ch1_i        ,
+    output  [11:0]  rx_ch1_q        ,
+    output  [11:0]  rx_ch2_i        ,
+    output  [11:0]  rx_ch2_q
+);
+
+genvar          m;
+
+// rx data
+wire [11:0] rx_data_i, rx_data_q;
+
+generate
+for (m=0; m<12; m=m+1) begin : rx_data_iddr
+
+IDDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .INIT_Q1        (1'b0           ),
+    .INIT_Q2        (1'b0           ),
+    .SRTYPE         ("ASYNC"        )
+) i_rx_data_iddr (
+    .CE             (1'b1           ),
+    .R              (1'b0           ),
+    .S              (1'b0           ),
+    .C              (clk_2x_in      ),
+    .D              (rx_data[m]     ),
+    .Q1             (rx_data_q[m]   ),
+    .Q2             (rx_data_i[m]   )
+);
+
+end
+endgenerate
+
+// rx frame
+wire        rx_frame_i;
+wire        rx_frame_q;
+
+IDDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .INIT_Q1        (1'b0           ),
+    .INIT_Q2        (1'b0           ),
+    .SRTYPE         ("ASYNC"        )
+) i_rx_frame_iddr (
+    .CE             (1'b1           ),
+    .R              (1'b0           ),
+    .S              (1'b0           ),
+    .C              (clk_2x_in      ),
+    .D              (rx_frame       ),
+    .Q1             (rx_frame_q     ),
+    .Q2             (rx_frame_i     )
+);
+
+// divide rx_data to dual channel
+reg     [11:0]  rx1_data_i = 'b0;
+reg     [11:0]  rx1_data_q = 'b0;
+reg     [11:0]  rx2_data_i = 'b0;
+reg     [11:0]  rx2_data_q = 'b0;
+
+wire            rx_fifo_wr_en;
+reg             rx_fifo_rd_en = 'b0;
+
+wire            rx_fifo_empty_1;
+wire            rx_fifo_empty_2;
+wire            rx_fifo_empty_3;
+wire            rx_fifo_empty_4;
+
+assign rx_fifo_wr_en = rx_frame_i; // align data & write enable
+
+always @ (posedge clk_2x_in) begin
+    if (clk_in_rst) begin
+        rx1_data_i <= 'b0;
+        rx2_data_i <= 'b0;
+    end
+    else if(rx_frame_i) begin
+        rx1_data_i <= rx_data_i;
+    end
+    else begin
+        rx2_data_i <= rx_data_i;
+    end
+end
+
+always @ (posedge clk_2x_in) begin
+    if (clk_in_rst) begin
+        rx1_data_q <= 'b0;
+        rx2_data_q <= 'b0;
+    end
+    else if(rx_frame_q) begin
+        rx1_data_q <= rx_data_q;
+    end
+    else begin
+        rx2_data_q <= rx_data_q;
+    end
+end
+
+always @(posedge rx_data_clk) begin
+    if (rx_data_clk_rst) begin
+        rx_fifo_rd_en <= 'b0;
+    end
+    else begin
+        rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4};
+    end
+end
+
+ad9361_fifo u_rx_fifo_ch1_i
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_2x_in      ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx1_data_i     ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en  ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (rx_ch1_i       ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_1)  // output wire empty
+);
+
+ad9361_fifo u_rx_fifo_ch1_q
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_2x_in      ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx1_data_q     ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en  ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (rx_ch1_q       ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_2)  // output wire empty
+);
+
+ad9361_fifo u_rx_fifo_ch2_i
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_2x_in      ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx2_data_i     ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en  ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (rx_ch2_i       ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_3)  // output wire empty
+);
+
+ad9361_fifo u_rx_fifo_ch2_q
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_2x_in      ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx2_data_q     ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en  ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (rx_ch2_q       ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_4)  // output wire empty
+);
+
+endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_single.v

@@ -0,0 +1,124 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/07/01 17:37:27
+// Last Modified Date: 2023/03/03 13:01
+// Design Name:
+// Module Name: ad9361_rx_map_cmos_single
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ad9361_rx_map_cmos_single
+(
+    input           clk_in          ,
+    input           clk_in_rst      ,
+
+    input           rx_data_clk     ,
+    input           rx_data_clk_rst ,
+
+    input           rx_fifo_rst     ,
+
+    input           rx_frame        ,
+    input   [11:0]  rx_data         ,
+
+    output  [11:0]  rx_data_i       ,
+    output  [11:0]  rx_data_q
+);
+
+genvar          m;
+
+// rx data
+wire [11:0] rx_raw_i, rx_raw_q;
+
+generate
+for (m=0; m<12; m=m+1) begin : rx_data_iddr
+
+IDDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .INIT_Q1        (1'b0           ),
+    .INIT_Q2        (1'b0           ),
+    .SRTYPE         ("ASYNC"        )
+) i_rx_data_iddr (
+    .CE             (1'b1           ),
+    .R              (1'b0           ),
+    .S              (1'b0           ),
+    .C              (clk_in         ),
+    .D              (rx_data[m]     ),
+    .Q1             (rx_raw_q[m]    ),
+    .Q2             (rx_raw_i[m]    )
+);
+
+end
+endgenerate
+
+
+// divide rx_data to dual channel
+reg             rx_fifo_wr_en = 1'b0;
+reg             rx_fifo_rd_en = 'b0;
+
+wire            rx_fifo_empty_1;
+wire            rx_fifo_empty_2;
+
+always @(posedge clk_in) begin
+    if (clk_in_rst) begin
+        rx_fifo_wr_en <= 1'b0;
+    end
+    else begin
+        rx_fifo_wr_en <= 1'b1;
+    end
+end
+
+always @(posedge rx_data_clk) begin
+    if (rx_data_clk_rst) begin
+        rx_fifo_rd_en <= 'b0;
+    end
+    else begin
+        rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2};
+    end
+end
+
+ad9361_fifo u_rx_fifo_i
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_in         ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx_raw_i       ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en  ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (rx_data_i      ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_1)  // output wire empty
+);
+
+ad9361_fifo u_rx_fifo_q
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_in         ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx_raw_q       ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en  ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (rx_data_q      ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_2)  // output wire empty
+);
+
+endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_dual.v

@@ -0,0 +1,277 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/07/01 17:37:27
+// Last Modified Date: 2023/03/06 10:54
+// Design Name:
+// Module Name: ad9361_rx_mapping_dual
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ad9361_rx_map_lvds_dual
+(
+    input           clk_4x_in       , // sync to input data
+    input           clk_in_rst      ,
+
+    input           rx_data_clk     , // sync to output data
+    input           rx_data_clk_rst ,
+
+    input           rx_fifo_rst     , // async fifo reset
+
+    input           rx_frame_p      ,
+    input           rx_frame_n      ,
+    input   [ 5:0]  rx_data_p       , // data from ad9361 p1 port
+    input   [ 5:0]  rx_data_n       ,
+
+    output  [11:0]  rx_ch1_i        ,
+    output  [11:0]  rx_ch1_q        ,
+    output  [11:0]  rx_ch2_i        ,
+    output  [11:0]  rx_ch2_q
+);
+
+genvar          m;
+
+// rx data
+wire [5:0] rx_data;
+wire [5:0] rx_data_i, rx_data_q;
+
+generate
+for (m=0; m<6; m=m+1) begin : rx_data_iddr
+
+IBUFDS #(
+    .DIFF_TERM  ("TRUE"         )
+) u_ibufds_rx_data
+(
+    .I          (rx_data_p[m]   ),
+    .IB         (rx_data_n[m]   ),
+    .O          (rx_data[m]     )
+);
+
+IDDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .INIT_Q1        (1'b0           ),
+    .INIT_Q2        (1'b0           ),
+    .SRTYPE         ("ASYNC"        )
+) u_rx_data_iddr (
+    .CE             (1'b1           ), // clock enable
+    .R              (1'b0           ), // iddr reset
+    .S              (1'b0           ), // iddr set
+    .C              (clk_4x_in      ), // iddr clock
+    .D              (rx_data[m]     ), // ddr data
+    .Q1             (rx_data_q[m]   ), // sdr data at rising edge
+    .Q2             (rx_data_i[m]   )  // sdr data at falling edge
+);
+
+end
+endgenerate
+
+// rx frame
+wire            rx_frame;
+wire            rx_frame_i;
+wire            rx_frame_q;
+
+IBUFDS #(
+    .DIFF_TERM  ("TRUE"     )
+) u_ibufds_rx_frame
+(
+    .I          (rx_frame_p ),
+    .IB         (rx_frame_n ),
+    .O          (rx_frame   )
+);
+
+IDDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .INIT_Q1        (1'b0           ),
+    .INIT_Q2        (1'b0           ),
+    .SRTYPE         ("ASYNC"        )
+) u_rx_frame_iddr (
+    .CE             (1'b1           ), // clock enable
+    .R              (1'b0           ), // iddr reset
+    .S              (1'b0           ), // iddr set
+    .C              (clk_4x_in      ), // iddr clock
+    .D              (rx_frame       ), // ddr data
+    .Q1             (rx_frame_q     ), // sdr data at rising edge
+    .Q2             (rx_frame_i     )  // sdr data at falling edge
+);
+
+// unpack rx frame & data
+reg             rx_frame_i_d1   = 'b0;
+reg     [ 5:0]  rx_data_i_d1    = 'b0;
+reg     [ 5:0]  rx_data_q_d1    = 'b0;
+reg             rx_flag         = 'b0; // rx frame rising edge indicator
+reg     [ 1:0]  rx_cnt          = 'b0; // unpack stage counter
+
+always @(posedge clk_4x_in) begin
+    // wait for [rx_flag]
+    rx_frame_i_d1 <= rx_frame_i;
+     rx_data_i_d1 <=  rx_data_i;
+     rx_data_q_d1 <=  rx_data_q;
+end
+
+always @(posedge clk_4x_in) begin
+    if (clk_in_rst) begin
+        rx_flag <= 'b0;
+    end
+    else if (~rx_frame_i_d1 & rx_frame_i) begin
+        // assert when rising edge of rx frame is detected
+        rx_flag <= 'b1;
+    end
+    else begin
+        rx_flag <= rx_flag;
+    end
+end
+
+always @(posedge clk_4x_in) begin
+    if (clk_in_rst) begin
+        rx_cnt <= 'b0;
+    end
+    else begin
+        rx_cnt <= (rx_flag) ? rx_cnt + 1'b1 : rx_cnt;
+    end
+end
+
+reg     [11:0]  rx1_data_i = 'b0;
+reg     [11:0]  rx1_data_q = 'b0;
+reg     [11:0]  rx2_data_i = 'b0;
+reg     [11:0]  rx2_data_q = 'b0;
+
+always @(posedge clk_4x_in) begin
+    if (clk_in_rst) begin
+        rx1_data_i <= 'b0;
+        rx1_data_q <= 'b0;
+        rx2_data_i <= 'b0;
+        rx2_data_q <= 'b0;
+    end
+    else begin
+        case (rx_cnt)
+            3'd0: begin
+                // 1st clock cycle: upper 6-bit of rx ch1 inphase/quadrature data
+                rx1_data_i[11:6] <= rx_data_i_d1;
+                rx1_data_q[11:6] <= rx_data_q_d1;
+            end
+            3'd1: begin
+                // 2nd clock cycle: lower 6-bit of rx ch1 inphase/quadrature data
+                rx1_data_i[ 5:0] <= rx_data_i_d1;
+                rx1_data_q[ 5:0] <= rx_data_q_d1;
+            end
+            3'd2: begin
+                // 3rd clock cycle: upper 6-bit of rx ch2 inphase/quadrature data
+                rx2_data_i[11:6] <= rx_data_i_d1;
+                rx2_data_q[11:6] <= rx_data_q_d1;
+            end
+            3'd3: begin
+                // 4th clock cycle: lower 6-bit of rx ch2 inphase/quadrature data
+                rx2_data_i[ 5:0] <= rx_data_i_d1;
+                rx2_data_q[ 5:0] <= rx_data_q_d1;
+            end
+            default: begin
+                rx1_data_i <= 'b0;
+                rx1_data_q <= 'b0;
+                rx2_data_i <= 'b0;
+                rx2_data_q <= 'b0;
+            end
+        endcase
+    end
+end
+
+// write fifo when rx1/2_data_i/q are all prepared with 192MHz clock
+// read fifo at every clock cycle with 48MHz clock
+reg fifo_wr_en = 'b0;
+reg fifo_rd_en = 'b0;
+wire rx_fifo_empty_1;
+wire rx_fifo_empty_2;
+wire rx_fifo_empty_3;
+wire rx_fifo_empty_4;
+
+always @(posedge clk_4x_in) begin
+    if (clk_in_rst) begin
+        fifo_wr_en <= 'b0;
+    end
+    else if (rx_cnt == 2'd3) begin
+        fifo_wr_en <= 1'b1;
+    end
+    else begin
+        fifo_wr_en <= 'b0;
+    end
+end
+
+always @(posedge rx_data_clk) begin
+    if (rx_data_clk_rst) begin
+        fifo_rd_en <= 1'b0;
+    end
+    else begin
+        fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4};
+    end
+end
+
+ad9361_fifo u_rx_fifo_ch1_i
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_4x_in      ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx1_data_i     ), // input wire [11 : 0] din
+    .wr_en      (fifo_wr_en     ), // input wire wr_en
+    .rd_en      (fifo_rd_en     ), // input wire rd_en
+    .dout       (rx_ch1_i       ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_1)  // output wire empty
+);
+
+ad9361_fifo u_rx_fifo_ch1_q
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_4x_in      ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx1_data_q     ), // input wire [11 : 0] din
+    .wr_en      (fifo_wr_en     ), // input wire wr_en
+    .rd_en      (fifo_rd_en     ), // input wire rd_en
+    .dout       (rx_ch1_q       ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_2)  // output wire empty
+);
+
+ad9361_fifo u_rx_fifo_ch2_i
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_4x_in      ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx2_data_i     ), // input wire [11 : 0] din
+    .wr_en      (fifo_wr_en     ), // input wire wr_en
+    .rd_en      (fifo_rd_en     ), // input wire rd_en
+    .dout       (rx_ch2_i       ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_3)  // output wire empty
+);
+
+ad9361_fifo u_rx_fifo_ch2_q
+(
+    .rst        (rx_fifo_rst    ), // input wire rst
+    .wr_clk     (clk_4x_in      ), // input wire wr_clk
+    .rd_clk     (rx_data_clk    ), // input wire rd_clk
+    .din        (rx2_data_q     ), // input wire [11 : 0] din
+    .wr_en      (fifo_wr_en     ), // input wire wr_en
+    .rd_en      (fifo_rd_en     ), // input wire rd_en
+    .dout       (rx_ch2_q       ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_4)  // output wire empty
+);
+
+endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v

@@ -0,0 +1,183 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/07/01 16:39:19
+// Last Modified Date: 2023/03/06 11:45
+// Design Name:
+// Module Name: ad9361_tx_map_cmos_dual
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ad9361_tx_map_cmos_dual
+(
+    input           clk_2x_in       ,
+    input           clk_in_rst      ,
+
+    input           tx_data_clk     ,
+    input           tx_data_clk_rst ,
+
+    input   [11:0]  tx_ch1_i        ,
+    input   [11:0]  tx_ch1_q        ,
+    input   [11:0]  tx_ch2_i        ,
+    input   [11:0]  tx_ch2_q        ,
+
+    output          clk_out         ,
+    output          tx_frame        ,
+    output  [11:0]  tx_data
+);
+
+genvar m;
+
+// input data fifo
+reg rx_fifo_rd_en = 'b0;
+wire [11:0] tx_fifo_ch1_i;
+wire [11:0] tx_fifo_ch1_q;
+wire [11:0] tx_fifo_ch2_i;
+wire [11:0] tx_fifo_ch2_q;
+
+always @(posedge clk_2x_in) begin
+    if (clk_in_rst) begin
+        rx_fifo_rd_en <= 'b0;
+    end
+    else begin
+        rx_fifo_rd_en <= ~rx_fifo_rd_en;
+    end
+end
+
+ad9361_fifo u_tx_fifo_ch1_i
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_2x_in      ), // input wire rd_clk
+    .din        (tx_ch1_i       ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_ch1_i  ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+ad9361_fifo u_tx_fifo_ch1_q
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_2x_in      ), // input wire rd_clk
+    .din        (tx_ch1_q       ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_ch1_q  ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+ad9361_fifo u_tx_fifo_ch2_i
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_2x_in      ), // input wire rd_clk
+    .din        (tx_ch2_i       ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_ch2_i  ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+ad9361_fifo u_tx_fifo_ch2_q
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_2x_in      ), // input wire rd_clk
+    .din        (tx_ch2_q       ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_ch2_q  ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+// frame and data control
+reg tx_frame_i = 'b0;
+reg tx_frame_q = 'b0;
+reg [11:0] tx_data_i = 'b0;
+reg [11:0] tx_data_q = 'b0;
+
+always @(posedge clk_2x_in) begin
+    if (clk_in_rst) begin
+        tx_frame_i <= 'b0;
+        tx_frame_q <= 'b0;
+        tx_data_i <= 'b0;
+        tx_data_q <= 'b0;
+    end
+    else if (rx_fifo_rd_en == 1'b0) begin
+        tx_frame_i <= 1'b1;
+        tx_frame_q <= 1'b1;
+        tx_data_i <= tx_fifo_ch1_i;
+        tx_data_q <= tx_fifo_ch1_q;
+    end
+    else begin
+        tx_frame_i <= 1'b0;
+        tx_frame_q <= 1'b0;
+        tx_data_i <= tx_fifo_ch2_i;
+        tx_data_q <= tx_fifo_ch2_q;
+    end
+end
+
+// output clock to port
+assign clk_out = clk_2x_in;
+
+// output tx frame to port
+ODDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .INIT           (1'b0           ),
+    .SRTYPE         ("ASYNC"        )
+) u_tx_frame_oddr (
+    .CE             (1'b1           ),
+    .R              (1'b0           ),
+    .S              (1'b0           ),
+    .C              (clk_2x_in      ),
+    .D1             (tx_frame_i     ),
+    .D2             (tx_frame_q     ),
+    .Q              (tx_frame       )
+);
+
+// output tx data to port
+generate
+for (m=0; m<12; m=m+1) begin: tx_data_oddr
+
+ODDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"   ),
+    .INIT           (1'b0          ),
+    .SRTYPE         ("ASYNC"       )
+) u_tx_data_oddr  (
+    .CE             (1'b1          ),
+    .R              (1'b0          ),
+    .S              (1'b0          ),
+    .C              (clk_2x_in     ),
+    .D1             (tx_data_i[m]  ),
+    .D2             (tx_data_q[m]  ),
+    .Q              (tx_data[m]    )
+);
+
+end
+endgenerate
+
+endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_single.v

@@ -0,0 +1,119 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/07/01 16:39:19
+// Design Name:
+// Module Name: ad9361_tx_mapping_single
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ad9361_tx_map_cmos_single
+(
+    input           clk_in          ,
+    input           clk_in_rst      ,
+
+    input           tx_data_clk     ,
+    input           tx_data_clk_rst ,
+
+    input   [11:0]  tx_data_i       ,
+    input   [11:0]  tx_data_q       ,
+
+    output          clk_out         ,
+    output          tx_frame        ,
+    output  [11:0]  tx_data
+);
+
+genvar m;
+
+// inout data fifo
+wire [11:0] tx_fifo_i;
+wire [11:0] tx_fifo_q;
+
+ad9361_fifo u_tx_fifo_i
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_in         ), // input wire rd_clk
+    .din        (tx_data_i      ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (1'b1           ), // input wire rd_en
+    .dout       (tx_fifo_i      ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+ad9361_fifo u_tx_fifo_q
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_in         ), // input wire rd_clk
+    .din        (tx_data_q      ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (1'b1           ), // input wire rd_en
+    .dout       (tx_fifo_q      ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+// frame and data control
+assign tx_frame_i = 1'b1;
+assign tx_frame_q = 1'b0;
+
+// output clock to port
+assign clk_out = clk_in;
+
+// output tx frame to port
+ODDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .INIT           (1'b0           ),
+    .SRTYPE         ("ASYNC"        )
+) u_tx_frame_oddr (
+    .CE             (1'b1           ),
+    .R              (1'b0           ),
+    .S              (1'b0           ),
+    .C              (clk_in         ),
+    .D1             (tx_frame_i     ),
+    .D2             (tx_frame_q     ),
+    .Q              (tx_frame       )
+);
+
+// output tx data to port
+generate
+for (m=0; m<12; m=m+1) begin: tx_data_oddr
+
+ODDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"   ),
+    .INIT           (1'b0          ),
+    .SRTYPE         ("ASYNC"       )
+) u_tx_data_oddr  (
+    .CE             (1'b1          ),
+    .R              (1'b0          ),
+    .S              (1'b0          ),
+    .C              (clk_in        ),
+    .D1             (tx_fifo_i[m]  ),
+    .D2             (tx_fifo_q[m]  ),
+    .Q              (tx_data[m]    )
+);
+
+end
+endgenerate
+
+endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_dual.v

@@ -0,0 +1,246 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2023/03/05 23:21:27
+// Last Modified Date: 2023/03/06 11:01
+// Design Name:
+// Module Name: ad9361_tx_map_lvds_dual
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ad9361_tx_map_lvds_dual
+(
+    input           clk_4x_in       ,
+    input           clk_in_rst      ,
+
+    input           tx_data_clk     ,
+    input           tx_data_clk_rst ,
+
+    input   [11:0]  tx_ch1_i        ,
+    input   [11:0]  tx_ch1_q        ,
+    input   [11:0]  tx_ch2_i        ,
+    input   [11:0]  tx_ch2_q        ,
+
+    output          clk_out_p       ,
+    output          clk_out_n       ,
+    output          tx_frame_p      ,
+    output          tx_frame_n      ,
+    output  [ 5:0]  tx_data_p       ,
+    output  [ 5:0]  tx_data_n
+);
+
+genvar m;
+
+// input data fifo
+reg [1:0] tx_control_cnt = 'b0;
+reg rx_fifo_rd_en = 'b0;
+wire [11:0] tx_fifo_ch1_i;
+wire [11:0] tx_fifo_ch1_q;
+wire [11:0] tx_fifo_ch2_i;
+wire [11:0] tx_fifo_ch2_q;
+
+always @(posedge clk_4x_in) begin
+    if (clk_in_rst) begin
+        tx_control_cnt <= 'b0;
+    end
+    else begin
+        tx_control_cnt <= tx_control_cnt + 1'b1;
+    end
+end
+
+always @(posedge clk_4x_in) begin
+    if (clk_in_rst) begin
+        rx_fifo_rd_en <= 'b0;
+    end
+    else if (tx_control_cnt == 2'd2) begin
+        rx_fifo_rd_en <= 1'b1;
+    end
+    else begin
+        rx_fifo_rd_en <= 'b0;
+    end
+end
+
+ad9361_fifo u_tx_fifo_ch1_i
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_4x_in      ), // input wire rd_clk
+    .din        (tx_ch1_i       ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_ch1_i  ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+ad9361_fifo u_tx_fifo_ch1_q
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_4x_in      ), // input wire rd_clk
+    .din        (tx_ch1_q       ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_ch1_q  ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+ad9361_fifo u_tx_fifo_ch2_i
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_4x_in      ), // input wire rd_clk
+    .din        (tx_ch2_i       ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_ch2_i  ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+ad9361_fifo u_tx_fifo_ch2_q
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_4x_in      ), // input wire rd_clk
+    .din        (tx_ch2_q       ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_ch2_q  ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (               )  // output wire empty
+);
+
+
+// frame and data control
+reg tx_frame_r = 'b0; // rising edge data
+reg tx_frame_f = 'b0; // falling edge data
+reg [5:0] tx_data_r = 'b0;
+reg [5:0] tx_data_f = 'b0;
+
+always @(posedge clk_4x_in) begin
+    if (clk_in_rst) begin
+        tx_frame_r <= 'b0;
+        tx_frame_f <= 'b0;
+        tx_data_r <= 'b0;
+        tx_data_f <= 'b0;
+    end
+    else begin
+        case (tx_control_cnt)
+            2'd0: begin
+                tx_frame_r <= 1'b1;
+                tx_frame_f <= 1'b1;
+                tx_data_r <= tx_fifo_ch1_i[11: 6];
+                tx_data_f <= tx_fifo_ch1_q[11: 6];
+            end
+            2'd1: begin
+                tx_frame_r <= 1'b1;
+                tx_frame_f <= 1'b1;
+                tx_data_r <= tx_fifo_ch1_i[5:0];
+                tx_data_f <= tx_fifo_ch1_q[5:0];
+            end
+            2'd2: begin
+                tx_frame_r <= 1'b0;
+                tx_frame_f <= 1'b0;
+                tx_data_r <= tx_fifo_ch2_i[11:6];
+                tx_data_f <= tx_fifo_ch2_q[11:6];
+            end
+            2'd3: begin
+                tx_frame_r <= 1'b0;
+                tx_frame_f <= 1'b0;
+                tx_data_r <= tx_fifo_ch2_i[5:0];
+                tx_data_f <= tx_fifo_ch2_q[5:0];
+            end
+            default: begin
+                tx_frame_r <= 'b0;
+                tx_frame_f <= 'b0;
+                tx_data_r <= 'b0;
+                tx_data_f <= 'b0;
+            end
+        endcase
+    end
+end
+
+// output clock to port
+wire clk_out;
+assign clk_out = clk_4x_in;
+
+OBUFDS u_obufds_clk_out
+(
+    .I  (clk_out    ),
+    .O  (clk_out_p  ),
+    .OB (clk_out_n  )
+);
+
+// output tx frame to port
+ODDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .INIT           (1'b0           ),
+    .SRTYPE         ("ASYNC"        )
+) u_tx_frame_oddr (
+    .CE             (1'b1           ),
+    .R              (1'b0           ),
+    .S              (1'b0           ),
+    .C              (clk_4x_in      ),
+    .D1             (tx_frame_r     ),
+    .D2             (tx_frame_f     ),
+    .Q              (tx_frame       )
+);
+
+OBUFDS u_obufds_tx_frame
+(
+    .I  (tx_frame   ),
+    .O  (tx_frame_p ),
+    .OB (tx_frame_n )
+);
+
+// output tx data to port
+wire [5:0] tx_data;
+
+generate
+for (m=0; m<6; m=m+1) begin: tx_data_oddr
+
+ODDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"   ),
+    .INIT           (1'b0          ),
+    .SRTYPE         ("ASYNC"       )
+) u_tx_data_oddr  (
+    .CE             (1'b1          ),
+    .R              (1'b0          ),
+    .S              (1'b0          ),
+    .C              (clk_4x_in     ),
+    .D1             (tx_data_r[m]  ),
+    .D2             (tx_data_f[m]  ),
+    .Q              (tx_data[m]    )
+);
+
+OBUFDS u_obufds_tx_data
+(
+    .I  (tx_data[m]     ),
+    .O  (tx_data_p[m]   ),
+    .OB (tx_data_n[m]   )
+);
+
+end
+endgenerate
+
+endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.xpr

@@ -0,0 +1,303 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!--                                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
+<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+
+<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/Workspace/vivado/vivado_pub/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="56c7290e44de4c80a4f826edd9352d43"/>
+    <Option Name="Part" Val="xc7z100ffg900-2"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
+    <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
+    <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
+    <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
+    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
+    <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="SimCompileState" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="1"/>
+    <Option Name="WTModelSimExportSim" Val="1"/>
+    <Option Name="WTQuestaExportSim" Val="1"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="1"/>
+    <Option Name="WTRivieraExportSim" Val="1"/>
+    <Option Name="WTActivehdlExportSim" Val="1"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+  </Configuration>
+  <FileSets Version="1" Minor="32">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_cmos_dual.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_lvds_dual.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_cmos_dual.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_lvds_dual.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_cmos_single.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_cmos_single.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="ad9361_rx_map_cmos_dual"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="ad9361_rx_map_cmos_dual"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="ad9361_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ad9361_fifo" RelGenDir="$PGENDIR/ad9361_fifo">
+      <File Path="$PSRCDIR/sources_1/ip/ad9361_fifo/ad9361_fifo.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="ad9361_fifo"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="21">
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+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="ad9361_fifo_synth_1" Type="Ft3:Synth" SrcSet="ad9361_fifo" Part="xc7z100ffg900-2" ConstrsSet="ad9361_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ad9361_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ad9361_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ad9361_fifo_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
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+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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+    </Run>
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+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
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+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
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+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
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+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
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+        <Step Id="write_bitstream"/>
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+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
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+      <Dashboard Name="default_dashboard">
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+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
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+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
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+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>

modules/xc7z100ffg900-2/tx_qpsk/tx_qpsk.srcs/sources_1/ip/cmpy_18x8/cmpy_18x8.xci

@@ -0,0 +1,212 @@
+{
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+        "C_M_AXIS_DOUT_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
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+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
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+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "22" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../tx_qpsk.gen/sources_1/ip/cmpy_18x8" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
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+      }
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+        "s_axis_b_tdata": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
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+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
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+            "TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ]
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+        },
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+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
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+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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+          },
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+          }
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+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
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+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
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+          "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
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+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
+          }
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+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
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+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
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+            "TDATA": [ { "physical_name": "s_axis_a_tdata" } ],
+            "TVALID": [ { "physical_name": "s_axis_a_tvalid" } ]
+          }
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+        "S_AXIS_B": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_b_tdata" } ],
+            "TVALID": [ { "physical_name": "s_axis_b_tvalid" } ]
+          }
+        }
+      }
+    }
+  }
+}

modules/xc7z100ffg900-2/tx_qpsk/tx_qpsk.srcs/sources_1/ip/coe/hrc_64_12_025.coe

@@ -0,0 +1,771 @@
+RADIX = 10;
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modules/xc7z100ffg900-2/tx_qpsk/tx_qpsk.srcs/sources_1/ip/coe/sweep_freq.coe

@@ -0,0 +1,258 @@
+MEMORY_INITIALIZATION_RADIX = 10;
+MEMORY_INITIALIZATION_VECTOR = 
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modules/xc7z100ffg900-2/tx_qpsk/tx_qpsk.srcs/sources_1/ip/dds_32b_8b/dds_32b_8b.xci

@@ -0,0 +1,355 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "dds_32b_8b",
+    "component_reference": "xilinx.com:ip:dds_compiler:6.0",
+    "ip_revision": "23",
+    "gen_directory": "../../../../tx_qpsk.gen/sources_1/ip/dds_32b_8b",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "dds_32b_8b", "resolve_type": "user", "usage": "all" } ],
+        "PartsPresent": [ { "value": "Phase_Generator_and_SIN_COS_LUT", "resolve_type": "user", "usage": "all" } ],
+        "DDS_Clock_Rate": [ { "value": "100", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Channels": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
+        "Mode_of_Operation": [ { "value": "Standard", "resolve_type": "user", "usage": "all" } ],
+        "Modulus": [ { "value": "9", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Parameter_Entry": [ { "value": "Hardware_Parameters", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Spurious_Free_Dynamic_Range": [ { "value": "45", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Frequency_Resolution": [ { "value": "0.4", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Noise_Shaping": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Phase_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Output_Width": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Phase_Increment": [ { "value": "Programmable", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "aresetn_intf": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclken_intf": {
+          "vlnv": "xilinx.com:signal:clockenable:1.0",
+          "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
+          }
+        },
+        "M_AXIS_DATA": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
+            "TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
+          }
+        },
+        "S_AXIS_CONFIG": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_config_tdata" } ],
+            "TVALID": [ { "physical_name": "s_axis_config_tvalid" } ]
+          }
+        }
+      }
+    }
+  }
+}

modules/xc7z100ffg900-2/tx_qpsk/tx_qpsk.srcs/sources_1/ip/hop_rom/hop_rom.xci

@@ -0,0 +1,252 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "hop_rom",
+    "component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
+    "ip_revision": "7",
+    "gen_directory": "../../../../tx_qpsk.gen/sources_1/ip/hop_rom",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "hop_rom", "resolve_type": "user", "usage": "all" } ],
+        "Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
+        "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Memory_Type": [ { "value": "Single_Port_ROM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_Byte_Write_Enable": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Byte_Size": [ { "value": "9", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ],
+        "Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Write_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Write_Depth_A": [ { "value": "256", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Read_Width_A": [ { "value": "32", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Write_Width_B": [ { "value": "32", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Read_Width_B": [ { "value": "32", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_B": [ { "value": "Always_Enabled", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Core": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Load_Init_File": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Coe_File": [ { "value": "../coe/sweep_freq.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_A_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Clock": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Enable_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ],
+        "MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ],
+        "CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ],
+        "EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
+        "C_XDEVICEFAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
+        "C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
+        "C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_32BIT_ADDRESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MEM_TYPE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BYTE_SIZE": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LOAD_INIT_FILE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INIT_FILE_NAME": [ { "value": "hop_rom.mif", "resolve_type": "generated", "usage": "all" } ],
+        "C_INIT_FILE": [ { "value": "hop_rom.mem", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
+        "C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_ENA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BYTE_WEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WEA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
+        "C_WRITE_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_DEPTH_A": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_DEPTH_A": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ADDRA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
+        "C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_ENB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BYTE_WEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WEB_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
+        "C_WRITE_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_DEPTH_B": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_DEPTH_B": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ADDRB_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
+        "C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COUNT_36K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_COUNT_18K_BRAM": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+        "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP     :     3.375199 mW", "resolve_type": "generated", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z100" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "7" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../tx_qpsk.gen/sources_1/ip/hop_rom" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
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+        "addra": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "douta": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
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+      "interfaces": {
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+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
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+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "RST.ARESETN": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "BRAM_PORTA": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addra" } ],
+            "CLK": [ { "physical_name": "clka" } ],
+            "DOUT": [ { "physical_name": "douta" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S_1": {
+          "address_blocks": {
+            "Mem0": {
+              "base_address": "0",
+              "range": "4096",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}

modules/xc7z100ffg900-2/tx_qpsk/tx_qpsk.srcs/sources_1/ip/hrc_64_12_025/hrc_64_12_025.xci

@@ -1,22 +1,22 @@
 {
   "schema": "xilinx.com:schema:json_instance:1.0",
   "ip_inst": {
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+    "xci_name": "hrc_64_12_025",
     "component_reference": "xilinx.com:ip:fir_compiler:7.2",
     "ip_revision": "20",
-    "gen_directory": "../../../../tx_qpsk_poly.gen/sources_1/ip/hrc_256_12_025",
+    "gen_directory": "../../../../tx_qpsk.gen/sources_1/ip/hrc_64_12_025",
     "parameters": {
       "component_parameters": {
-        "Component_Name": [ { "value": "hrc_256_12_025", "resolve_type": "user", "usage": "all" } ],
+        "Component_Name": [ { "value": "hrc_64_12_025", "resolve_type": "user", "usage": "all" } ],
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+        "Coefficient_File": [ { "value": "../coe/hrc_64_12_025.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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-        "Interpolation_Rate": [ { "value": "256", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Interpolation_Rate": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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@@ -64,7 +64,7 @@
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-        "ColumnConfig": [ { "value": "13", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "ColumnConfig": [ { "value": "7", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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@@ -90,18 +90,18 @@
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       },
       "model_parameters": {
-        "C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_XDEVICEFAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
         "C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
-        "C_COMPONENT_NAME": [ { "value": "hrc_256_12_025", "resolve_type": "generated", "usage": "all" } ],
+        "C_COMPONENT_NAME": [ { "value": "hrc_64_12_025", "resolve_type": "generated", "usage": "all" } ],
-        "C_COEF_FILE": [ { "value": "hrc_256_12_025.mif", "resolve_type": "generated", "usage": "all" } ],
+        "C_COEF_FILE": [ { "value": "hrc_64_12_025.mif", "resolve_type": "generated", "usage": "all" } ],
-        "C_COEF_FILE_LINES": [ { "value": "3328", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COEF_FILE_LINES": [ { "value": "448", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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-        "C_SYMMETRY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SYMMETRY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_NUM_FILTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_NUM_TAPS": [ { "value": "3073", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_TAPS": [ { "value": "769", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_NUM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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@@ -109,41 +109,41 @@
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-        "C_COL_CONFIG": [ { "value": "13", "resolve_type": "generated", "usage": "all" } ],
+        "C_COL_CONFIG": [ { "value": "7", "resolve_type": "generated", "usage": "all" } ],
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-        "C_DATA_PATH_WIDTHS": [ { "value": "2,2,2,2", "resolve_type": "generated", "usage": "all" } ],
+        "C_DATA_PATH_WIDTHS": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ],
         "C_DATA_IP_PATH_WIDTHS": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ],
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-        "C_COEF_PATH_WIDTHS": [ { "value": "16,16,16,16", "resolve_type": "generated", "usage": "all" } ],
+        "C_COEF_PATH_WIDTHS": [ { "value": "17", "resolve_type": "generated", "usage": "all" } ],
         "C_COEF_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_DATA_PATH_SRC": [ { "value": "0,0,0,0", "resolve_type": "generated", "usage": "all" } ],
+        "C_DATA_PATH_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
-        "C_COEF_PATH_SRC": [ { "value": "0,1,2,3", "resolve_type": "generated", "usage": "all" } ],
+        "C_COEF_PATH_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
-        "C_PX_PATH_SRC": [ { "value": "0,1,2,3", "resolve_type": "generated", "usage": "all" } ],
+        "C_PX_PATH_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
-        "C_DATA_PATH_SIGN": [ { "value": "0,0,0,0", "resolve_type": "generated", "usage": "all" } ],
+        "C_DATA_PATH_SIGN": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
-        "C_COEF_PATH_SIGN": [ { "value": "0,0,0,0", "resolve_type": "generated", "usage": "all" } ],
+        "C_COEF_PATH_SIGN": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
-        "C_ACCUM_PATH_WIDTHS": [ { "value": "18,18,18,18", "resolve_type": "generated", "usage": "all" } ],
+        "C_ACCUM_PATH_WIDTHS": [ { "value": "19", "resolve_type": "generated", "usage": "all" } ],
         "C_OUTPUT_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_OUTPUT_PATH_WIDTHS": [ { "value": "18,18,18,18", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTPUT_PATH_WIDTHS": [ { "value": "18", "resolve_type": "generated", "usage": "all" } ],
-        "C_ACCUM_OP_PATH_WIDTHS": [ { "value": "18,18,18,18", "resolve_type": "generated", "usage": "all" } ],
+        "C_ACCUM_OP_PATH_WIDTHS": [ { "value": "18", "resolve_type": "generated", "usage": "all" } ],
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-        "C_DATA_PATH_PSAMP_SRC": [ { "value": "-0;-0;-0;-0", "resolve_type": "generated", "usage": "all" } ],
+        "C_DATA_PATH_PSAMP_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
-        "C_OP_PATH_PSAMP_SRC": [ { "value": "-0;-0;-0;-0", "resolve_type": "generated", "usage": "all" } ],
+        "C_OP_PATH_PSAMP_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
-        "C_NUM_MADDS": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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-        "C_OPT_MADDS": [ { "value": "none;none;none;none", "resolve_type": "generated", "usage": "all" } ],
+        "C_OPT_MADDS": [ { "value": "none", "resolve_type": "generated", "usage": "all" } ],
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-        "C_OPBUFF_MEMTYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPBUFF_MEMTYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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-        "C_MEM_ARRANGEMENT": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MEM_ARRANGEMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_DATA_MEM_PACKING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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-        "C_LATENCY": [ { "value": "19", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LATENCY": [ { "value": "17", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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         "C_DATA_HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -153,7 +153,7 @@
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         "C_M_DATA_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_M_DATA_TDATA_WIDTH": [ { "value": "96", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_TDATA_WIDTH": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_M_DATA_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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         "C_CONFIG_SYNC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -162,23 +162,23 @@
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       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "ARCHITECTURE": [ { "value": "zynq" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu48dr" } ],
+        "DEVICE": [ { "value": "xc7z100" } ],
-        "PACKAGE": [ { "value": "fsvg1517" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
         "SPEEDGRADE": [ { "value": "-2" } ],
         "STATIC_POWER": [ { "value": "" } ],
-        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
       },
       "runtime_parameters": {
         "IPCONTEXT": [ { "value": "IP_Flow" } ],
         "IPREVISION": [ { "value": "20" } ],
         "MANAGED": [ { "value": "TRUE" } ],
-        "OUTPUTDIR": [ { "value": "../../../../tx_qpsk_poly.gen/sources_1/ip/hrc_256_12_025" } ],
+        "OUTPUTDIR": [ { "value": "../../../../tx_qpsk.gen/sources_1/ip/hrc_64_12_025" } ],
         "SELECTEDSIMMODEL": [ { "value": "" } ],
         "SHAREDDIR": [ { "value": "." } ],
         "SWVERSION": [ { "value": "2023.2.1" } ],
@@ -192,7 +192,7 @@
         "s_axis_data_tready": [ { "direction": "out", "driver_value": "0x1" } ],
         "s_axis_data_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
         "m_axis_data_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
-        "m_axis_data_tdata": [ { "direction": "out", "size_left": "95", "size_right": "0", "driver_value": "0" } ]
+        "m_axis_data_tdata": [ { "direction": "out", "size_left": "23", "size_right": "0", "driver_value": "0" } ]
       },
       "interfaces": {
         "event_s_data_tlast_missing_intf": {
@@ -299,7 +299,7 @@
           "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
           "mode": "slave",
           "parameters": {
-            "TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -324,7 +324,7 @@
           "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
           "mode": "master",
           "parameters": {
-            "TDATA_NUM_BYTES": [ { "value": "12", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDATA_NUM_BYTES": [ { "value": "3", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],

modules/xc7z100ffg900-2/tx_qpsk/tx_qpsk.srcs/sources_1/new/tx_qpsk.v

@@ -0,0 +1,539 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/03/23 20:17:56
+// Last Modified Date: 2023/03/10 15:41
+// Design Name:
+// Module Name: tx_qpsk
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+//   Revision 0.01 - File Created
+//   20230228-1541 - 修改不扫频、无基带频偏时 [baseband_i/q] 的数据输出，原来从
+//     乘法器引出，会导致频率为 0 时输出数据错误，现在直接从基带数据引出。
+//   20230310-1542 - 增加输入参数，发送数据更改为直接由参数输入，发送方波改为 8
+//     倍过采样，发送双音信号中 1MHz 信号的频率控制字可以根据参数中的时钟频率计
+//     算得出。
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tx_qpsk
+#(
+    parameter DATA_WIDTH = 12, // need to be <= 16
+    parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
+    parameter BIT_DATA_LEN = 128,
+    parameter SQUARE_INTERP = 8,
+    parameter CLK_FREQ = 245760000 // in Hertz
+)
+(
+    input           clk                 ,
+    input           rst                 ,
+    output [DATA_WIDTH-1:0] tx_data_i   ,
+    output [DATA_WIDTH-1:0] tx_data_q   ,
+    // debug ports
+    input   [ 1:0]  waveform_sel        ,
+    input           sweep_on            ,
+    input   [31:0]  freq_set            ,
+    input   [ 1:0]  iq_sel              ,
+    input   [ 3:0]  bb_rshift
+);
+
+localparam RCOS_INTERP = 64;
+localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP;
+localparam FREQ_WORD_1M = 64'd2**64'd32*64'd1000000/CLK_FREQ;
+
+////////////////////////////////////////////////////////////////////////////////
+///////////////////////////////// Data Counter /////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// symbol & interpolation counter
+reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0]  cnt = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        cnt <= 'b0;
+    end
+    else begin
+        cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1;
+    end
+end
+
+////////////////////////////////////////////////////////////////////////////////
+////////////////////// Root-Rasied Cosine Shaping Filter ///////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// address
+reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_i = 'b0;
+reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_q = 'b1;
+
+always @(posedge clk) begin
+    if (rst) begin
+        hrc_data_addr_i <= 'b0;
+        hrc_data_addr_q <= 'b1;
+    end
+    else begin
+        hrc_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0};
+        hrc_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1};
+    end
+end
+
+// bit data
+reg hrc_data_i = 'b0;
+reg hrc_data_q = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        hrc_data_i <= 'b0;
+        hrc_data_q <= 'b0;
+    end
+    else begin
+        hrc_data_i <= BIT_DATA[hrc_data_addr_i];
+        hrc_data_q <= BIT_DATA[hrc_data_addr_q];
+    end
+end
+
+// polarization
+wire    [ 7:0]  hrc_data_polar_i;
+wire    [ 7:0]  hrc_data_polar_q;
+
+assign hrc_data_polar_i = {{7{hrc_data_i}},1'b1};
+assign hrc_data_polar_q = {{7{hrc_data_q}},1'b1};
+
+// root raised cosine shaping-filter
+wire    [23:0]  hrc_wave_i;
+wire    [23:0]  hrc_wave_q;
+
+hrc_64_12_025 u_hrc_i (
+    .aclk               (clk                ), // input wire aclk
+    .s_axis_data_tvalid (~rst               ), // input wire s_axis_data_tvalid
+    .s_axis_data_tready (                   ), // output wire s_axis_data_tready
+    .s_axis_data_tdata  (hrc_data_polar_i   ), // input wire [7 : 0] s_axis_data_tdata
+    .m_axis_data_tvalid (                   ), // output wire m_axis_data_tvalid
+    .m_axis_data_tdata  (hrc_wave_i         )  // output wire [23 : 0] m_axis_data_tdata
+);
+
+hrc_64_12_025 u_hrc_q (
+    .aclk               (clk                ), // input wire aclk
+    .s_axis_data_tvalid (~rst               ), // input wire s_axis_data_tvalid
+    .s_axis_data_tready (                   ), // output wire s_axis_data_tready
+    .s_axis_data_tdata  (hrc_data_polar_q   ), // input wire [7 : 0] s_axis_data_tdata
+    .m_axis_data_tvalid (                   ), // output wire m_axis_data_tvalid
+    .m_axis_data_tdata  (hrc_wave_q         )  // output wire [23 : 0] m_axis_data_tdata
+);
+
+
+////////////////////////////////////////////////////////////////////////////////
+//////////////////////////// Square Shaping Filter /////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// address
+reg [$clog2(BIT_DATA_LEN)-1 : 0] hsq_data_addr = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        hsq_data_addr <= 'b0;
+    end
+    else
+        hsq_data_addr <= {cnt[$clog2(SQUARE_INTERP) +: $clog2(BIT_DATA_LEN)]};
+end
+
+// bit data
+reg hsq_data = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        hsq_data <= 'b0;
+    end
+    else begin
+        hsq_data <= BIT_DATA[hsq_data_addr];
+    end
+end
+
+// square shaping-filter
+reg     [17:0]  hsq_wave_i ='b0;
+reg     [17:0]  hsq_wave_q ='b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        hsq_wave_i <= 'b0;
+        hsq_wave_q <= 'b0;
+    end
+    else begin
+        hsq_wave_i <= hsq_data ? 18'b01_1111_1111_1111_1111 : 18'b10_0000_0000_0000_0001;
+        hsq_wave_q <= hsq_data ? 18'b10_0000_0000_0000_0001 : 18'b01_1111_1111_1111_1111;
+    end
+end
+
+
+////////////////////////////////////////////////////////////////////////////////
+/////////////////////////////// Two Tone Siganl ////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// cosine wave with freq of 1 MHz
+wire signed [7:0] cos_1m;
+wire signed [7:0] sin_1m;
+
+dds_32b_8b u_dds_1m
+(
+    .aclk                 (clk                  ),  // input wire aclk
+    .s_axis_config_tvalid (1'b1                 ),  // input wire s_axis_config_tvalid
+    .s_axis_config_tdata  (FREQ_WORD_1M[31:0]   ),  // input wire [31 : 0] s_axis_config_tdata
+    .m_axis_data_tvalid   (                     ),  // output wire m_axis_data_tvalid
+    .m_axis_data_tdata    ({sin_1m,cos_1m}      )   // output wire [15 : 0] m_axis_data_tdata
+);
+
+// two-tone signal
+reg signed [16:0] two_tone_wave_i = 'b0;
+reg signed [16:0] two_tone_wave_q = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        two_tone_wave_i <= 'b0;
+        two_tone_wave_q <= 'b0;
+    end
+    else begin
+        two_tone_wave_i <= 17'b0_0111_1111_1111_1111 + {cos_1m[7],cos_1m,8'd0};
+        two_tone_wave_q <= 17'b0 + {sin_1m[7],sin_1m,8'd0};
+    end
+end
+
+
+////////////////////////////////////////////////////////////////////////////////
+///////////////////// Waveform Selection & Hopping Control /////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// baseband signal select
+reg [17:0] baseband_sel_i = 'b0;
+reg [17:0] baseband_sel_q = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        baseband_sel_i <= 'b0;
+        baseband_sel_q <= 'b0;
+    end
+    else begin
+        case (waveform_sel[1:0])
+            2'd0: begin
+                baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
+                baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
+            end
+            2'd1: begin
+                baseband_sel_i <= hsq_wave_i[17:0];
+                baseband_sel_q <= hsq_wave_q[17:0];
+            end
+            2'd2: begin
+                baseband_sel_i <= 18'b01_1111_1111_1111_1111;
+                baseband_sel_q <= 18'b0;
+            end
+            2'd3: begin
+                baseband_sel_i <= {two_tone_wave_i[16:0],1'b0};
+                baseband_sel_q <= {two_tone_wave_q[16:0],1'b0};
+            end
+            default: begin
+                baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
+                baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
+            end
+        endcase
+    end
+end
+
+// hopping control, 3750hop/s
+reg     [23:0]  sweep_rom_addr = 'b0;
+wire    [31:0]  freq_sweep;
+
+always @(posedge clk) begin
+    if (rst) begin
+        sweep_rom_addr <= 'b0;
+    end
+    else if (sweep_on) begin
+        sweep_rom_addr <= sweep_rom_addr + 24'b1;
+    end
+    else begin
+        sweep_rom_addr <= 'b0;
+    end
+end
+
+hop_rom u_sweep_rom
+(
+    .clka       (clk                    ), // input wire clka
+    .addra      (sweep_rom_addr[23:16]  ), // input wire [7 : 0] addra
+    .douta      (freq_sweep             )  // output wire [31 : 0] douta
+);
+
+// choose the actual frequency word
+reg     [31:0]  freq_word = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        freq_word <= 'b0;
+    end
+    else if (sweep_on) begin
+        // frequency sweep
+        freq_word <= freq_sweep;
+    end
+    else begin
+        // normal operation
+        freq_word <= freq_set;
+    end
+end
+
+// baseband frequency shift carrier generation
+wire    [ 7:0] cos_dds;
+wire    [ 7:0] sin_dds;
+reg     [ 7:0] cos = 'b0;
+reg     [ 7:0] sin = 'b0;
+
+dds_32b_8b u_dds_bb_shift (
+    .aclk                 (clk              ), // input wire aclk
+    .s_axis_config_tvalid (~rst             ), // input wire s_axis_config_tvalid
+    .s_axis_config_tdata  (freq_word        ), // input wire [31 : 0] s_axis_config_tdata
+    .m_axis_data_tvalid   (                 ), // output wire m_axis_data_tvalid
+    .m_axis_data_tdata    ({sin_dds,cos_dds})  // output wire [31 : 0] m_axis_data_tdata
+);
+
+always @(posedge clk) begin
+    if (rst) begin
+        cos <= 'b0;
+        sin <= 'b0;
+    end
+    else if (freq_word == 'b0) begin
+        // to make sure the carriers stay at the right position when freq = 0
+        cos <= 8'b0111_1111;
+        sin <= 8'b0111_1111;
+    end
+    else begin
+        cos <= cos_dds;
+        sin <= sin_dds;
+    end
+end
+
+// baseband frequency shift modulation
+wire    [47:0]  mod_cmpy_a;
+wire    [15:0]  mod_cmpy_b;
+wire    [63:0]  mod_cmpy_out;
+
+wire    [26:0]  baseband_mult_i;
+wire    [26:0]  baseband_mult_q;
+
+assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i};
+assign mod_cmpy_b = {-sin,cos};
+
+assign baseband_mult_i = mod_cmpy_out[58:32];
+assign baseband_mult_q = mod_cmpy_out[26: 0];
+
+cmpy_18x8 u_cmpy_18x8
+(
+    .aclk               (clk            ), // input wire aclk
+    .s_axis_a_tvalid    (1'b1           ), // input wire s_axis_a_tvalid
+    .s_axis_a_tdata     (mod_cmpy_a     ), // input wire [47 : 0] s_axis_a_tdata
+    .s_axis_b_tvalid    (1'b1           ), // input wire s_axis_b_tvalid
+    .s_axis_b_tdata     (mod_cmpy_b     ), // input wire [15 : 0] s_axis_b_tdata
+    .m_axis_dout_tvalid (               ), // output wire m_axis_dout_tvalid
+    .m_axis_dout_tdata  (mod_cmpy_out   )  // output wire [63 : 0] m_axis_dout_tdata
+);
+
+// truncate to 16-bit
+reg signed  [15:0]  baseband_i = 'b0;
+reg signed  [15:0]  baseband_q = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        baseband_i <= 'b0;
+        baseband_q <= 'b0;
+    end
+    else begin
+        case (waveform_sel[1:0])
+            2'd0: begin
+                // scale rasied-cosine-shaped bpsk signal by 1.125 or 1.625
+                baseband_i <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_i[17 -: 16] + {{3{baseband_sel_i[17]}},baseband_sel_i[17 -: 13]}) : (baseband_mult_i[25:10] + {baseband_mult_i[25],baseband_mult_i[25:11]} + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]});
+                baseband_q <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_q[17 -: 16] + {{3{baseband_sel_q[17]}},baseband_sel_q[17 -: 13]}) : (baseband_mult_q[25:10] + {baseband_mult_q[25],baseband_mult_q[25:11]} + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]});
+            end
+            2'd1: begin
+                baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : (baseband_mult_i[25:10] + {{2{baseband_mult_i[25]}},baseband_mult_i[25:12]});
+                baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : (baseband_mult_q[25:10] + {{2{baseband_mult_q[25]}},baseband_mult_q[25:12]});
+            end
+            2'd2: begin
+                baseband_i <= baseband_mult_i[24:9];
+                baseband_q <= baseband_mult_q[24:9];
+            end
+            2'd3: begin
+                baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9];
+                baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9];
+            end
+            default: begin
+                // scale rasied-cosine-shaped bpsk signal by 1.125
+                baseband_i <= baseband_mult_i[25:10] + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]};
+                baseband_q <= baseband_mult_q[25:10] + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]};
+            end
+        endcase
+    end
+end
+
+// iq selection & baseband right shift
+reg signed [15:0] baseband_data_i = 'b0;
+reg signed [15:0] baseband_data_q = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        baseband_data_i <= 'b0;
+        baseband_data_q <= 'b0;
+    end
+    else begin
+        // inphase selection
+        if (iq_sel[1]) begin
+            baseband_data_i <= baseband_i >>> bb_rshift;
+        end
+        else begin
+            baseband_data_i <= 'b0;
+        end
+        // quadrature selection
+        if (iq_sel[0]) begin
+            baseband_data_q <= baseband_q >>> bb_rshift;
+        end
+        else begin
+            baseband_data_q <= 'b0;
+        end
+    end
+end
+
+// output data to ports
+assign tx_data_i = baseband_data_i[15 -: DATA_WIDTH];
+assign tx_data_q = baseband_data_q[15 -: DATA_WIDTH];
+
+endmodule
+
+
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 2020/12/08 12:43:46
+// Design Name:
+// Module Name: tb_tx_qpsk
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+// module tb_tx_qpsk;
+
+// reg             clk         = 1'b0  ;
+// reg             rst         = 1'b1  ;
+// reg             tx_on       = 1'b1  ;
+// reg     [31:0]  freq_set            ;
+// reg     [ 1:0]  waveform_sel = 2'b00;
+// reg     [ 1:0]  iq_sel      = 2'b11 ;
+// wire    [11:0]  tx_data_i           ;
+// wire    [11:0]  tx_data_q           ;
+// reg     [ 3:0]  bb_rshift   = 5'b0  ;
+
+// tx_qpsk u_tx_qpsk
+// (
+//     .clk            (clk            ),
+//     .rst            (rst            ),
+//     .tx_data_i      (tx_data_i      ),
+//     .tx_data_q      (tx_data_q      ),
+//     .waveform_sel   (waveform_sel   ),
+//     .sweep_on       (1'b0           ),
+//     // .freq_set       (32'd447392426  ),
+//     .freq_set       (32'd0          ),
+//     .iq_sel         (iq_sel         ),
+//     .bb_rshift      (bb_rshift      )
+// );
+
+// initial begin
+//     #102
+//     rst = 1'b0;
+//     // freq_set = 32'd873813333;
+//     // waveform_sel = 2'b00;
+//     // bb_rshift = 5'd0;
+//     // #5000
+//     // bb_rshift = 5'd1;
+//     // #5000
+//     // bb_rshift = 5'd2;
+//     // #5000
+//     // bb_rshift = 5'd3;
+//     // #5000
+//     // bb_rshift = 5'd4;
+//     // #5000
+//     // bb_rshift = 5'd5;
+//     // #5000
+//     // bb_rshift = 5'd6;
+//     // #5000
+//     // bb_rshift = 5'd7;
+//     // #5000
+//     // bb_rshift = 5'd8;
+//     // #5000
+//     // bb_rshift = 5'd9;
+//     // #5000
+//     // bb_rshift = 5'd14;
+//     // #5000
+//     // bb_rshift = 5'd15;
+//     // #5000
+//     // bb_rshift = 5'd16;
+//     // freq_set = 32'd0;
+//     // func_sel = 3'b010;
+//     // #7777
+//     // freq_set = 32'd536870912;
+//     // func_sel = 3'b100;
+//     // #7777
+//     // freq_set = 32'd0;
+//     // func_sel = 3'b100;
+//     // #7777
+//     // freq_set = 32'd536870912;
+//     // func_sel = 3'b010;
+//     // #7777
+//     // freq_set = 32'd0;
+//     // func_sel = 3'b010;
+//     // freq_set = 32'd536870912;
+//     // iq_sel = 2'b00;
+//     // #7777
+//     // freq_set = 32'd536870912;
+//     // iq_sel = 2'b01;
+//     // #7777
+//     // freq_set = 32'd536870912;
+//     // iq_sel = 2'b10;
+//     // #7777
+//     // freq_set = 32'd536870912;
+//     // iq_sel = 2'b11;
+// end
+
+// always #5 clk = ~clk;
+
+// // integer i;
+// // integer w_file;
+
+// // initial begin
+// //     w_file = $fopen("D:\\qpsk_josh.txt","w");
+// //     for (i = 0; i <= 35000; i = i + 1) begin
+// //         wait(clk);
+// //         #10;
+// //         $fdisplay(w_file,"%d    %d",$signed(tx_data_i),
+// //                 $signed(tx_data_q));
+// //         if (i == 35000) begin
+// //             $fclose(w_file);
+// //             $stop;
+// //         end
+// //     end
+// // end
+
+// endmodule

modules/xc7z100ffg900-2/tx_qpsk/tx_qpsk.xpr

@@ -4,11 +4,11 @@
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
 <!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/Workspace/vivado-git-new/modules/xczu48dr-fsvg1517-2-i/tx_qpsk_poly/tx_qpsk_poly.xpr">
+<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/Workspace/vivado/vivado_pub/modules/xc7z100ffg900-2/tx_qpsk/tx_qpsk.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="fe1ad6990cf04f9197091f4875cffe86"/>
+    <Option Name="Id" Val="530ad85e2b5149f1879968832c5788e7"/>
-    <Option Name="Part" Val="xczu48dr-fsvg1517-2-i"/>
+    <Option Name="Part" Val="xc7z100ffg900-2"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
     <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
@@ -90,28 +90,7 @@
   <FileSets Version="1" Minor="32">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
       <Filter Type="Srcs"/>
-      <File Path="$PPRDIR/../dds_par/dds_par.srcs/sources_1/ip/cos_16384_16b/cos_16384_16b.xci">
+      <File Path="$PSRCDIR/sources_1/new/tx_qpsk.v">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../dds_par/dds_par.srcs/sources_1/new/addr_to_wave.v">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../dds_par/dds_par.srcs/sources_1/new/dds_par.v">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PSRCDIR/sources_1/new/tx_qpsk_poly.v">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
@@ -124,19 +103,7 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/ip/coe/hrc_256_12_025.coe">
+      <File Path="$PSRCDIR/sources_1/ip/coe/sweep_freq.coe">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PSRCDIR/sources_1/ip/coe/hrc_512_12_025.coe">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../dds_par/dds_par.srcs/sources_1/ip/coe/cos_16384_16b.coe">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
@@ -144,7 +111,7 @@
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="tx_qpsk_poly"/>
+        <Option Name="TopModule" Val="tx_qpsk"/>
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
     </FileSet>
@@ -157,7 +124,7 @@
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="tx_qpsk_poly"/>
+        <Option Name="TopModule" Val="tx_qpsk"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TopAutoSet" Val="TRUE"/>
         <Option Name="TransportPathDelay" Val="0"/>
@@ -176,6 +143,32 @@
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
     </FileSet>
+    <FileSet Name="dds_32b_8b" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dds_32b_8b" RelGenDir="$PGENDIR/dds_32b_8b">
+      <File Path="$PSRCDIR/sources_1/ip/dds_32b_8b/dds_32b_8b.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="dds_32b_8b"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="cmpy_18x8" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_18x8" RelGenDir="$PGENDIR/cmpy_18x8">
+      <File Path="$PSRCDIR/sources_1/ip/cmpy_18x8/cmpy_18x8.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="cmpy_18x8"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
     <FileSet Name="hrc_64_12_025" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_64_12_025" RelGenDir="$PGENDIR/hrc_64_12_025">
       <File Path="$PSRCDIR/sources_1/ip/hrc_64_12_025/hrc_64_12_025.xci">
         <FileInfo>
@@ -189,8 +182,8 @@
         <Option Name="UseBlackboxStub" Val="1"/>
       </Config>
     </FileSet>
-    <FileSet Name="hrc_256_12_025" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_256_12_025" RelGenDir="$PGENDIR/hrc_256_12_025">
+    <FileSet Name="hop_rom" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hop_rom" RelGenDir="$PGENDIR/hop_rom">
-      <File Path="$PSRCDIR/sources_1/ip/hrc_256_12_025/hrc_256_12_025.xci">
+      <File Path="$PSRCDIR/sources_1/ip/hop_rom/hop_rom.xci">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
@@ -198,20 +191,7 @@
         </FileInfo>
       </File>
       <Config>
-        <Option Name="TopModule" Val="hrc_256_12_025"/>
+        <Option Name="TopModule" Val="hop_rom"/>
-        <Option Name="UseBlackboxStub" Val="1"/>
-      </Config>
-    </FileSet>
-    <FileSet Name="hrc_512_12_025" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_512_12_025" RelGenDir="$PGENDIR/hrc_512_12_025">
-      <File Path="$PSRCDIR/sources_1/ip/hrc_512_12_025/hrc_512_12_025.xci">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <Config>
-        <Option Name="TopModule" Val="hrc_512_12_025"/>
         <Option Name="UseBlackboxStub" Val="1"/>
       </Config>
     </FileSet>
@@ -238,18 +218,7 @@
     </Simulator>
   </Simulators>
   <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z100ffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
-      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
-        <Step Id="synth_design"/>
-      </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
-      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
-      <RQSFiles/>
-    </Run>
-    <Run Id="hrc_64_12_025_synth_1" Type="Ft3:Synth" SrcSet="hrc_64_12_025" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="hrc_64_12_025" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hrc_64_12_025_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
           <Desc>Vivado Synthesis Defaults</Desc>
@@ -261,7 +230,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="hrc_256_12_025_synth_1" Type="Ft3:Synth" SrcSet="hrc_256_12_025" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="hrc_256_12_025" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hrc_256_12_025_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_256_12_025_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_256_12_025_synth_1">
+    <Run Id="dds_32b_8b_synth_1" Type="Ft3:Synth" SrcSet="dds_32b_8b" Part="xc7z100ffg900-2" ConstrsSet="dds_32b_8b" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dds_32b_8b_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dds_32b_8b_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dds_32b_8b_synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
           <Desc>Vivado Synthesis Defaults</Desc>
@@ -273,7 +242,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="hrc_512_12_025_synth_1" Type="Ft3:Synth" SrcSet="hrc_512_12_025" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="hrc_512_12_025" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hrc_512_12_025_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_512_12_025_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_512_12_025_synth_1">
+    <Run Id="cmpy_18x8_synth_1" Type="Ft3:Synth" SrcSet="cmpy_18x8" Part="xc7z100ffg900-2" ConstrsSet="cmpy_18x8" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/cmpy_18x8_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_18x8_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_18x8_synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
           <Desc>Vivado Synthesis Defaults</Desc>
@@ -285,7 +254,31 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="hrc_64_12_025_synth_1" Type="Ft3:Synth" SrcSet="hrc_64_12_025" Part="xc7z100ffg900-2" ConstrsSet="hrc_64_12_025" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hrc_64_12_025_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="hop_rom_synth_1" Type="Ft3:Synth" SrcSet="hop_rom" Part="xc7z100ffg900-2" ConstrsSet="hop_rom" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hop_rom_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hop_rom_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hop_rom_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
           <Desc>Default settings for Implementation.</Desc>
@@ -304,7 +297,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="hrc_64_12_025_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="hrc_64_12_025" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hrc_64_12_025_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_impl_1">
+    <Run Id="dds_32b_8b_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="dds_32b_8b" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dds_32b_8b_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dds_32b_8b_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dds_32b_8b_impl_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
           <Desc>Default settings for Implementation.</Desc>
@@ -323,7 +316,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="hrc_256_12_025_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="hrc_256_12_025" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hrc_256_12_025_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_256_12_025_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_256_12_025_impl_1">
+    <Run Id="cmpy_18x8_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="cmpy_18x8" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="cmpy_18x8_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_18x8_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_18x8_impl_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
           <Desc>Default settings for Implementation.</Desc>
@@ -342,7 +335,26 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="hrc_512_12_025_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="hrc_512_12_025" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hrc_512_12_025_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_512_12_025_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_512_12_025_impl_1">
+    <Run Id="hrc_64_12_025_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="hrc_64_12_025" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hrc_64_12_025_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="hop_rom_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="hop_rom" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hop_rom_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hop_rom_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hop_rom_impl_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
           <Desc>Default settings for Implementation.</Desc>

modules/xczu48dr-fsvg1517-2-i/tx_qpsk_poly/tx_qpsk_poly.srcs/sources_1/ip/coe/hrc_64_12_025.coe

@@ -1,776 +0,0 @@
-; XILINX CORE Generator v1.0 
-; Copyright 2023 Gatsby Van <[email protected]>
-;	generated by MATLAB 23.2 (R2023b)
-;	generated at: 15-Jan-2024 11:07:53 +0800
-
-RADIX = 10;
-COEFDATA = 
-  -46,
-  -30,
-  -13,
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modules/xczu48dr-fsvg1517-2-i/tx_qpsk_poly/tx_qpsk_poly.srcs/sources_1/ip/hrc_512_12_025/hrc_512_12_025.xci

@@ -1,349 +0,0 @@
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-  }
-}

modules/xczu48dr-fsvg1517-2-i/tx_qpsk_poly/tx_qpsk_poly.srcs/sources_1/new/tx_qpsk_poly.v

@@ -1,627 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company:
-// Engineer:
-//      _           _        ____
-//     | | ___  ___| |__    / ___| __ _  ___
-//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
-// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
-//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
-//
-// Create Date: 2022/03/23 20:17:56
-// Last Modified Date: 2023/03/10 15:41
-// Design Name:
-// Module Name: tx_qpsk_poly
-// Project Name:
-// Target Devices:
-// Tool Versions:
-// Description:
-//
-// Dependencies:
-//
-// Revision:
-//   Revision 0.01 - File Created
-//   20230228-1541 - 修改不扫频、无基带频偏时 [baseband_i/q] 的数据输出，原来从
-//     乘法器引出，会导致频率为 0 时输出数据错误，现在直接从基带数据引出。
-//   20230310-1542 - 增加输入参数，发送数据更改为直接由参数输入，发送方波改为 8
-//     倍过采样，发送双音信号中 1MHz 信号的频率控制字可以根据参数中的时钟频率计
-//     算得出。
-// Additional Comments:
-//
-//////////////////////////////////////////////////////////////////////////////////
-
-
-module tx_qpsk_poly
-#(
-  parameter DATA_WIDTH = 12, // need to be <= 16
-  parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
-  parameter BIT_DATA_LEN = 128,
-  parameter SQUARE_INTERP = 8,
-  parameter CLK_FREQ = 245_760_000*8, // in Hertz
-  parameter PARALLEL_NUM = 8
-)
-(
-  input           clk                 ,
-  input           rst                 ,
-  output [DATA_WIDTH-1:0] tx_data_i   ,
-  output [DATA_WIDTH-1:0] tx_data_q   ,
-  // debug ports
-  input   [ 1:0]  waveform_sel        ,
-  input           sweep_on            ,
-  input   [31:0]  freq_set            ,
-  input   [ 1:0]  iq_sel              ,
-  input   [ 3:0]  bb_rshift
-);
-
-localparam RCOS_INTERP = 64*PARALLEL_NUM;
-localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP;
-localparam FREQ_WORD_1M = (64'd2)**(64'd16)*(64'd1_000_000)/CLK_FREQ;
-
-integer i;
-genvar m;
-
-////////////////////////////////////////////////////////////////////////////////
-///////////////////////////////// Data Counter /////////////////////////////////
-////////////////////////////////////////////////////////////////////////////////
-// symbol & interpolation counter
-reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0]  cnt = 'b0;
-
-always @(posedge clk) begin
-    if (rst) begin
-        cnt <= 'b0;
-    end
-    else begin
-        cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1;
-    end
-end
-
-// address
-reg [$clog2(BIT_DATA_LEN)-1 : 0] bit_data_addr_i = 'b0;
-reg [$clog2(BIT_DATA_LEN)-1 : 0] bit_data_addr_q = 'b1;
-
-always @(posedge clk) begin
-    if (rst) begin
-        bit_data_addr_i <= 'b0;
-        bit_data_addr_q <= 'b1;
-    end
-    else begin
-        bit_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0};
-        bit_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1};
-    end
-end
-
-// bit data
-reg bit_data_i = 'b0;
-reg bit_data_q = 'b0;
-
-always @(posedge clk) begin
-    if (rst) begin
-        bit_data_i <= 'b0;
-        bit_data_q <= 'b0;
-    end
-    else begin
-        bit_data_i <= BIT_DATA[bit_data_addr_i];
-        bit_data_q <= BIT_DATA[bit_data_addr_q];
-    end
-end
-
-////////////////////////////////////////////////////////////////////////////////
-////////////////////// Root-Rasied Cosine Shaping Filter ///////////////////////
-////////////////////////////////////////////////////////////////////////////////
-
-// polarization
-wire [7:0] hrc_data_polar_i;
-wire [7:0] hrc_data_polar_q;
-
-assign hrc_data_polar_i = {{7{bit_data_i}},1'b1};
-assign hrc_data_polar_q = {{7{bit_data_q}},1'b1};
-
-// root raised cosine shaping-filter
-wire [24*PARALLEL_NUM-1 : 0] hrc_wave_i;
-wire [24*PARALLEL_NUM-1 : 0] hrc_wave_q;
-
-wire [23:0] hrc_wave_i_par [0 : PARALLEL_NUM-1];
-wire [23:0] hrc_wave_q_par [0 : PARALLEL_NUM-1];
-
-generate
-
-for (m = 0; m < PARALLEL_NUM; m = m + 1) begin
-  assign hrc_wave_i_par[m] = hrc_wave_i[24*m +: 24];
-  assign hrc_wave_q_par[m] = hrc_wave_q[24*m +: 24];
-end
-
-case (PARALLEL_NUM)
-  1: begin
-    hrc_64_12_025 u_hrc_i
-    (
-      .aclk               (clk              ), // input wire aclk
-      .s_axis_data_tvalid (~rst             ), // input wire s_axis_data_tvalid
-      .s_axis_data_tready (                 ), // output wire s_axis_data_tready
-      .s_axis_data_tdata  (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
-      .m_axis_data_tvalid (                 ), // output wire m_axis_data_tvalid
-      .m_axis_data_tdata  (hrc_wave_i       )  // output wire [23 : 0] m_axis_data_tdata
-    );
-
-    hrc_64_12_025 u_hrc_q
-    (
-      .aclk               (clk              ), // input wire aclk
-      .s_axis_data_tvalid (~rst             ), // input wire s_axis_data_tvalid
-      .s_axis_data_tready (                 ), // output wire s_axis_data_tready
-      .s_axis_data_tdata  (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
-      .m_axis_data_tvalid (                 ), // output wire m_axis_data_tvalid
-      .m_axis_data_tdata  (hrc_wave_q       )  // output wire [23 : 0] m_axis_data_tdata
-    );
-    end
-  4: begin
-    hrc_256_12_025 u_hrc_i
-    (
-      .aclk               (clk              ), // input wire aclk
-      .s_axis_data_tvalid (~rst             ), // input wire s_axis_data_tvalid
-      .s_axis_data_tready (                 ), // output wire s_axis_data_tready
-      .s_axis_data_tdata  (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
-      .m_axis_data_tvalid (                 ), // output wire m_axis_data_tvalid
-      .m_axis_data_tdata  (hrc_wave_i       )  // output wire [95 : 0] m_axis_data_tdata
-    );
-
-    hrc_256_12_025 u_hrc_q
-    (
-      .aclk               (clk              ), // input wire aclk
-      .s_axis_data_tvalid (~rst             ), // input wire s_axis_data_tvalid
-      .s_axis_data_tready (                 ), // output wire s_axis_data_tready
-      .s_axis_data_tdata  (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
-      .m_axis_data_tvalid (                 ), // output wire m_axis_data_tvalid
-      .m_axis_data_tdata  (hrc_wave_q       )  // output wire [95 : 0] m_axis_data_tdata
-    );
-  end
-  8: begin
-    hrc_512_12_025 u_hrc_i
-    (
-      .aclk               (clk              ), // input wire aclk
-      .s_axis_data_tvalid (~rst             ), // input wire s_axis_data_tvalid
-      .s_axis_data_tready (                 ), // output wire s_axis_data_tready
-      .s_axis_data_tdata  (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
-      .m_axis_data_tvalid (                 ), // output wire m_axis_data_tvalid
-      .m_axis_data_tdata  (hrc_wave_i       )  // output wire [191 : 0] m_axis_data_tdata
-    );
-
-    hrc_512_12_025 u_hrc_q
-    (
-      .aclk               (clk              ), // input wire aclk
-      .s_axis_data_tvalid (~rst             ), // input wire s_axis_data_tvalid
-      .s_axis_data_tready (                 ), // output wire s_axis_data_tready
-      .s_axis_data_tdata  (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
-      .m_axis_data_tvalid (                 ), // output wire m_axis_data_tvalid
-      .m_axis_data_tdata  (hrc_wave_q       )  // output wire [191 : 0] m_axis_data_tdata
-    );
-  end
-  default: begin
-    hrc_64_12_025 u_hrc_i
-    (
-      .aclk               (clk              ), // input wire aclk
-      .s_axis_data_tvalid (~rst             ), // input wire s_axis_data_tvalid
-      .s_axis_data_tready (                 ), // output wire s_axis_data_tready
-      .s_axis_data_tdata  (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
-      .m_axis_data_tvalid (                 ), // output wire m_axis_data_tvalid
-      .m_axis_data_tdata  (hrc_wave_i       )  // output wire [23 : 0] m_axis_data_tdata
-    );
-
-    hrc_64_12_025 u_hrc_q
-    (
-      .aclk               (clk              ), // input wire aclk
-      .s_axis_data_tvalid (~rst             ), // input wire s_axis_data_tvalid
-      .s_axis_data_tready (                 ), // output wire s_axis_data_tready
-      .s_axis_data_tdata  (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
-      .m_axis_data_tvalid (                 ), // output wire m_axis_data_tvalid
-      .m_axis_data_tdata  (hrc_wave_q       )  // output wire [23 : 0] m_axis_data_tdata
-    );
-  end
-endcase
-
-endgenerate
-
-
-////////////////////////////////////////////////////////////////////////////////
-//////////////////////////// Square Shaping Filter /////////////////////////////
-////////////////////////////////////////////////////////////////////////////////
-
-// square shaping-filter
-reg [17:0] hsq_wave_i ='b0;
-reg [17:0] hsq_wave_q ='b0;
-
-always @(posedge clk) begin
-  if (rst) begin
-    hsq_wave_i <= 'b0;
-    hsq_wave_q <= 'b0;
-  end
-  else begin
-    hsq_wave_i <= bit_data_i ? 18'b01_1111_1111_1111_1111 : 18'b10_0000_0000_0000_0001;
-    hsq_wave_q <= bit_data_q ? 18'b10_0000_0000_0000_0001 : 18'b01_1111_1111_1111_1111;
-  end
-end
-
-
-////////////////////////////////////////////////////////////////////////////////
-/////////////////////////////// Two Tone Signal ////////////////////////////////
-////////////////////////////////////////////////////////////////////////////////
-// cosine wave with freq of 1 MHz
-wire signed [16*PARALLEL_NUM-1 : 0] cos_1m;
-wire signed [16*PARALLEL_NUM-1 : 0] sin_1m;
-
-wire signed [15 : 0] cos_1m_par [0 : PARALLEL_NUM-1];
-wire signed [15 : 0] sin_1m_par [0 : PARALLEL_NUM-1];
-
-generate
-for (m = 0; m < PARALLEL_NUM; m = m + 1) begin
-  assign cos_1m_par[m] = cos_1m[16*m +: 16];
-  assign sin_1m_par[m] = sin_1m[16*m +: 16];
-end
-endgenerate
-
-dds_par #(
-  .PHASE_WIDTH  (16           ),
-  .WAVE_WIDTH   (16           ),
-  .PARALLEL_NUM (PARALLEL_NUM )
-)
-(
-  .clk      (clk          ),
-  .rst      (rst          ),
-
-  .phase_inc(FREQ_WORD_1M ),
-
-  .cos_wave (cos_1m       ),
-  .sin_wave (sin_1m       )
-);
-
-// two-tone signal
-reg signed [15:0] two_tone_wave_i [0 : PARALLEL_NUM-1];
-reg signed [15:0] two_tone_wave_q [0 : PARALLEL_NUM-1];
-
-always @(posedge clk) begin
-  if (rst) begin
-    for (i = 0; i < PARALLEL_NUM; i = i + 1) begin
-      two_tone_wave_i[i] <= 'b0;
-      two_tone_wave_q[i] <= 'b0;
-    end
-  end
-  else begin
-    for (i = 0; i < PARALLEL_NUM; i = i + 1) begin
-      two_tone_wave_i[i] <= (cos_1m[i] >>> 1) + 16'h3fff;
-      two_tone_wave_q[i] <= (sin_1m[i] >>> 1) + 16'b0;
-    end
-  end
-end
-
-
-////////////////////////////////////////////////////////////////////////////////
-///////////////////// Waveform Selection & Hopping Control /////////////////////
-////////////////////////////////////////////////////////////////////////////////
-// baseband signal select
-reg [15:0] baseband_sel_i [0 : PARALLEL_NUM-1];
-reg [15:0] baseband_sel_q [0 : PARALLEL_NUM-1];
-
-always @(posedge clk) begin
-  if (rst) begin
-    for (i = 0; i < PARALLEL_NUM; i = i + 1) begin
-      baseband_sel_i[i] <= 'b0;
-      baseband_sel_q[i] <= 'b0;
-    end
-  end
-  else begin
-    for (i = 0; i < PARALLEL_NUM; i = i + 1) begin
-      case (waveform_sel[1:0])
-        2'd0: begin
-          baseband_sel_i[i] <= hrc_wave_i_par[i][0 +: 16];
-          baseband_sel_q[i] <= hrc_wave_q_par[i][0 +: 16];
-        end
-        2'd1: begin
-          baseband_sel_i[i] <= hsq_wave_i[17:0];
-          baseband_sel_q[i] <= hsq_wave_q[17:0];
-        end
-        2'd2: begin
-          baseband_sel_i[i] <= 16'h7fff;
-          baseband_sel_q[i] <= 16'b0;
-        end
-        2'd3: begin
-          baseband_sel_i[i] <= two_tone_wave_i[i];
-          baseband_sel_q[i] <= two_tone_wave_q[i];
-        end
-        default: begin
-          baseband_sel_i[i] <= hrc_wave_i_par[i][0 +: 16];
-          baseband_sel_q[i] <= hrc_wave_q_par[i][0 +: 16];
-        end
-      endcase
-    end
-  end
-end
-
-// hopping control, 3750hop/s
-reg     [23:0]  sweep_rom_addr = 'b0;
-wire    [31:0]  freq_sweep;
-
-always @(posedge clk) begin
-  if (rst) begin
-    sweep_rom_addr <= 'b0;
-  end
-  else if (sweep_on) begin
-    sweep_rom_addr <= sweep_rom_addr + 24'b1;
-  end
-  else begin
-    sweep_rom_addr <= 'b0;
-  end
-end
-
-hop_rom u_sweep_rom
-(
-  .clka       (clk                    ), // input wire clka
-  .addra      (sweep_rom_addr[23:16]  ), // input wire [7 : 0] addra
-  .douta      (freq_sweep             )  // output wire [31 : 0] douta
-);
-
-// choose the actual frequency word
-reg     [31:0]  freq_word = 'b0;
-
-always @(posedge clk) begin
-  if (rst) begin
-    freq_word <= 'b0;
-  end
-  else if (sweep_on) begin
-    // frequency sweep
-    freq_word <= freq_sweep;
-  end
-  else begin
-    // normal operation
-    freq_word <= freq_set;
-  end
-end
-
-// baseband frequency shift carrier generation
-wire    [ 7:0] cos_dds;
-wire    [ 7:0] sin_dds;
-reg     [ 7:0] cos = 'b0;
-reg     [ 7:0] sin = 'b0;
-
-dds_32b_8b u_dds_bb_shift (
-  .aclk                 (clk              ), // input wire aclk
-  .s_axis_config_tvalid (~rst             ), // input wire s_axis_config_tvalid
-  .s_axis_config_tdata  (freq_word        ), // input wire [31 : 0] s_axis_config_tdata
-  .m_axis_data_tvalid   (                 ), // output wire m_axis_data_tvalid
-  .m_axis_data_tdata    ({sin_dds,cos_dds})  // output wire [31 : 0] m_axis_data_tdata
-);
-
-always @(posedge clk) begin
-  if (rst) begin
-    cos <= 'b0;
-    sin <= 'b0;
-  end
-  else if (freq_word == 'b0) begin
-    // to make sure the carriers stay at the right position when freq = 0
-    cos <= 8'b0111_1111;
-    sin <= 8'b0111_1111;
-  end
-  else begin
-    cos <= cos_dds;
-    sin <= sin_dds;
-  end
-end
-
-// baseband frequency shift modulation
-wire    [47:0]  mod_cmpy_a;
-wire    [15:0]  mod_cmpy_b;
-wire    [63:0]  mod_cmpy_out;
-
-wire    [26:0]  baseband_mult_i;
-wire    [26:0]  baseband_mult_q;
-
-assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i};
-assign mod_cmpy_b = {-sin,cos};
-
-assign baseband_mult_i = mod_cmpy_out[58:32];
-assign baseband_mult_q = mod_cmpy_out[26: 0];
-
-cmpy_18x8 u_cmpy_18x8
-(
-  .aclk               (clk            ), // input wire aclk
-  .s_axis_a_tvalid    (1'b1           ), // input wire s_axis_a_tvalid
-  .s_axis_a_tdata     (mod_cmpy_a     ), // input wire [47 : 0] s_axis_a_tdata
-  .s_axis_b_tvalid    (1'b1           ), // input wire s_axis_b_tvalid
-  .s_axis_b_tdata     (mod_cmpy_b     ), // input wire [15 : 0] s_axis_b_tdata
-  .m_axis_dout_tvalid (               ), // output wire m_axis_dout_tvalid
-  .m_axis_dout_tdata  (mod_cmpy_out   )  // output wire [63 : 0] m_axis_dout_tdata
-);
-
-// truncate to 16-bit
-reg signed  [15:0]  baseband_i = 'b0;
-reg signed  [15:0]  baseband_q = 'b0;
-
-always @(posedge clk) begin
-  if (rst) begin
-    baseband_i <= 'b0;
-    baseband_q <= 'b0;
-  end
-  else begin
-    case (waveform_sel[1:0])
-      2'd0: begin
-        // scale rasied-cosine-shaped bpsk signal by 1.125 or 1.625
-        baseband_i <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_i[17 -: 16] + {{3{baseband_sel_i[17]}},baseband_sel_i[17 -: 13]}) : (baseband_mult_i[25:10] + {baseband_mult_i[25],baseband_mult_i[25:11]} + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]});
-        baseband_q <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_q[17 -: 16] + {{3{baseband_sel_q[17]}},baseband_sel_q[17 -: 13]}) : (baseband_mult_q[25:10] + {baseband_mult_q[25],baseband_mult_q[25:11]} + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]});
-      end
-      2'd1: begin
-        baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : (baseband_mult_i[25:10] + {{2{baseband_mult_i[25]}},baseband_mult_i[25:12]});
-        baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : (baseband_mult_q[25:10] + {{2{baseband_mult_q[25]}},baseband_mult_q[25:12]});
-      end
-      2'd2: begin
-        baseband_i <= baseband_mult_i[24:9];
-        baseband_q <= baseband_mult_q[24:9];
-      end
-      2'd3: begin
-        baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9];
-        baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9];
-      end
-      default: begin
-        // scale rasied-cosine-shaped bpsk signal by 1.125
-        baseband_i <= baseband_mult_i[25:10] + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]};
-        baseband_q <= baseband_mult_q[25:10] + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]};
-      end
-    endcase
-  end
-end
-
-// iq selection & baseband right shift
-reg signed [15:0] baseband_data_i = 'b0;
-reg signed [15:0] baseband_data_q = 'b0;
-
-always @(posedge clk) begin
-  if (rst) begin
-    baseband_data_i <= 'b0;
-    baseband_data_q <= 'b0;
-  end
-  else begin
-    // inphase selection
-    if (iq_sel[1]) begin
-      baseband_data_i <= baseband_i >>> bb_rshift;
-    end
-    else begin
-      baseband_data_i <= 'b0;
-    end
-    // quadrature selection
-    if (iq_sel[0]) begin
-      baseband_data_q <= baseband_q >>> bb_rshift;
-    end
-    else begin
-      baseband_data_q <= 'b0;
-    end
-  end
-end
-
-// output data to ports
-assign tx_data_i = baseband_data_i[15 -: DATA_WIDTH];
-assign tx_data_q = baseband_data_q[15 -: DATA_WIDTH];
-
-endmodule
-
-
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company:
-// Engineer:
-//
-// Create Date: 2020/12/08 12:43:46
-// Design Name:
-// Module Name: tb_tx_qpsk
-// Project Name:
-// Target Devices:
-// Tool Versions:
-// Description:
-//
-// Dependencies:
-//
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-//
-//////////////////////////////////////////////////////////////////////////////////
-
-
-// module tb_tx_qpsk;
-
-// reg             clk         = 1'b0  ;
-// reg             rst         = 1'b1  ;
-// reg             tx_on       = 1'b1  ;
-// reg     [31:0]  freq_set            ;
-// reg     [ 1:0]  waveform_sel = 2'b00;
-// reg     [ 1:0]  iq_sel      = 2'b11 ;
-// wire    [11:0]  tx_data_i           ;
-// wire    [11:0]  tx_data_q           ;
-// reg     [ 3:0]  bb_rshift   = 5'b0  ;
-
-// tx_qpsk u_tx_qpsk
-// (
-//     .clk            (clk            ),
-//     .rst            (rst            ),
-//     .tx_data_i      (tx_data_i      ),
-//     .tx_data_q      (tx_data_q      ),
-//     .waveform_sel   (waveform_sel   ),
-//     .sweep_on       (1'b0           ),
-//     // .freq_set       (32'd447392426  ),
-//     .freq_set       (32'd0          ),
-//     .iq_sel         (iq_sel         ),
-//     .bb_rshift      (bb_rshift      )
-// );
-
-// initial begin
-//     #102
-//     rst = 1'b0;
-//     // freq_set = 32'd873813333;
-//     // waveform_sel = 2'b00;
-//     // bb_rshift = 5'd0;
-//     // #5000
-//     // bb_rshift = 5'd1;
-//     // #5000
-//     // bb_rshift = 5'd2;
-//     // #5000
-//     // bb_rshift = 5'd3;
-//     // #5000
-//     // bb_rshift = 5'd4;
-//     // #5000
-//     // bb_rshift = 5'd5;
-//     // #5000
-//     // bb_rshift = 5'd6;
-//     // #5000
-//     // bb_rshift = 5'd7;
-//     // #5000
-//     // bb_rshift = 5'd8;
-//     // #5000
-//     // bb_rshift = 5'd9;
-//     // #5000
-//     // bb_rshift = 5'd14;
-//     // #5000
-//     // bb_rshift = 5'd15;
-//     // #5000
-//     // bb_rshift = 5'd16;
-//     // freq_set = 32'd0;
-//     // func_sel = 3'b010;
-//     // #7777
-//     // freq_set = 32'd536870912;
-//     // func_sel = 3'b100;
-//     // #7777
-//     // freq_set = 32'd0;
-//     // func_sel = 3'b100;
-//     // #7777
-//     // freq_set = 32'd536870912;
-//     // func_sel = 3'b010;
-//     // #7777
-//     // freq_set = 32'd0;
-//     // func_sel = 3'b010;
-//     // freq_set = 32'd536870912;
-//     // iq_sel = 2'b00;
-//     // #7777
-//     // freq_set = 32'd536870912;
-//     // iq_sel = 2'b01;
-//     // #7777
-//     // freq_set = 32'd536870912;
-//     // iq_sel = 2'b10;
-//     // #7777
-//     // freq_set = 32'd536870912;
-//     // iq_sel = 2'b11;
-// end
-
-// always #5 clk = ~clk;
-
-// // integer i;
-// // integer w_file;
-
-// // initial begin
-// //     w_file = $fopen("D:\\qpsk_josh.txt","w");
-// //     for (i = 0; i <= 35000; i = i + 1) begin
-// //         wait(clk);
-// //         #10;
-// //         $fdisplay(w_file,"%d    %d",$signed(tx_data_i),
-// //                 $signed(tx_data_q));
-// //         if (i == 35000) begin
-// //             $fclose(w_file);
-// //             $stop;
-// //         end
-// //     end
-// // end
-
-// endmodule

projects/ax7020/ax7020_borad_preset.tcl

@@ -0,0 +1,819 @@
+proc getPresetInfo {} {
+  return [dict create name {ax7020} description {ax7020}  vlnv xilinx.com:ip:processing_system7:5.5 display_name {ax7020} ]
+}
+
+proc validate_preset {IPINST} { return true }
+
+
+proc apply_preset {IPINST} {
+  return [dict create \
+    CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000}  \
+    CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF}  \
+    CONFIG.PCW_UART0_BASEADDR {0xE0000000}  \
+    CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF}  \
+    CONFIG.PCW_UART1_BASEADDR {0xE0001000}  \
+    CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF}  \
+    CONFIG.PCW_I2C0_BASEADDR {0xE0004000}  \
+    CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF}  \
+    CONFIG.PCW_I2C1_BASEADDR {0xE0005000}  \
+    CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF}  \
+    CONFIG.PCW_SPI0_BASEADDR {0xE0006000}  \
+    CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF}  \
+    CONFIG.PCW_SPI1_BASEADDR {0xE0007000}  \
+    CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF}  \
+    CONFIG.PCW_CAN0_BASEADDR {0xE0008000}  \
+    CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF}  \
+    CONFIG.PCW_CAN1_BASEADDR {0xE0009000}  \
+    CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF}  \
+    CONFIG.PCW_GPIO_BASEADDR {0xE000A000}  \
+    CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF}  \
+    CONFIG.PCW_ENET0_BASEADDR {0xE000B000}  \
+    CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF}  \
+    CONFIG.PCW_ENET1_BASEADDR {0xE000C000}  \
+    CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF}  \
+    CONFIG.PCW_SDIO0_BASEADDR {0xE0100000}  \
+    CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF}  \
+    CONFIG.PCW_SDIO1_BASEADDR {0xE0101000}  \
+    CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF}  \
+    CONFIG.PCW_USB0_BASEADDR {0xE0102000}  \
+    CONFIG.PCW_USB0_HIGHADDR {0xE0102fff}  \
+    CONFIG.PCW_USB1_BASEADDR {0xE0103000}  \
+    CONFIG.PCW_USB1_HIGHADDR {0xE0103fff}  \
+    CONFIG.PCW_TTC0_BASEADDR {0xE0104000}  \
+    CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff}  \
+    CONFIG.PCW_TTC1_BASEADDR {0xE0105000}  \
+    CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff}  \
+    CONFIG.PCW_FCLK_CLK0_BUF {TRUE}  \
+    CONFIG.PCW_FCLK_CLK1_BUF {TRUE}  \
+    CONFIG.PCW_FCLK_CLK2_BUF {TRUE}  \
+    CONFIG.PCW_FCLK_CLK3_BUF {FALSE}  \
+    CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333333}  \
+    CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3}  \
+    CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15}  \
+    CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10}  \
+    CONFIG.PCW_UIPARAM_DDR_CL {7}  \
+    CONFIG.PCW_UIPARAM_DDR_CWL {6}  \
+    CONFIG.PCW_UIPARAM_DDR_T_RCD {7}  \
+    CONFIG.PCW_UIPARAM_DDR_T_RP {7}  \
+    CONFIG.PCW_UIPARAM_DDR_T_RC {48.91}  \
+    CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0}  \
+    CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0}  \
+    CONFIG.PCW_UIPARAM_DDR_AL {0}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.0}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.0}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.0}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.0}  \
+    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.25}  \
+    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.25}  \
+    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.25}  \
+    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.25}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {0}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {0}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {0}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {0}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {0}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {0}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {101.239}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {79.5025}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {60.536}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {71.7715}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {104.5365}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {70.676}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {59.1615}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {81.319}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {54.563}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {54.563}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {54.563}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {54.563}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.047}  \
+    CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.025}  \
+    CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.006}  \
+    CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.017}  \
+    CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.080}  \
+    CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.063}  \
+    CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.057}  \
+    CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.068}  \
+    CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {767}  \
+    CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333}  \
+    CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {767}  \
+    CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159}  \
+    CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200}  \
+    CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100}  \
+    CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60}  \
+    CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60}  \
+    CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100}  \
+    CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100}  \
+    CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666}  \
+    CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100}  \
+    CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1}  \
+    CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1}  \
+    CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {127.777779}  \
+    CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333}  \
+    CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50}  \
+    CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333}  \
+    CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333}  \
+    CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333}  \
+    CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333}  \
+    CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333}  \
+    CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333}  \
+    CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200}  \
+    CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200}  \
+    CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100}  \
+    CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {150}  \
+    CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {24}  \
+    CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50}  \
+    CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {766.666687}  \
+    CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374}  \
+    CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730}  \
+    CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000}  \
+    CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000}  \
+    CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000}  \
+    CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000}  \
+    CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60}  \
+    CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60}  \
+    CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000}  \
+    CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000}  \
+    CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000}  \
+    CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000}  \
+    CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095}  \
+    CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095}  \
+    CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50}  \
+    CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {127.777786}  \
+    CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50}  \
+    CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000}  \
+    CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000}  \
+    CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000}  \
+    CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {142.857132}  \
+    CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {23.809525}  \
+    CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000}  \
+    CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {127.777786}  \
+    CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {127.777786}  \
+    CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {127.777786}  \
+    CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {127.777786}  \
+    CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {127.777786}  \
+    CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {127.777786}  \
+    CONFIG.PCW_CLK0_FREQ {100000000}  \
+    CONFIG.PCW_CLK1_FREQ {142857132}  \
+    CONFIG.PCW_CLK2_FREQ {23809525}  \
+    CONFIG.PCW_CLK3_FREQ {10000000}  \
+    CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0}  \
+    CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2}  \
+    CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2}  \
+    CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5}  \
+    CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {10}  \
+    CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10}  \
+    CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1}  \
+    CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5}  \
+    CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {7}  \
+    CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {42}  \
+    CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2}  \
+    CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1}  \
+    CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1}  \
+    CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1}  \
+    CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8}  \
+    CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1}  \
+    CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1}  \
+    CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15}  \
+    CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7}  \
+    CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5}  \
+    CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_ARMPLL_CTRL_FBDIV {46}  \
+    CONFIG.PCW_IOPLL_CTRL_FBDIV {30}  \
+    CONFIG.PCW_DDRPLL_CTRL_FBDIV {32}  \
+    CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1533.333}  \
+    CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000}  \
+    CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667}  \
+    CONFIG.PCW_SMC_PERIPHERAL_VALID {0}  \
+    CONFIG.PCW_SDIO_PERIPHERAL_VALID {1}  \
+    CONFIG.PCW_SPI_PERIPHERAL_VALID {0}  \
+    CONFIG.PCW_CAN_PERIPHERAL_VALID {0}  \
+    CONFIG.PCW_UART_PERIPHERAL_VALID {1}  \
+    CONFIG.PCW_EN_EMIO_CAN0 {0}  \
+    CONFIG.PCW_EN_EMIO_CAN1 {0}  \
+    CONFIG.PCW_EN_EMIO_ENET0 {0}  \
+    CONFIG.PCW_EN_EMIO_ENET1 {0}  \
+    CONFIG.PCW_EN_PTP_ENET0 {0}  \
+    CONFIG.PCW_EN_PTP_ENET1 {0}  \
+    CONFIG.PCW_EN_EMIO_GPIO {0}  \
+    CONFIG.PCW_EN_EMIO_I2C0 {1}  \
+    CONFIG.PCW_EN_EMIO_I2C1 {1}  \
+    CONFIG.PCW_EN_EMIO_PJTAG {0}  \
+    CONFIG.PCW_EN_EMIO_SDIO0 {0}  \
+    CONFIG.PCW_EN_EMIO_CD_SDIO0 {0}  \
+    CONFIG.PCW_EN_EMIO_WP_SDIO0 {0}  \
+    CONFIG.PCW_EN_EMIO_SDIO1 {0}  \
+    CONFIG.PCW_EN_EMIO_CD_SDIO1 {0}  \
+    CONFIG.PCW_EN_EMIO_WP_SDIO1 {0}  \
+    CONFIG.PCW_EN_EMIO_SPI0 {0}  \
+    CONFIG.PCW_EN_EMIO_SPI1 {0}  \
+    CONFIG.PCW_EN_EMIO_UART0 {0}  \
+    CONFIG.PCW_EN_EMIO_UART1 {0}  \
+    CONFIG.PCW_EN_EMIO_MODEM_UART0 {0}  \
+    CONFIG.PCW_EN_EMIO_MODEM_UART1 {0}  \
+    CONFIG.PCW_EN_EMIO_TTC0 {0}  \
+    CONFIG.PCW_EN_EMIO_TTC1 {0}  \
+    CONFIG.PCW_EN_EMIO_WDT {0}  \
+    CONFIG.PCW_EN_EMIO_TRACE {0}  \
+    CONFIG.PCW_USE_AXI_NONSECURE {0}  \
+    CONFIG.PCW_USE_M_AXI_GP0 {1}  \
+    CONFIG.PCW_USE_M_AXI_GP1 {0}  \
+    CONFIG.PCW_USE_S_AXI_GP0 {0}  \
+    CONFIG.PCW_USE_S_AXI_GP1 {0}  \
+    CONFIG.PCW_USE_S_AXI_ACP {0}  \
+    CONFIG.PCW_USE_S_AXI_HP0 {1}  \
+    CONFIG.PCW_USE_S_AXI_HP1 {0}  \
+    CONFIG.PCW_USE_S_AXI_HP2 {0}  \
+    CONFIG.PCW_USE_S_AXI_HP3 {0}  \
+    CONFIG.PCW_USE_DMA0 {0}  \
+    CONFIG.PCW_USE_DMA1 {0}  \
+    CONFIG.PCW_USE_DMA2 {0}  \
+    CONFIG.PCW_USE_DMA3 {0}  \
+    CONFIG.PCW_USE_TRACE {0}  \
+    CONFIG.PCW_TRACE_PIPELINE_WIDTH {8}  \
+    CONFIG.PCW_INCLUDE_TRACE_BUFFER {0}  \
+    CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128}  \
+    CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0}  \
+    CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12}  \
+    CONFIG.PCW_USE_CROSS_TRIGGER {0}  \
+    CONFIG.PCW_FTM_CTI_IN0 {<Select>}  \
+    CONFIG.PCW_FTM_CTI_IN1 {<Select>}  \
+    CONFIG.PCW_FTM_CTI_IN2 {<Select>}  \
+    CONFIG.PCW_FTM_CTI_IN3 {<Select>}  \
+    CONFIG.PCW_FTM_CTI_OUT0 {<Select>}  \
+    CONFIG.PCW_FTM_CTI_OUT1 {<Select>}  \
+    CONFIG.PCW_FTM_CTI_OUT2 {<Select>}  \
+    CONFIG.PCW_FTM_CTI_OUT3 {<Select>}  \
+    CONFIG.PCW_USE_DEBUG {0}  \
+    CONFIG.PCW_USE_CR_FABRIC {1}  \
+    CONFIG.PCW_USE_AXI_FABRIC_IDLE {0}  \
+    CONFIG.PCW_USE_DDR_BYPASS {0}  \
+    CONFIG.PCW_USE_FABRIC_INTERRUPT {1}  \
+    CONFIG.PCW_USE_PROC_EVENT_BUS {0}  \
+    CONFIG.PCW_USE_EXPANDED_IOP {0}  \
+    CONFIG.PCW_USE_HIGH_OCM {0}  \
+    CONFIG.PCW_USE_PS_SLCR_REGISTERS {0}  \
+    CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0}  \
+    CONFIG.PCW_USE_CORESIGHT {0}  \
+    CONFIG.PCW_EN_EMIO_SRAM_INT {0}  \
+    CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64}  \
+    CONFIG.PCW_GP0_NUM_WRITE_THREADS {4}  \
+    CONFIG.PCW_GP0_NUM_READ_THREADS {4}  \
+    CONFIG.PCW_GP1_NUM_WRITE_THREADS {4}  \
+    CONFIG.PCW_GP1_NUM_READ_THREADS {4}  \
+    CONFIG.PCW_UART0_BAUD_RATE {115200}  \
+    CONFIG.PCW_UART1_BAUD_RATE {115200}  \
+    CONFIG.PCW_EN_4K_TIMER {0}  \
+    CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12}  \
+    CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0}  \
+    CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0}  \
+    CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12}  \
+    CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12}  \
+    CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0}  \
+    CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0}  \
+    CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12}  \
+    CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6}  \
+    CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6}  \
+    CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3}  \
+    CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0}  \
+    CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0}  \
+    CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31}  \
+    CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31}  \
+    CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6}  \
+    CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64}  \
+    CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6}  \
+    CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64}  \
+    CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6}  \
+    CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64}  \
+    CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6}  \
+    CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64}  \
+    CONFIG.PCW_EN_DDR {1}  \
+    CONFIG.PCW_EN_SMC {0}  \
+    CONFIG.PCW_EN_QSPI {1}  \
+    CONFIG.PCW_EN_CAN0 {0}  \
+    CONFIG.PCW_EN_CAN1 {0}  \
+    CONFIG.PCW_EN_ENET0 {1}  \
+    CONFIG.PCW_EN_ENET1 {0}  \
+    CONFIG.PCW_EN_GPIO {1}  \
+    CONFIG.PCW_EN_I2C0 {1}  \
+    CONFIG.PCW_EN_I2C1 {1}  \
+    CONFIG.PCW_EN_PJTAG {0}  \
+    CONFIG.PCW_EN_SDIO0 {1}  \
+    CONFIG.PCW_EN_SDIO1 {0}  \
+    CONFIG.PCW_EN_SPI0 {0}  \
+    CONFIG.PCW_EN_SPI1 {0}  \
+    CONFIG.PCW_EN_UART0 {0}  \
+    CONFIG.PCW_EN_UART1 {1}  \
+    CONFIG.PCW_EN_MODEM_UART0 {0}  \
+    CONFIG.PCW_EN_MODEM_UART1 {0}  \
+    CONFIG.PCW_EN_TTC0 {0}  \
+    CONFIG.PCW_EN_TTC1 {0}  \
+    CONFIG.PCW_EN_WDT {0}  \
+    CONFIG.PCW_EN_TRACE {0}  \
+    CONFIG.PCW_EN_USB0 {1}  \
+    CONFIG.PCW_EN_USB1 {0}  \
+    CONFIG.PCW_DQ_WIDTH {32}  \
+    CONFIG.PCW_DQS_WIDTH {4}  \
+    CONFIG.PCW_DM_WIDTH {4}  \
+    CONFIG.PCW_MIO_PRIMITIVE {54}  \
+    CONFIG.PCW_EN_CLK0_PORT {1}  \
+    CONFIG.PCW_EN_CLK1_PORT {1}  \
+    CONFIG.PCW_EN_CLK2_PORT {1}  \
+    CONFIG.PCW_EN_CLK3_PORT {0}  \
+    CONFIG.PCW_EN_RST0_PORT {1}  \
+    CONFIG.PCW_EN_RST1_PORT {0}  \
+    CONFIG.PCW_EN_RST2_PORT {0}  \
+    CONFIG.PCW_EN_RST3_PORT {0}  \
+    CONFIG.PCW_EN_CLKTRIG0_PORT {0}  \
+    CONFIG.PCW_EN_CLKTRIG1_PORT {0}  \
+    CONFIG.PCW_EN_CLKTRIG2_PORT {0}  \
+    CONFIG.PCW_EN_CLKTRIG3_PORT {0}  \
+    CONFIG.PCW_P2F_DMAC_ABORT_INTR {0}  \
+    CONFIG.PCW_P2F_DMAC0_INTR {0}  \
+    CONFIG.PCW_P2F_DMAC1_INTR {0}  \
+    CONFIG.PCW_P2F_DMAC2_INTR {0}  \
+    CONFIG.PCW_P2F_DMAC3_INTR {0}  \
+    CONFIG.PCW_P2F_DMAC4_INTR {0}  \
+    CONFIG.PCW_P2F_DMAC5_INTR {0}  \
+    CONFIG.PCW_P2F_DMAC6_INTR {0}  \
+    CONFIG.PCW_P2F_DMAC7_INTR {0}  \
+    CONFIG.PCW_P2F_SMC_INTR {0}  \
+    CONFIG.PCW_P2F_QSPI_INTR {0}  \
+    CONFIG.PCW_P2F_CTI_INTR {0}  \
+    CONFIG.PCW_P2F_GPIO_INTR {0}  \
+    CONFIG.PCW_P2F_USB0_INTR {0}  \
+    CONFIG.PCW_P2F_ENET0_INTR {0}  \
+    CONFIG.PCW_P2F_SDIO0_INTR {0}  \
+    CONFIG.PCW_P2F_I2C0_INTR {0}  \
+    CONFIG.PCW_P2F_SPI0_INTR {0}  \
+    CONFIG.PCW_P2F_UART0_INTR {0}  \
+    CONFIG.PCW_P2F_CAN0_INTR {0}  \
+    CONFIG.PCW_P2F_USB1_INTR {0}  \
+    CONFIG.PCW_P2F_ENET1_INTR {0}  \
+    CONFIG.PCW_P2F_SDIO1_INTR {0}  \
+    CONFIG.PCW_P2F_I2C1_INTR {0}  \
+    CONFIG.PCW_P2F_SPI1_INTR {0}  \
+    CONFIG.PCW_P2F_UART1_INTR {0}  \
+    CONFIG.PCW_P2F_CAN1_INTR {0}  \
+    CONFIG.PCW_IRQ_F2P_INTR {1}  \
+    CONFIG.PCW_IRQ_F2P_MODE {DIRECT}  \
+    CONFIG.PCW_CORE0_FIQ_INTR {0}  \
+    CONFIG.PCW_CORE0_IRQ_INTR {0}  \
+    CONFIG.PCW_CORE1_FIQ_INTR {0}  \
+    CONFIG.PCW_CORE1_IRQ_INTR {0}  \
+    CONFIG.PCW_VALUE_SILVERSION {3}  \
+    CONFIG.PCW_GP0_EN_MODIFIABLE_TXN {0}  \
+    CONFIG.PCW_GP1_EN_MODIFIABLE_TXN {0}  \
+    CONFIG.PCW_IMPORT_BOARD_PRESET {None}  \
+    CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None}  \
+    CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V}  \
+    CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}  \
+    CONFIG.PCW_UIPARAM_DDR_ENABLE {1}  \
+    CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0}  \
+    CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3}  \
+    CONFIG.PCW_UIPARAM_DDR_ECC {Disabled}  \
+    CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit}  \
+    CONFIG.PCW_UIPARAM_DDR_BL {8}  \
+    CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)}  \
+    CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125}  \
+    CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits}  \
+    CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits}  \
+    CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F}  \
+    CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}  \
+    CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}  \
+    CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0}  \
+    CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}  \
+    CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0}  \
+    CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0}  \
+    CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0}  \
+    CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0}  \
+    CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)}  \
+    CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2}  \
+    CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15}  \
+    CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2}  \
+    CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_NAND_GRP_D8_ENABLE {0}  \
+    CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_NOR_GRP_A25_ENABLE {0}  \
+    CONFIG.PCW_NOR_GRP_CS0_ENABLE {0}  \
+    CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0}  \
+    CONFIG.PCW_NOR_GRP_CS1_ENABLE {0}  \
+    CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0}  \
+    CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0}  \
+    CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6}  \
+    CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}  \
+    CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6}  \
+    CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0}  \
+    CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4}  \
+    CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0}  \
+    CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0}  \
+    CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF}  \
+    CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27}  \
+    CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1}  \
+    CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53}  \
+    CONFIG.PCW_ENET_RESET_ENABLE {1}  \
+    CONFIG.PCW_ENET_RESET_SELECT {Share reset pin}  \
+    CONFIG.PCW_ENET0_RESET_ENABLE {0}  \
+    CONFIG.PCW_ENET0_RESET_IO {<Select>}  \
+    CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0}  \
+    CONFIG.PCW_ENET1_RESET_ENABLE {0}  \
+    CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45}  \
+    CONFIG.PCW_SD0_GRP_CD_ENABLE {1}  \
+    CONFIG.PCW_SD0_GRP_CD_IO {MIO 47}  \
+    CONFIG.PCW_SD0_GRP_WP_ENABLE {0}  \
+    CONFIG.PCW_SD0_GRP_POW_ENABLE {0}  \
+    CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_SD1_SD1_IO {<Select>}  \
+    CONFIG.PCW_SD1_GRP_CD_ENABLE {0}  \
+    CONFIG.PCW_SD1_GRP_WP_ENABLE {0}  \
+    CONFIG.PCW_SD1_GRP_POW_ENABLE {0}  \
+    CONFIG.PCW_UART0_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_UART0_GRP_FULL_ENABLE {0}  \
+    CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49}  \
+    CONFIG.PCW_UART1_GRP_FULL_ENABLE {0}  \
+    CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0}  \
+    CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0}  \
+    CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0}  \
+    CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0}  \
+    CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0}  \
+    CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0}  \
+    CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0}  \
+    CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0}  \
+    CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0}  \
+    CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0}  \
+    CONFIG.PCW_TRACE_GRP_8BIT_ENABLE {0}  \
+    CONFIG.PCW_TRACE_GRP_16BIT_ENABLE {0}  \
+    CONFIG.PCW_TRACE_GRP_32BIT_ENABLE {0}  \
+    CONFIG.PCW_TRACE_INTERNAL_WIDTH {2}  \
+    CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39}  \
+    CONFIG.PCW_USB_RESET_ENABLE {1}  \
+    CONFIG.PCW_USB_RESET_SELECT {Share reset pin}  \
+    CONFIG.PCW_USB0_RESET_ENABLE {1}  \
+    CONFIG.PCW_USB0_RESET_IO {MIO 46}  \
+    CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_USB1_RESET_ENABLE {0}  \
+    CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_I2C0_I2C0_IO {EMIO}  \
+    CONFIG.PCW_I2C0_GRP_INT_ENABLE {1}  \
+    CONFIG.PCW_I2C0_GRP_INT_IO {EMIO}  \
+    CONFIG.PCW_I2C0_RESET_ENABLE {0}  \
+    CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_I2C1_I2C1_IO {EMIO}  \
+    CONFIG.PCW_I2C1_GRP_INT_ENABLE {1}  \
+    CONFIG.PCW_I2C1_GRP_INT_IO {EMIO}  \
+    CONFIG.PCW_I2C_RESET_ENABLE {1}  \
+    CONFIG.PCW_I2C_RESET_SELECT {Share reset pin}  \
+    CONFIG.PCW_I2C1_RESET_ENABLE {0}  \
+    CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}  \
+    CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO}  \
+    CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0}  \
+    CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1}  \
+    CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps}  \
+    CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps}  \
+    CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL}  \
+    CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL}  \
+    CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External}  \
+    CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External}  \
+    CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External}  \
+    CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X}  \
+    CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X}  \
+    CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X}  \
+    CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X}  \
+    CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X}  \
+    CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X}  \
+    CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X}  \
+    CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL}  \
+    CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_USB_RESET_POLARITY {Active Low}  \
+    CONFIG.PCW_ENET_RESET_POLARITY {Active Low}  \
+    CONFIG.PCW_I2C_RESET_POLARITY {Active Low}  \
+    CONFIG.PCW_MIO_0_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_0_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_0_SLEW {slow}  \
+    CONFIG.PCW_MIO_1_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_1_DIRECTION {out}  \
+    CONFIG.PCW_MIO_1_SLEW {fast}  \
+    CONFIG.PCW_MIO_2_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_2_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_2_SLEW {fast}  \
+    CONFIG.PCW_MIO_3_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_3_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_3_SLEW {fast}  \
+    CONFIG.PCW_MIO_4_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_4_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_4_SLEW {fast}  \
+    CONFIG.PCW_MIO_5_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_5_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_5_SLEW {fast}  \
+    CONFIG.PCW_MIO_6_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_6_DIRECTION {out}  \
+    CONFIG.PCW_MIO_6_SLEW {fast}  \
+    CONFIG.PCW_MIO_7_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_7_DIRECTION {out}  \
+    CONFIG.PCW_MIO_7_SLEW {slow}  \
+    CONFIG.PCW_MIO_8_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_8_DIRECTION {out}  \
+    CONFIG.PCW_MIO_8_SLEW {slow}  \
+    CONFIG.PCW_MIO_9_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_9_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_9_SLEW {slow}  \
+    CONFIG.PCW_MIO_10_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_10_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_10_SLEW {slow}  \
+    CONFIG.PCW_MIO_11_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_11_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_11_SLEW {slow}  \
+    CONFIG.PCW_MIO_12_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_12_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_12_SLEW {slow}  \
+    CONFIG.PCW_MIO_13_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_13_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_13_SLEW {slow}  \
+    CONFIG.PCW_MIO_14_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_14_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_14_SLEW {slow}  \
+    CONFIG.PCW_MIO_15_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_15_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_15_SLEW {slow}  \
+    CONFIG.PCW_MIO_16_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_16_IOTYPE {HSTL 1.8V}  \
+    CONFIG.PCW_MIO_16_DIRECTION {out}  \
+    CONFIG.PCW_MIO_16_SLEW {fast}  \
+    CONFIG.PCW_MIO_17_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_17_IOTYPE {HSTL 1.8V}  \
+    CONFIG.PCW_MIO_17_DIRECTION {out}  \
+    CONFIG.PCW_MIO_17_SLEW {fast}  \
+    CONFIG.PCW_MIO_18_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_18_IOTYPE {HSTL 1.8V}  \
+    CONFIG.PCW_MIO_18_DIRECTION {out}  \
+    CONFIG.PCW_MIO_18_SLEW {fast}  \
+    CONFIG.PCW_MIO_19_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_19_IOTYPE {HSTL 1.8V}  \
+    CONFIG.PCW_MIO_19_DIRECTION {out}  \
+    CONFIG.PCW_MIO_19_SLEW {fast}  \
+    CONFIG.PCW_MIO_20_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_20_IOTYPE {HSTL 1.8V}  \
+    CONFIG.PCW_MIO_20_DIRECTION {out}  \
+    CONFIG.PCW_MIO_20_SLEW {fast}  \
+    CONFIG.PCW_MIO_21_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_21_IOTYPE {HSTL 1.8V}  \
+    CONFIG.PCW_MIO_21_DIRECTION {out}  \
+    CONFIG.PCW_MIO_21_SLEW {fast}  \
+    CONFIG.PCW_MIO_22_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_22_IOTYPE {HSTL 1.8V}  \
+    CONFIG.PCW_MIO_22_DIRECTION {in}  \
+    CONFIG.PCW_MIO_22_SLEW {fast}  \
+    CONFIG.PCW_MIO_23_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_23_IOTYPE {HSTL 1.8V}  \
+    CONFIG.PCW_MIO_23_DIRECTION {in}  \
+    CONFIG.PCW_MIO_23_SLEW {fast}  \
+    CONFIG.PCW_MIO_24_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_24_IOTYPE {HSTL 1.8V}  \
+    CONFIG.PCW_MIO_24_DIRECTION {in}  \
+    CONFIG.PCW_MIO_24_SLEW {fast}  \
+    CONFIG.PCW_MIO_25_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_25_IOTYPE {HSTL 1.8V}  \
+    CONFIG.PCW_MIO_25_DIRECTION {in}  \
+    CONFIG.PCW_MIO_25_SLEW {fast}  \
+    CONFIG.PCW_MIO_26_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_26_IOTYPE {HSTL 1.8V}  \
+    CONFIG.PCW_MIO_26_DIRECTION {in}  \
+    CONFIG.PCW_MIO_26_SLEW {fast}  \
+    CONFIG.PCW_MIO_27_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_27_IOTYPE {HSTL 1.8V}  \
+    CONFIG.PCW_MIO_27_DIRECTION {in}  \
+    CONFIG.PCW_MIO_27_SLEW {fast}  \
+    CONFIG.PCW_MIO_28_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_28_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_28_SLEW {slow}  \
+    CONFIG.PCW_MIO_29_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_29_DIRECTION {in}  \
+    CONFIG.PCW_MIO_29_SLEW {slow}  \
+    CONFIG.PCW_MIO_30_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_30_DIRECTION {out}  \
+    CONFIG.PCW_MIO_30_SLEW {slow}  \
+    CONFIG.PCW_MIO_31_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_31_DIRECTION {in}  \
+    CONFIG.PCW_MIO_31_SLEW {slow}  \
+    CONFIG.PCW_MIO_32_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_32_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_32_SLEW {slow}  \
+    CONFIG.PCW_MIO_33_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_33_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_33_SLEW {slow}  \
+    CONFIG.PCW_MIO_34_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_34_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_34_SLEW {slow}  \
+    CONFIG.PCW_MIO_35_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_35_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_35_SLEW {slow}  \
+    CONFIG.PCW_MIO_36_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_36_DIRECTION {in}  \
+    CONFIG.PCW_MIO_36_SLEW {slow}  \
+    CONFIG.PCW_MIO_37_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_37_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_37_SLEW {slow}  \
+    CONFIG.PCW_MIO_38_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_38_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_38_SLEW {slow}  \
+    CONFIG.PCW_MIO_39_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_39_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_39_SLEW {slow}  \
+    CONFIG.PCW_MIO_40_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_40_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_40_SLEW {fast}  \
+    CONFIG.PCW_MIO_41_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_41_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_41_SLEW {fast}  \
+    CONFIG.PCW_MIO_42_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_42_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_42_SLEW {fast}  \
+    CONFIG.PCW_MIO_43_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_43_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_43_SLEW {fast}  \
+    CONFIG.PCW_MIO_44_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_44_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_44_SLEW {fast}  \
+    CONFIG.PCW_MIO_45_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_45_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_45_SLEW {fast}  \
+    CONFIG.PCW_MIO_46_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_46_DIRECTION {out}  \
+    CONFIG.PCW_MIO_46_SLEW {slow}  \
+    CONFIG.PCW_MIO_47_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_47_DIRECTION {in}  \
+    CONFIG.PCW_MIO_47_SLEW {slow}  \
+    CONFIG.PCW_MIO_48_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_48_DIRECTION {out}  \
+    CONFIG.PCW_MIO_48_SLEW {slow}  \
+    CONFIG.PCW_MIO_49_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_49_DIRECTION {in}  \
+    CONFIG.PCW_MIO_49_SLEW {slow}  \
+    CONFIG.PCW_MIO_50_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_50_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_50_SLEW {slow}  \
+    CONFIG.PCW_MIO_51_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_51_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_51_SLEW {slow}  \
+    CONFIG.PCW_MIO_52_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_52_DIRECTION {out}  \
+    CONFIG.PCW_MIO_52_SLEW {slow}  \
+    CONFIG.PCW_MIO_53_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_53_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_53_SLEW {slow}  \
+    CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA}  \
+    CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0}  \
+    CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#gpio[8]#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#tx#rx#gpio[50]#gpio[51]#mdc#mdio}  \
+    CONFIG.PCW_PS7_SI_REV {PRODUCTION}  \
+    CONFIG.PCW_FPGA_FCLK0_ENABLE {1}  \
+    CONFIG.PCW_FPGA_FCLK1_ENABLE {1}  \
+    CONFIG.PCW_FPGA_FCLK2_ENABLE {1}  \
+    CONFIG.PCW_FPGA_FCLK3_ENABLE {0}  \
+    CONFIG.PCW_NOR_SRAM_CS0_T_TR {1}  \
+    CONFIG.PCW_NOR_SRAM_CS0_T_PC {1}  \
+    CONFIG.PCW_NOR_SRAM_CS0_T_WP {1}  \
+    CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1}  \
+    CONFIG.PCW_NOR_SRAM_CS0_T_WC {11}  \
+    CONFIG.PCW_NOR_SRAM_CS0_T_RC {11}  \
+    CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0}  \
+    CONFIG.PCW_NOR_SRAM_CS1_T_TR {1}  \
+    CONFIG.PCW_NOR_SRAM_CS1_T_PC {1}  \
+    CONFIG.PCW_NOR_SRAM_CS1_T_WP {1}  \
+    CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1}  \
+    CONFIG.PCW_NOR_SRAM_CS1_T_WC {11}  \
+    CONFIG.PCW_NOR_SRAM_CS1_T_RC {11}  \
+    CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0}  \
+    CONFIG.PCW_NOR_CS0_T_TR {1}  \
+    CONFIG.PCW_NOR_CS0_T_PC {1}  \
+    CONFIG.PCW_NOR_CS0_T_WP {1}  \
+    CONFIG.PCW_NOR_CS0_T_CEOE {1}  \
+    CONFIG.PCW_NOR_CS0_T_WC {11}  \
+    CONFIG.PCW_NOR_CS0_T_RC {11}  \
+    CONFIG.PCW_NOR_CS0_WE_TIME {0}  \
+    CONFIG.PCW_NOR_CS1_T_TR {1}  \
+    CONFIG.PCW_NOR_CS1_T_PC {1}  \
+    CONFIG.PCW_NOR_CS1_T_WP {1}  \
+    CONFIG.PCW_NOR_CS1_T_CEOE {1}  \
+    CONFIG.PCW_NOR_CS1_T_WC {11}  \
+    CONFIG.PCW_NOR_CS1_T_RC {11}  \
+    CONFIG.PCW_NOR_CS1_WE_TIME {0}  \
+    CONFIG.PCW_NAND_CYCLES_T_RR {1}  \
+    CONFIG.PCW_NAND_CYCLES_T_AR {1}  \
+    CONFIG.PCW_NAND_CYCLES_T_CLR {1}  \
+    CONFIG.PCW_NAND_CYCLES_T_WP {1}  \
+    CONFIG.PCW_NAND_CYCLES_T_REA {1}  \
+    CONFIG.PCW_NAND_CYCLES_T_WC {11}  \
+    CONFIG.PCW_NAND_CYCLES_T_RC {11}  \
+    CONFIG.PCW_SMC_CYCLE_T0 {NA}  \
+    CONFIG.PCW_SMC_CYCLE_T1 {NA}  \
+    CONFIG.PCW_SMC_CYCLE_T2 {NA}  \
+    CONFIG.PCW_SMC_CYCLE_T3 {NA}  \
+    CONFIG.PCW_SMC_CYCLE_T4 {NA}  \
+    CONFIG.PCW_SMC_CYCLE_T5 {NA}  \
+    CONFIG.PCW_SMC_CYCLE_T6 {NA}  \
+    CONFIG.PCW_PACKAGE_NAME {clg400}  \
+    CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0}  \
+  ]
+}
+
+

projects/ax7020/ax7020_spi_loopback/README.md

@@ -0,0 +1,13 @@
+# README
+
+## 基本功能
+
+最开始开发本程序的想法是使用 SPI 0 作为 Master，使用 SPI 1 作为 Slave，实现 Master 下发、Slave echo 的功能，并基于 Xilinx SPI 实现 3-wire SPI 的支持。
+
+在开发软件程序的时候发现 Xilinx SPI 的功能比较复杂。在 Master 模式下，使用 `XSpiPs_PolledTransfer()` 可以驱动 SCLK 工作，会发送 Tx buffer 的数据到 MOSI 端口，并将 SCLK 持续过程中 MISO 端口的数据接收到 Rx buffer 中，过程中各端口的三态控制保持不变，因此无法使用三态信号控制 3-wire SPI 的 Input/Output 管脚。
+
+目前对于 3-wire SPI 的初步想法是先写后读，使用 1-bit GPIO 对 IO 管脚进行 tri-state 控制，但是这样会造成 SCLK 不连续，也会造成 CS 信号的中断，暂时无法确定对 Slave 的 SPI 状态机有无影响；CS 信号是否持续可以通过寄存器 `XSPIPS_FORCE_SSELECT_OPTION` 控制。
+
+## 扩展功能
+
+本程序还启用了两个 IIC Controller，同样想要开发使用 IIC 0 作为 Master，使用 IIC 1 作为 Slave，实现 Master 下发、Slave echo 的功能。

projects/ax7020/ax7020_spi_loopback/ax7020_spi_loopback.runs/impl_1/debug_nets.ltx

@@ -0,0 +1,428 @@
+{
+    "ltx_root": {
+        "version": 4,
+        "minor": 0,
+        "ltx_data": [
+            {
+                "name": "EDA_PROBESET",
+                "active": true,
+                "debug_cores": [
+                    {
+                        "type": "XSDB_V3",
+                        "name": "dbg_hub",
+                        "spec": "labtools_xsdbm_v3",
+                        "clk_input_freq_hz": "100000000"
+                    },
+                    {
+                        "type": "ILA_V3",
+                        "name": "system_bd_i/ila_0",
+                        "spec": "labtools_ila_v6",
+                        "ipName": "ila",
+                        "core_location": {
+                            "user_chain": 1,
+                            "slave_index": 0,
+                            "bscan_switch_index": 0
+                        },
+                        "uuid": "DEA337535A745DF2940B25E394985E07",
+                        "pins": [
+                            {
+                                "name": "probe0",
+                                "id": 0,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 0,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/processing_system7_0_SPI0_SCLK_O",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe1",
+                                "id": 1,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 1,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/processing_system7_0_SPI0_MOSI_O",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe2",
+                                "id": 2,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 2,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/processing_system7_0_SPI1_MISO_O",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe3",
+                                "id": 3,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 3,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/processing_system7_0_SPI0_SS_O",
+                                        "isBus": false
+                                    }
+                                ]
+                            }
+                        ]
+                    },
+                    {
+                        "type": "ILA_V3",
+                        "name": "system_bd_i/system_ila_1/inst/ila_lib",
+                        "spec": "labtools_ila_v6",
+                        "ipName": "ila",
+                        "core_location": {
+                            "user_chain": 1,
+                            "slave_index": 1,
+                            "bscan_switch_index": 0
+                        },
+                        "uuid": "4156E93C9EDF549FB62E4EFE498326AB",
+                        "pins": [
+                            {
+                                "name": "probe0",
+                                "id": 4,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 0,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_0_IIC_sda_i_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe1",
+                                "id": 5,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 1,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_0_IIC_sda_o_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe2",
+                                "id": 6,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 2,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_0_IIC_sda_t_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe3",
+                                "id": 7,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 3,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_0_IIC_scl_i_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe4",
+                                "id": 8,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 4,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_0_IIC_scl_o_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe5",
+                                "id": 9,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 5,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_0_IIC_scl_t_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe6",
+                                "id": 10,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 6,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_1_IIC_sda_i_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe7",
+                                "id": 11,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 7,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_1_IIC_sda_o_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe8",
+                                "id": 12,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 8,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_1_IIC_sda_t_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe9",
+                                "id": 13,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 9,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_1_IIC_scl_i_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe10",
+                                "id": 14,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 10,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_1_IIC_scl_o_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe11",
+                                "id": 15,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 11,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_1_IIC_scl_t_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            }
+                        ],
+                        "bus_interfaces": [
+                            {
+                                "name": "SLOT_0_IIC",
+                                "vlnv": "xilinx.com:interface:iic:1.0",
+                                "connectedBus": "processing_system7_0_IIC_0",
+                                "port_maps": [
+                                    {
+                                        "logical_port": "SCL_I",
+                                        "physical_pin": {
+                                            "id": 7,
+                                            "name": "probe3",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SCL_O",
+                                        "physical_pin": {
+                                            "id": 8,
+                                            "name": "probe4",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SCL_T",
+                                        "physical_pin": {
+                                            "id": 9,
+                                            "name": "probe5",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SDA_I",
+                                        "physical_pin": {
+                                            "id": 4,
+                                            "name": "probe0",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SDA_O",
+                                        "physical_pin": {
+                                            "id": 5,
+                                            "name": "probe1",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SDA_T",
+                                        "physical_pin": {
+                                            "id": 6,
+                                            "name": "probe2",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "SLOT_1_IIC",
+                                "vlnv": "xilinx.com:interface:iic:1.0",
+                                "connectedBus": "processing_system7_0_IIC_1",
+                                "port_maps": [
+                                    {
+                                        "logical_port": "SCL_I",
+                                        "physical_pin": {
+                                            "id": 13,
+                                            "name": "probe9",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SCL_O",
+                                        "physical_pin": {
+                                            "id": 14,
+                                            "name": "probe10",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SCL_T",
+                                        "physical_pin": {
+                                            "id": 15,
+                                            "name": "probe11",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SDA_I",
+                                        "physical_pin": {
+                                            "id": 10,
+                                            "name": "probe6",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SDA_O",
+                                        "physical_pin": {
+                                            "id": 11,
+                                            "name": "probe7",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SDA_T",
+                                        "physical_pin": {
+                                            "id": 12,
+                                            "name": "probe8",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    }
+                                ]
+                            }
+                        ]
+                    }
+                ]
+            }
+        ]
+    }
+}

projects/ax7020/ax7020_spi_loopback/ax7020_spi_loopback.runs/impl_1/system_bd_wrapper.ltx

@@ -0,0 +1,428 @@
+{
+    "ltx_root": {
+        "version": 4,
+        "minor": 0,
+        "ltx_data": [
+            {
+                "name": "EDA_PROBESET",
+                "active": true,
+                "debug_cores": [
+                    {
+                        "type": "XSDB_V3",
+                        "name": "dbg_hub",
+                        "spec": "labtools_xsdbm_v3",
+                        "clk_input_freq_hz": "100000000"
+                    },
+                    {
+                        "type": "ILA_V3",
+                        "name": "system_bd_i/ila_0",
+                        "spec": "labtools_ila_v6",
+                        "ipName": "ila",
+                        "core_location": {
+                            "user_chain": 1,
+                            "slave_index": 0,
+                            "bscan_switch_index": 0
+                        },
+                        "uuid": "DEA337535A745DF2940B25E394985E07",
+                        "pins": [
+                            {
+                                "name": "probe0",
+                                "id": 0,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 0,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/processing_system7_0_SPI0_SCLK_O",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe1",
+                                "id": 1,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 1,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/processing_system7_0_SPI0_MOSI_O",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe2",
+                                "id": 2,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 2,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/processing_system7_0_SPI1_MISO_O",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe3",
+                                "id": 3,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 3,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/processing_system7_0_SPI0_SS_O",
+                                        "isBus": false
+                                    }
+                                ]
+                            }
+                        ]
+                    },
+                    {
+                        "type": "ILA_V3",
+                        "name": "system_bd_i/system_ila_1/inst/ila_lib",
+                        "spec": "labtools_ila_v6",
+                        "ipName": "ila",
+                        "core_location": {
+                            "user_chain": 1,
+                            "slave_index": 1,
+                            "bscan_switch_index": 0
+                        },
+                        "uuid": "4156E93C9EDF549FB62E4EFE498326AB",
+                        "pins": [
+                            {
+                                "name": "probe0",
+                                "id": 4,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 0,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_0_IIC_sda_i_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe1",
+                                "id": 5,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 1,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_0_IIC_sda_o_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe2",
+                                "id": 6,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 2,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_0_IIC_sda_t_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe3",
+                                "id": 7,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 3,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_0_IIC_scl_i_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe4",
+                                "id": 8,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 4,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_0_IIC_scl_o_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe5",
+                                "id": 9,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 5,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_0_IIC_scl_t_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe6",
+                                "id": 10,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 6,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_1_IIC_sda_i_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe7",
+                                "id": 11,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 7,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_1_IIC_sda_o_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe8",
+                                "id": 12,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 8,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_1_IIC_sda_t_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe9",
+                                "id": 13,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 9,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_1_IIC_scl_i_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe10",
+                                "id": 14,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 10,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_1_IIC_scl_o_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "probe11",
+                                "id": 15,
+                                "type": "DATA_TRIGGER",
+                                "direction": "IN",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 11,
+                                "nets": [
+                                    {
+                                        "name": "system_bd_i/system_ila_1/inst/SLOT_1_IIC_scl_t_1",
+                                        "isBus": false
+                                    }
+                                ]
+                            }
+                        ],
+                        "bus_interfaces": [
+                            {
+                                "name": "SLOT_0_IIC",
+                                "vlnv": "xilinx.com:interface:iic:1.0",
+                                "connectedBus": "processing_system7_0_IIC_0",
+                                "port_maps": [
+                                    {
+                                        "logical_port": "SCL_I",
+                                        "physical_pin": {
+                                            "id": 7,
+                                            "name": "probe3",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SCL_O",
+                                        "physical_pin": {
+                                            "id": 8,
+                                            "name": "probe4",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SCL_T",
+                                        "physical_pin": {
+                                            "id": 9,
+                                            "name": "probe5",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SDA_I",
+                                        "physical_pin": {
+                                            "id": 4,
+                                            "name": "probe0",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SDA_O",
+                                        "physical_pin": {
+                                            "id": 5,
+                                            "name": "probe1",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SDA_T",
+                                        "physical_pin": {
+                                            "id": 6,
+                                            "name": "probe2",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    }
+                                ]
+                            },
+                            {
+                                "name": "SLOT_1_IIC",
+                                "vlnv": "xilinx.com:interface:iic:1.0",
+                                "connectedBus": "processing_system7_0_IIC_1",
+                                "port_maps": [
+                                    {
+                                        "logical_port": "SCL_I",
+                                        "physical_pin": {
+                                            "id": 13,
+                                            "name": "probe9",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SCL_O",
+                                        "physical_pin": {
+                                            "id": 14,
+                                            "name": "probe10",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SCL_T",
+                                        "physical_pin": {
+                                            "id": 15,
+                                            "name": "probe11",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SDA_I",
+                                        "physical_pin": {
+                                            "id": 10,
+                                            "name": "probe6",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SDA_O",
+                                        "physical_pin": {
+                                            "id": 11,
+                                            "name": "probe7",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    },
+                                    {
+                                        "logical_port": "SDA_T",
+                                        "physical_pin": {
+                                            "id": 12,
+                                            "name": "probe8",
+                                            "leftBit": 0,
+                                            "width": 1
+                                        }
+                                    }
+                                ]
+                            }
+                        ]
+                    }
+                ]
+            }
+        ]
+    }
+}

projects/ax7020/ax7020_spi_loopback/ax7020_spi_loopback.srcs/sources_1/bd/system_bd/ip/system_bd_xlconstant_0_0/system_bd_xlconstant_0_0.xci

@@ -0,0 +1,49 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_xlconstant_0_0",
+    "cell_name": "xlconstant_vcc",
+    "component_reference": "xilinx.com:ip:xlconstant:1.1",
+    "ip_revision": "8",
+    "gen_directory": "../../../../../../ax7020_spi_loopback.gen/sources_1/bd/system_bd/ip/system_bd_xlconstant_0_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "system_bd_xlconstant_0_0", "resolve_type": "user", "usage": "all" } ],
+        "CONST_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CONST_VAL": [ { "value": "1", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "CONST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "CONST_VAL": [ { "value": "0x1", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z020" } ],
+        "PACKAGE": [ { "value": "clg400" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "8" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../ax7020_spi_loopback.gen/sources_1/bd/system_bd/ip/system_bd_xlconstant_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "dout": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
+      }
+    }
+  }
+}

projects/ax7020/ax7020_spi_loopback/ax7020_spi_loopback.srcs/sources_1/bd/system_bd/system_bd.bda

@@ -0,0 +1,203 @@
+{
+    "graphjs": {
+        "version": "1.0",
+        "keys": [
+            {
+                "abrv": "VH",
+                "name": "vert_hid",
+                "type": "int",
+                "for": "node"
+            },
+            {
+                "abrv": "VM",
+                "name": "vert_name",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "VT",
+                "name": "vert_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "BA",
+                "name": "base_addr",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "HA",
+                "name": "high_addr",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "BP",
+                "name": "base_param",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "HP",
+                "name": "high_param",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MA",
+                "name": "master_addrspace",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MX",
+                "name": "master_instance",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MI",
+                "name": "master_interface",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MS",
+                "name": "master_segment",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MV",
+                "name": "master_vlnv",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "SX",
+                "name": "slave_instance",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "SI",
+                "name": "slave_interface",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MM",
+                "name": "slave_memmap",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "SS",
+                "name": "slave_segment",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "SV",
+                "name": "slave_vlnv",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "TM",
+                "name": "memory_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "TU",
+                "name": "usage_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "LT",
+                "name": "lock_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "BT",
+                "name": "boot_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "EH",
+                "name": "edge_hid",
+                "type": "int",
+                "for": "edge"
+            }
+        ],
+        "vertice_type_order": [
+            {
+                "abrv": "BC",
+                "desc": "Block Container"
+            },
+            {
+                "abrv": "PR",
+                "desc": "Parital Reference"
+            },
+            {
+                "abrv": "VR",
+                "desc": "Variant"
+            },
+            {
+                "abrv": "PM",
+                "desc": "Variant Permutations"
+            },
+            {
+                "abrv": "CX",
+                "desc": "Boundary Connection"
+            },
+            {
+                "abrv": "AC",
+                "desc": "Assignment Coordinate"
+            },
+            {
+                "abrv": "ACE",
+                "desc": "Excluded Assign Coordinate"
+            },
+            {
+                "abrv": "APX",
+                "desc": "Boundary Aperture"
+            },
+            {
+                "abrv": "CIP",
+                "desc": "High level Processing System"
+            }
+        ],
+        "vertices": {
+            "V0": {
+                "VM": "system_bd",
+                "VT": "BC"
+            },
+            "V1": {
+                "VH": "2",
+                "VM": "system_bd",
+                "VT": "VR"
+            },
+            "V2": {
+                "VH": "2",
+                "VT": "PM",
+                "TU": "active"
+            }
+        },
+        "edges": [
+            {
+                "src": "V0",
+                "trg": "V1"
+            },
+            {
+                "src": "V1",
+                "trg": "V2"
+            }
+        ]
+    }
+}

projects/ax7020/ax7020_spi_loopback/ax7020_spi_loopback.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui

@@ -0,0 +1,35 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"1.6245",
+   "Default View_TopLeft":"-322,-18",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
+#  -string -flagsOSRD
+preplace port DDR -pg 1 -lvl 3 -x 600 -y 60 -defaultsOSRD
+preplace port FIXED_IO -pg 1 -lvl 3 -x 600 -y 80 -defaultsOSRD
+preplace inst processing_system7_0 -pg 1 -lvl 1 -x 150 -y 290 -defaultsOSRD
+preplace inst system_ila_1 -pg 1 -lvl 2 -x 480 -y 180 -defaultsOSRD -resize 160 116
+preplace inst xlconstant_vcc -pg 1 -lvl 2 -x 480 -y 480 -defaultsOSRD -orient R180
+preplace inst ila_0 -pg 1 -lvl 2 -x 480 -y 340 -defaultsOSRD
+preplace netloc processing_system7_0_FCLK_CLK0 1 1 1 380 200n
+preplace netloc processing_system7_0_I2C0_SCL_O 1 1 1 300 160n
+preplace netloc processing_system7_0_I2C0_SDA_O 1 1 1 310 140n
+preplace netloc processing_system7_0_I2C1_SDA_O 1 1 1 350 120n
+preplace netloc xlconstant_0_dout 1 1 1 330 340n
+preplace netloc processing_system7_0_SPI0_SCLK_O 1 1 1 350 280n
+preplace netloc processing_system7_0_SPI0_MOSI_O 1 1 1 340 300n
+preplace netloc processing_system7_0_SPI0_SS_O 1 1 1 310 360n
+preplace netloc processing_system7_0_SPI1_MISO_O 1 1 1 320 320n
+preplace netloc processing_system7_0_DDR 1 1 2 NJ 60 N
+preplace netloc processing_system7_0_FIXED_IO 1 1 2 NJ 80 N
+preplace netloc processing_system7_0_IIC_0 1 1 1 360J 100n
+preplace netloc processing_system7_0_IIC_1 1 1 1 NJ 180
+levelinfo -pg 1 0 150 480 600
+pagesize -pg 1 -db -bbox -sgen 0 0 720 580
+"
+}
+{
+   "da_board_cnt":"1",
+   "da_clkrst_cnt":"2",
+   "da_ps7_cnt":"1"
+}

projects/ax7020/ax7020_spi_loopback/ax7020_spi_loopback.xpr

@@ -0,0 +1,315 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!--                                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
+<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+
+<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/Workspace/vivado/vivado_pub/projects/ax7020/ax7020_spi_loopback/ax7020_spi_loopback.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="c18ef9a92fea4fc68eba6ded4a199fe4"/>
+    <Option Name="Part" Val="xc7z020clg400-2"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
+    <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
+    <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
+    <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
+    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
+    <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="SimCompileState" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+  </Configuration>
+  <FileSets Version="1" Minor="32">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/bd/system_bd/system_bd.bd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+        <CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_ila_0_0/system_bd_ila_0_0.xci">
+          <Proxy FileSetName="system_bd_ila_0_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci">
+          <Proxy FileSetName="system_bd_processing_system7_0_0"/>
+        </CompFileExtendedInfo>
+      </File>
+      <File Path="$PGENDIR/sources_1/bd/system_bd/hdl/system_bd_wrapper.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="system_bd_wrapper"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="system_bd_wrapper"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <File Path="$PSRCDIR/utils_1/imports/synth_1/system_bd_wrapper.dcp">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedInSteps" Val="synth_1"/>
+          <Attr Name="AutoDcp" Val="1"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="system_bd_processing_system7_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_processing_system7_0_0" RelGenDir="$PGENDIR/system_bd_processing_system7_0_0">
+      <Config>
+        <Option Name="TopModule" Val="system_bd_processing_system7_0_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="system_bd_ila_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_ila_0_0" RelGenDir="$PGENDIR/system_bd_ila_0_0">
+      <Config>
+        <Option Name="TopModule" Val="system_bd_ila_0_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="21">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/system_bd_wrapper.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_bd_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_processing_system7_0_0" Part="xc7z020clg400-2" ConstrsSet="system_bd_processing_system7_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_processing_system7_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_bd_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_ila_0_0" Part="xc7z020clg400-2" ConstrsSet="system_bd_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_ila_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_ila_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_ila_0_0_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 18 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_bd_processing_system7_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="system_bd_processing_system7_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_processing_system7_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_bd_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="system_bd_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_ila_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_ila_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board/>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/.cproject

@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="org.eclipse.cdt.core.default.config.1693814654">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1693814654" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
+                				
+                <externalSettings/>
+                				
+                <extensions/>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    
+</cproject>

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/.gitignore

@@ -0,0 +1,3 @@
+/export/
+*.o
+*.d

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/.project

@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>ax7020_platform</name>
+	<comment>Created by Vitis v2023.2</comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.xilinx.sdx.scw.PlatformProjectBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.xilinx.sdx.scw.platformProject</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+	</natures>
+</projectDescription>

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/hw/ps7_init.h

@@ -0,0 +1,117 @@
+/******************************************************************************
+*
+* Copyright (C) 2010-2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  766666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158730
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  125000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  100000000
+#define UART_FREQ  100000000
+#define SPI_FREQ  166666672
+#define I2C_FREQ  127777779
+#define WDT_FREQ  127777786
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  100000000
+#define FPGA1_FREQ  10000000
+#define FPGA2_FREQ  10000000
+#define FPGA3_FREQ  10000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer(); 
+int get_number_of_cycles_for_delay(unsigned int delay); 
+#ifdef __cplusplus
+}
+#endif
+

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/hw/ps7_init.tcl

@@ -0,0 +1,838 @@
+proc ps7_pll_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA3C0
+    mask_write 0XF8000100 0x0007F000 0x0002E000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x001452C0
+    mask_write 0XF8000108 0x0007F000 0x0001E000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00700F01
+    mask_write 0XF8000138 0x00000011 0x00000001
+    mask_write 0XF8000140 0x03F03F71 0x00100801
+    mask_write 0XF800014C 0x00003F31 0x00000501
+    mask_write 0XF8000150 0x00003F33 0x00000A01
+    mask_write 0XF8000154 0x00003F33 0x00000A02
+    mask_write 0XF8000158 0x00003F33 0x00000603
+    mask_write 0XF8000168 0x00003F31 0x00000501
+    mask_write 0XF8000170 0x03F03F30 0x00200500
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x01ECC44D
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_3_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x0007FFFF 0x00001082
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004285B
+    mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
+    mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
+    mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
+    mask_write 0XF8006024 0x0FFFFFC3 0x00000000
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
+    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+    mask_write 0XF8006038 0x00000003 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+    mask_write 0XF8006048 0x0003F03F 0x0003C008
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x00010000 0x00000000
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF8006078 0x03FFFFFF 0x00466111
+    mask_write 0XF800607C 0x000FFFFF 0x00032222
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x00000200 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFCF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFCF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFCF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFCF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x00029000
+    mask_write 0XF8006130 0x000FFFFF 0x00029000
+    mask_write 0XF8006134 0x000FFFFF 0x00029000
+    mask_write 0XF8006138 0x000FFFFF 0x00029000
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x00000080
+    mask_write 0XF8006158 0x000FFFFF 0x00000080
+    mask_write 0XF800615C 0x000FFFFF 0x00000080
+    mask_write 0XF8006160 0x000FFFFF 0x00000080
+    mask_write 0XF8006168 0x001FFFFF 0x000000F9
+    mask_write 0XF800616C 0x001FFFFF 0x000000F9
+    mask_write 0XF8006170 0x001FFFFF 0x000000F9
+    mask_write 0XF8006174 0x001FFFFF 0x000000F9
+    mask_write 0XF800617C 0x000FFFFF 0x000000C0
+    mask_write 0XF8006180 0x000FFFFF 0x000000C0
+    mask_write 0XF8006184 0x000FFFFF 0x000000C0
+    mask_write 0XF8006188 0x000FFFFF 0x000000C0
+    mask_write 0XF8006190 0x6FFFFEFE 0x00040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000703FF 0x000003FF
+    mask_write 0XF800620C 0x000703FF 0x000003FF
+    mask_write 0XF8006210 0x000703FF 0x000003FF
+    mask_write 0XF8006214 0x000703FF 0x000003FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF5 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B00 0x00000071 0x00000001
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B6C 0x00007FFF 0x00000260
+    mask_write 0XF8000B70 0x00000001 0x00000001
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FEFFFF 0x00000823
+    mask_write 0XF8000700 0x00003FFF 0x00001600
+    mask_write 0XF8000704 0x00003FFF 0x00001702
+    mask_write 0XF8000708 0x00003FFF 0x00000702
+    mask_write 0XF800070C 0x00003FFF 0x00000702
+    mask_write 0XF8000710 0x00003FFF 0x00000702
+    mask_write 0XF8000714 0x00003FFF 0x00000702
+    mask_write 0XF8000718 0x00003FFF 0x00000702
+    mask_write 0XF800071C 0x00003FFF 0x00000600
+    mask_write 0XF8000720 0x00003FFF 0x00000600
+    mask_write 0XF8000724 0x00003FFF 0x00001600
+    mask_write 0XF8000728 0x00003FFF 0x00001600
+    mask_write 0XF800072C 0x00003FFF 0x00001600
+    mask_write 0XF8000730 0x00003FFF 0x00001600
+    mask_write 0XF8000734 0x00003FFF 0x00001600
+    mask_write 0XF8000738 0x00003FFF 0x00001600
+    mask_write 0XF800073C 0x00003FFF 0x00001600
+    mask_write 0XF8000740 0x00003FFF 0x00003902
+    mask_write 0XF8000744 0x00003FFF 0x00003902
+    mask_write 0XF8000748 0x00003FFF 0x00003902
+    mask_write 0XF800074C 0x00003FFF 0x00003902
+    mask_write 0XF8000750 0x00003FFF 0x00003902
+    mask_write 0XF8000754 0x00003FFF 0x00003902
+    mask_write 0XF8000758 0x00003FFF 0x00001903
+    mask_write 0XF800075C 0x00003FFF 0x00001903
+    mask_write 0XF8000760 0x00003FFF 0x00001903
+    mask_write 0XF8000764 0x00003FFF 0x00001903
+    mask_write 0XF8000768 0x00003FFF 0x00001903
+    mask_write 0XF800076C 0x00003FFF 0x00001903
+    mask_write 0XF8000770 0x00003FFF 0x00001204
+    mask_write 0XF8000774 0x00003FFF 0x00001205
+    mask_write 0XF8000778 0x00003FFF 0x00001204
+    mask_write 0XF800077C 0x00003FFF 0x00001205
+    mask_write 0XF8000780 0x00003FFF 0x00001204
+    mask_write 0XF8000784 0x00003FFF 0x00001204
+    mask_write 0XF8000788 0x00003FFF 0x00001204
+    mask_write 0XF800078C 0x00003FFF 0x00001204
+    mask_write 0XF8000790 0x00003FFF 0x00001205
+    mask_write 0XF8000794 0x00003FFF 0x00001204
+    mask_write 0XF8000798 0x00003FFF 0x00001204
+    mask_write 0XF800079C 0x00003FFF 0x00001204
+    mask_write 0XF80007A0 0x00003FFF 0x00001380
+    mask_write 0XF80007A4 0x00003FFF 0x00001380
+    mask_write 0XF80007A8 0x00003FFF 0x00001380
+    mask_write 0XF80007AC 0x00003FFF 0x00001380
+    mask_write 0XF80007B0 0x00003FFF 0x00001380
+    mask_write 0XF80007B4 0x00003FFF 0x00001380
+    mask_write 0XF80007B8 0x00003FFF 0x00001200
+    mask_write 0XF80007BC 0x00003F01 0x00001201
+    mask_write 0XF80007C0 0x00003FFF 0x000012E0
+    mask_write 0XF80007C4 0x00003FFF 0x000012E1
+    mask_write 0XF80007C8 0x00003FFF 0x00001200
+    mask_write 0XF80007CC 0x00003FFF 0x00001200
+    mask_write 0XF80007D0 0x00003FFF 0x00001280
+    mask_write 0XF80007D4 0x00003FFF 0x00001280
+    mask_write 0XF8000830 0x003F003F 0x002F0037
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mwr -force 0XF8000004 0x0000767B
+    mask_write 0XE0001034 0x000000FF 0x00000006
+    mask_write 0XE0001018 0x0000FFFF 0x0000007C
+    mask_write 0XE0001000 0x000001FF 0x00000017
+    mask_write 0XE0001004 0x000003FF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+    mask_write 0XE000A244 0x003FFFFF 0x00004000
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+    mask_write 0XE000A248 0x003FFFFF 0x00004000
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+}
+proc ps7_post_config_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_3_0 {} {
+    mwr -force 0XF8898FB0 0xC5ACCE55
+    mwr -force 0XF8899FB0 0xC5ACCE55
+    mwr -force 0XF8809FB0 0xC5ACCE55
+}
+proc ps7_pll_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA3C0
+    mask_write 0XF8000100 0x0007F000 0x0002E000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x001452C0
+    mask_write 0XF8000108 0x0007F000 0x0001E000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00700F01
+    mask_write 0XF8000138 0x00000011 0x00000001
+    mask_write 0XF8000140 0x03F03F71 0x00100801
+    mask_write 0XF800014C 0x00003F31 0x00000501
+    mask_write 0XF8000150 0x00003F33 0x00000A01
+    mask_write 0XF8000154 0x00003F33 0x00000A02
+    mask_write 0XF8000158 0x00003F33 0x00000603
+    mask_write 0XF8000168 0x00003F31 0x00000501
+    mask_write 0XF8000170 0x03F03F30 0x00200500
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x01ECC44D
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_2_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x1FFFFFFF 0x00081082
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004285B
+    mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
+    mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
+    mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
+    mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
+    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+    mask_write 0XF8006038 0x00001FC3 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+    mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x0001FFFF 0x00000101
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF8006078 0x03FFFFFF 0x00466111
+    mask_write 0XF800607C 0x000FFFFF 0x00032222
+    mask_write 0XF80060A0 0x00FFFFFF 0x00008000
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x000007FF 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFFF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFFF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x00029000
+    mask_write 0XF8006130 0x000FFFFF 0x00029000
+    mask_write 0XF8006134 0x000FFFFF 0x00029000
+    mask_write 0XF8006138 0x000FFFFF 0x00029000
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x00000080
+    mask_write 0XF8006158 0x000FFFFF 0x00000080
+    mask_write 0XF800615C 0x000FFFFF 0x00000080
+    mask_write 0XF8006160 0x000FFFFF 0x00000080
+    mask_write 0XF8006168 0x001FFFFF 0x000000F9
+    mask_write 0XF800616C 0x001FFFFF 0x000000F9
+    mask_write 0XF8006170 0x001FFFFF 0x000000F9
+    mask_write 0XF8006174 0x001FFFFF 0x000000F9
+    mask_write 0XF800617C 0x000FFFFF 0x000000C0
+    mask_write 0XF8006180 0x000FFFFF 0x000000C0
+    mask_write 0XF8006184 0x000FFFFF 0x000000C0
+    mask_write 0XF8006188 0x000FFFFF 0x000000C0
+    mask_write 0XF8006190 0xFFFFFFFF 0x10040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000F03FF 0x000803FF
+    mask_write 0XF800620C 0x000F03FF 0x000803FF
+    mask_write 0XF8006210 0x000F03FF 0x000803FF
+    mask_write 0XF8006214 0x000F03FF 0x000803FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF7 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B00 0x00000303 0x00000001
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B6C 0x00007FFF 0x00000260
+    mask_write 0XF8000B70 0x00000021 0x00000021
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FFFFFF 0x00000823
+    mask_write 0XF8000700 0x00003FFF 0x00001600
+    mask_write 0XF8000704 0x00003FFF 0x00001702
+    mask_write 0XF8000708 0x00003FFF 0x00000702
+    mask_write 0XF800070C 0x00003FFF 0x00000702
+    mask_write 0XF8000710 0x00003FFF 0x00000702
+    mask_write 0XF8000714 0x00003FFF 0x00000702
+    mask_write 0XF8000718 0x00003FFF 0x00000702
+    mask_write 0XF800071C 0x00003FFF 0x00000600
+    mask_write 0XF8000720 0x00003FFF 0x00000600
+    mask_write 0XF8000724 0x00003FFF 0x00001600
+    mask_write 0XF8000728 0x00003FFF 0x00001600
+    mask_write 0XF800072C 0x00003FFF 0x00001600
+    mask_write 0XF8000730 0x00003FFF 0x00001600
+    mask_write 0XF8000734 0x00003FFF 0x00001600
+    mask_write 0XF8000738 0x00003FFF 0x00001600
+    mask_write 0XF800073C 0x00003FFF 0x00001600
+    mask_write 0XF8000740 0x00003FFF 0x00003902
+    mask_write 0XF8000744 0x00003FFF 0x00003902
+    mask_write 0XF8000748 0x00003FFF 0x00003902
+    mask_write 0XF800074C 0x00003FFF 0x00003902
+    mask_write 0XF8000750 0x00003FFF 0x00003902
+    mask_write 0XF8000754 0x00003FFF 0x00003902
+    mask_write 0XF8000758 0x00003FFF 0x00001903
+    mask_write 0XF800075C 0x00003FFF 0x00001903
+    mask_write 0XF8000760 0x00003FFF 0x00001903
+    mask_write 0XF8000764 0x00003FFF 0x00001903
+    mask_write 0XF8000768 0x00003FFF 0x00001903
+    mask_write 0XF800076C 0x00003FFF 0x00001903
+    mask_write 0XF8000770 0x00003FFF 0x00001204
+    mask_write 0XF8000774 0x00003FFF 0x00001205
+    mask_write 0XF8000778 0x00003FFF 0x00001204
+    mask_write 0XF800077C 0x00003FFF 0x00001205
+    mask_write 0XF8000780 0x00003FFF 0x00001204
+    mask_write 0XF8000784 0x00003FFF 0x00001204
+    mask_write 0XF8000788 0x00003FFF 0x00001204
+    mask_write 0XF800078C 0x00003FFF 0x00001204
+    mask_write 0XF8000790 0x00003FFF 0x00001205
+    mask_write 0XF8000794 0x00003FFF 0x00001204
+    mask_write 0XF8000798 0x00003FFF 0x00001204
+    mask_write 0XF800079C 0x00003FFF 0x00001204
+    mask_write 0XF80007A0 0x00003FFF 0x00001380
+    mask_write 0XF80007A4 0x00003FFF 0x00001380
+    mask_write 0XF80007A8 0x00003FFF 0x00001380
+    mask_write 0XF80007AC 0x00003FFF 0x00001380
+    mask_write 0XF80007B0 0x00003FFF 0x00001380
+    mask_write 0XF80007B4 0x00003FFF 0x00001380
+    mask_write 0XF80007B8 0x00003FFF 0x00001200
+    mask_write 0XF80007BC 0x00003F01 0x00001201
+    mask_write 0XF80007C0 0x00003FFF 0x000012E0
+    mask_write 0XF80007C4 0x00003FFF 0x000012E1
+    mask_write 0XF80007C8 0x00003FFF 0x00001200
+    mask_write 0XF80007CC 0x00003FFF 0x00001200
+    mask_write 0XF80007D0 0x00003FFF 0x00001280
+    mask_write 0XF80007D4 0x00003FFF 0x00001280
+    mask_write 0XF8000830 0x003F003F 0x002F0037
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mwr -force 0XF8000004 0x0000767B
+    mask_write 0XE0001034 0x000000FF 0x00000006
+    mask_write 0XE0001018 0x0000FFFF 0x0000007C
+    mask_write 0XE0001000 0x000001FF 0x00000017
+    mask_write 0XE0001004 0x00000FFF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+    mask_write 0XE000A244 0x003FFFFF 0x00004000
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+    mask_write 0XE000A248 0x003FFFFF 0x00004000
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+}
+proc ps7_post_config_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_2_0 {} {
+    mwr -force 0XF8898FB0 0xC5ACCE55
+    mwr -force 0XF8899FB0 0xC5ACCE55
+    mwr -force 0XF8809FB0 0xC5ACCE55
+}
+proc ps7_pll_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA3C0
+    mask_write 0XF8000100 0x0007F000 0x0002E000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x001452C0
+    mask_write 0XF8000108 0x0007F000 0x0001E000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00700F01
+    mask_write 0XF8000138 0x00000011 0x00000001
+    mask_write 0XF8000140 0x03F03F71 0x00100801
+    mask_write 0XF800014C 0x00003F31 0x00000501
+    mask_write 0XF8000150 0x00003F33 0x00000A01
+    mask_write 0XF8000154 0x00003F33 0x00000A02
+    mask_write 0XF8000158 0x00003F33 0x00000603
+    mask_write 0XF8000168 0x00003F31 0x00000501
+    mask_write 0XF8000170 0x03F03F30 0x00200500
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x01ECC44D
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_1_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x1FFFFFFF 0x00081082
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004285B
+    mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
+    mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
+    mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
+    mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
+    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+    mask_write 0XF8006038 0x00001FC3 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+    mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x0001FFFF 0x00000101
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF80060A0 0x00FFFFFF 0x00008000
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x000007FF 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFFF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFFF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x00029000
+    mask_write 0XF8006130 0x000FFFFF 0x00029000
+    mask_write 0XF8006134 0x000FFFFF 0x00029000
+    mask_write 0XF8006138 0x000FFFFF 0x00029000
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x00000080
+    mask_write 0XF8006158 0x000FFFFF 0x00000080
+    mask_write 0XF800615C 0x000FFFFF 0x00000080
+    mask_write 0XF8006160 0x000FFFFF 0x00000080
+    mask_write 0XF8006168 0x001FFFFF 0x000000F9
+    mask_write 0XF800616C 0x001FFFFF 0x000000F9
+    mask_write 0XF8006170 0x001FFFFF 0x000000F9
+    mask_write 0XF8006174 0x001FFFFF 0x000000F9
+    mask_write 0XF800617C 0x000FFFFF 0x000000C0
+    mask_write 0XF8006180 0x000FFFFF 0x000000C0
+    mask_write 0XF8006184 0x000FFFFF 0x000000C0
+    mask_write 0XF8006188 0x000FFFFF 0x000000C0
+    mask_write 0XF8006190 0xFFFFFFFF 0x10040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000F03FF 0x000803FF
+    mask_write 0XF800620C 0x000F03FF 0x000803FF
+    mask_write 0XF8006210 0x000F03FF 0x000803FF
+    mask_write 0XF8006214 0x000F03FF 0x000803FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF7 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B00 0x00000303 0x00000001
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B6C 0x000073FF 0x00000260
+    mask_write 0XF8000B70 0x00000021 0x00000021
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FFFFFF 0x00000823
+    mask_write 0XF8000700 0x00003FFF 0x00001600
+    mask_write 0XF8000704 0x00003FFF 0x00001702
+    mask_write 0XF8000708 0x00003FFF 0x00000702
+    mask_write 0XF800070C 0x00003FFF 0x00000702
+    mask_write 0XF8000710 0x00003FFF 0x00000702
+    mask_write 0XF8000714 0x00003FFF 0x00000702
+    mask_write 0XF8000718 0x00003FFF 0x00000702
+    mask_write 0XF800071C 0x00003FFF 0x00000600
+    mask_write 0XF8000720 0x00003FFF 0x00000600
+    mask_write 0XF8000724 0x00003FFF 0x00001600
+    mask_write 0XF8000728 0x00003FFF 0x00001600
+    mask_write 0XF800072C 0x00003FFF 0x00001600
+    mask_write 0XF8000730 0x00003FFF 0x00001600
+    mask_write 0XF8000734 0x00003FFF 0x00001600
+    mask_write 0XF8000738 0x00003FFF 0x00001600
+    mask_write 0XF800073C 0x00003FFF 0x00001600
+    mask_write 0XF8000740 0x00003FFF 0x00003902
+    mask_write 0XF8000744 0x00003FFF 0x00003902
+    mask_write 0XF8000748 0x00003FFF 0x00003902
+    mask_write 0XF800074C 0x00003FFF 0x00003902
+    mask_write 0XF8000750 0x00003FFF 0x00003902
+    mask_write 0XF8000754 0x00003FFF 0x00003902
+    mask_write 0XF8000758 0x00003FFF 0x00001903
+    mask_write 0XF800075C 0x00003FFF 0x00001903
+    mask_write 0XF8000760 0x00003FFF 0x00001903
+    mask_write 0XF8000764 0x00003FFF 0x00001903
+    mask_write 0XF8000768 0x00003FFF 0x00001903
+    mask_write 0XF800076C 0x00003FFF 0x00001903
+    mask_write 0XF8000770 0x00003FFF 0x00001204
+    mask_write 0XF8000774 0x00003FFF 0x00001205
+    mask_write 0XF8000778 0x00003FFF 0x00001204
+    mask_write 0XF800077C 0x00003FFF 0x00001205
+    mask_write 0XF8000780 0x00003FFF 0x00001204
+    mask_write 0XF8000784 0x00003FFF 0x00001204
+    mask_write 0XF8000788 0x00003FFF 0x00001204
+    mask_write 0XF800078C 0x00003FFF 0x00001204
+    mask_write 0XF8000790 0x00003FFF 0x00001205
+    mask_write 0XF8000794 0x00003FFF 0x00001204
+    mask_write 0XF8000798 0x00003FFF 0x00001204
+    mask_write 0XF800079C 0x00003FFF 0x00001204
+    mask_write 0XF80007A0 0x00003FFF 0x00001380
+    mask_write 0XF80007A4 0x00003FFF 0x00001380
+    mask_write 0XF80007A8 0x00003FFF 0x00001380
+    mask_write 0XF80007AC 0x00003FFF 0x00001380
+    mask_write 0XF80007B0 0x00003FFF 0x00001380
+    mask_write 0XF80007B4 0x00003FFF 0x00001380
+    mask_write 0XF80007B8 0x00003FFF 0x00001200
+    mask_write 0XF80007BC 0x00003F01 0x00001201
+    mask_write 0XF80007C0 0x00003FFF 0x000012E0
+    mask_write 0XF80007C4 0x00003FFF 0x000012E1
+    mask_write 0XF80007C8 0x00003FFF 0x00001200
+    mask_write 0XF80007CC 0x00003FFF 0x00001200
+    mask_write 0XF80007D0 0x00003FFF 0x00001280
+    mask_write 0XF80007D4 0x00003FFF 0x00001280
+    mask_write 0XF8000830 0x003F003F 0x002F0037
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mwr -force 0XF8000004 0x0000767B
+    mask_write 0XE0001034 0x000000FF 0x00000006
+    mask_write 0XE0001018 0x0000FFFF 0x0000007C
+    mask_write 0XE0001000 0x000001FF 0x00000017
+    mask_write 0XE0001004 0x00000FFF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+    mask_write 0XE000A244 0x003FFFFF 0x00004000
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+    mask_write 0XE000A248 0x003FFFFF 0x00004000
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+}
+proc ps7_post_config_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_1_0 {} {
+    mwr -force 0XF8898FB0 0xC5ACCE55
+    mwr -force 0XF8899FB0 0xC5ACCE55
+    mwr -force 0XF8809FB0 0xC5ACCE55
+}
+set PCW_SILICON_VER_1_0 "0x0"
+set PCW_SILICON_VER_2_0 "0x1"
+set PCW_SILICON_VER_3_0 "0x2"
+set APU_FREQ  767000000
+
+
+
+proc mask_poll { addr mask } {
+    set count 1
+    set curval "0x[string range [mrd $addr] end-8 end]"
+    set maskedval [expr {$curval & $mask}]
+    while { $maskedval == 0 } {
+        set curval "0x[string range [mrd $addr] end-8 end]"
+        set maskedval [expr {$curval & $mask}]
+        set count [ expr { $count + 1 } ]
+        if { $count == 100000000 } {
+          puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
+          break
+        }
+    }
+}
+
+
+
+proc mask_delay { addr val } {
+    set delay  [ get_number_of_cycles_for_delay $val ]
+    perf_reset_and_start_timer
+    set curval "0x[string range [mrd $addr] end-8 end]"
+    set maskedval [expr {$curval < $delay}]
+    while { $maskedval == 1 } {
+        set curval "0x[string range [mrd $addr] end-8 end]"
+        set maskedval [expr {$curval < $delay}]
+    }
+    perf_reset_clock 
+}
+
+proc ps_version { } {
+    set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
+    set mask_sil_ver "0x[expr {$si_ver >> 28}]"
+    return $mask_sil_ver;
+}
+
+proc ps7_post_config {} {
+    set saved_mode [configparams force-mem-accesses]                  
+    configparams force-mem-accesses 1 
+    
+	variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+        ps7_post_config_1_0   
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+        ps7_post_config_2_0   
+    } else {
+        ps7_post_config_3_0   
+    }
+	configparams force-mem-accesses $saved_mode                                       
+}
+
+proc ps7_debug {} {
+    variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+        ps7_debug_1_0   
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+        ps7_debug_2_0   
+    } else {
+        ps7_debug_3_0   
+    }
+}
+proc ps7_init {} {
+    variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+            ps7_mio_init_data_1_0
+            ps7_pll_init_data_1_0
+            ps7_clock_init_data_1_0
+            ps7_ddr_init_data_1_0
+            ps7_peripherals_init_data_1_0
+            #puts "PCW Silicon Version : 1.0"
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+            ps7_mio_init_data_2_0
+            ps7_pll_init_data_2_0
+            ps7_clock_init_data_2_0
+            ps7_ddr_init_data_2_0
+            ps7_peripherals_init_data_2_0
+            #puts "PCW Silicon Version : 2.0"
+    } else {
+            ps7_mio_init_data_3_0
+            ps7_pll_init_data_3_0
+            ps7_clock_init_data_3_0
+            ps7_ddr_init_data_3_0
+            ps7_peripherals_init_data_3_0
+            #puts "PCW Silicon Version : 3.0"
+    }
+}
+
+
+# For delay calculation using global timer 
+
+# start timer 
+ proc perf_start_clock { } {
+
+    #writing SCU_GLOBAL_TIMER_CONTROL register
+
+    mask_write 0xF8F00208 0x00000109 0x00000009
+}
+
+# stop timer and reset timer count regs 
+ proc perf_reset_clock { } {
+	perf_disable_clock
+    mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
+    mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
+}
+
+# Compute mask for given delay in miliseconds
+proc get_number_of_cycles_for_delay { delay } {
+
+  # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+  variable APU_FREQ
+  return [ expr ($delay * $APU_FREQ /(2 * 1000))]
+}
+
+
+# stop timer 
+proc perf_disable_clock {} {
+    mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 
+}
+
+proc perf_reset_and_start_timer {} {
+  	    perf_reset_clock 
+	    perf_start_clock 
+}
+
+

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/hw/ps7_init_gpl.h

@@ -0,0 +1,131 @@
+/******************************************************************************
+*
+* Copyright (C) 2010-2020 <Xilinx Inc.>
+* 
+*  This program is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License as published by
+*  the Free Software Foundation; either version 2 of the License, or
+*  (at your option) any later version.
+*
+*  This program is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*  GNU General Public License for more details.
+* 
+*  You should have received a copy of the GNU General Public License along
+*  with this program; if not, see <http://www.gnu.org/licenses/>
+* 
+* 
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  766666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158730
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  125000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  100000000
+#define UART_FREQ  100000000
+#define SPI_FREQ  166666672
+#define I2C_FREQ  127777779
+#define WDT_FREQ  127777786
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  100000000
+#define FPGA1_FREQ  10000000
+#define FPGA2_FREQ  10000000
+#define FPGA3_FREQ  10000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer(); 
+int get_number_of_cycles_for_delay(unsigned int delay); 
+#ifdef __cplusplus
+}
+#endif
+

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/platform.spr

@@ -0,0 +1 @@
+{"platformName":"ax7020_platform","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"ax7020_platform","platHandOff":"/home/josh/Workspace/vivado/vivado_pub/projects/ax7020/ax7020_spi_loopback/system_bd_wrapper.xsa","platIntHandOff":"<platformDir>/hw/system_bd_wrapper.xsa","deviceType":"zynq","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","fsblExtraCompilerFlags":"-MMD -MP       -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"ax7020_platform","systems":[{"systemName":"ax7020_platform","systemDesc":"ax7020_platform","sysIsBootAutoGen":"true","systemDispName":"ax7020_platform","sysActiveDom":"standalone_domain","sysDefaultDom":"standalone_domain","domains":[{"domainName":"zynq_fsbl","domainDispName":"zynq_fsbl","domainDesc":"FSBL Application BSP - Auto Generated.","processors":"ps7_cortexa9_0","os":"standalone","sdxOs":"standalone","debugEnable":"","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.0","mssFile":"","md5Digest":"04033c47e09287081b4db90f42ca4f251","compatibleApp":"zynq_fsbl","domType":"bootDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilffs:5.1","xilrsa:1.7"],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_domain","domainDispName":"standalone on ps7_cortexa9_0","domainDesc":"standalone_domain","processors":"ps7_cortexa9_0","os":"standalone","sdxOs":"standalone","qemuArgs":"<platformDir>/resources/ax7020_platform/standalone_domain/qemu_args.txt","qemuData":"<platformDir>/resources/ax7020_platform/standalone_domain/qemu","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.0","mssFile":"","md5Digest":"3c8ea8c7d7702deb3c198ce1c999e722","compatibleApp":"","domType":"mssDomain","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/platform.tcl

@@ -0,0 +1,37 @@
+# 
+# Usage: To re-create this platform project launch xsct with below options.
+# xsct /home/josh/Workspace/vivado/vivado_pub/projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/platform.tcl
+# 
+# OR launch xsct and run below command.
+# source /home/josh/Workspace/vivado/vivado_pub/projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/platform.tcl
+# 
+# To create the platform in a different location, modify the -out option of "platform create" command.
+# -out option specifies the output directory of the platform project.
+
+platform create -name {ax7020_platform}\
+-hw {/home/josh/Workspace/vivado/vivado_pub/projects/ax7020/ax7020_spi_loopback/ax7020_spi_loopback.xsa}\
+-proc {ps7_cortexa9_0} -os {standalone} -out {/home/josh/Workspace/vivado/vivado_pub/projects/ax7020/ax7020_spi_loopback/vitis}
+
+platform write
+platform generate -domains 
+platform active {ax7020_platform}
+bsp reload
+platform generate
+domain active {zynq_fsbl}
+domain active {standalone_domain}
+bsp reload
+bsp reload
+platform generate -domains 
+platform config -updatehw {/home/josh/Workspace/vivado/vivado_pub/projects/ax7020/ax7020_spi_loopback/ax7020_spi_loopback.xsa}
+platform generate -domains 
+platform config -updatehw {/home/josh/Workspace/vivado/vivado_pub/projects/ax7020/ax7020_spi_loopback/system_bd_wrapper.xsa}
+platform generate -domains 
+platform config -updatehw {/home/josh/Workspace/vivado/vivado_pub/projects/ax7020/ax7020_spi_loopback/system_bd_wrapper.xsa}
+platform generate -domains 
+platform config -updatehw {/home/josh/Workspace/vivado/vivado_pub/projects/ax7020/ax7020_spi_loopback/system_bd_wrapper.xsa}
+platform generate -domains 
+bsp reload
+platform generate -domains 
+domain active {zynq_fsbl}
+bsp reload
+bsp reload

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/ps7_cortexa9_0/standalone_domain/bsp/Makefile

@@ -0,0 +1,49 @@
+# Makefile generated by Xilinx.
+
+DRIVER_LIB_VERSION = 1.0
+PROCESSOR = ps7_cortexa9_0
+LIBRARIES = ${PROCESSOR}/lib/libxil.a
+BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
+SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
+BSP_SEQUENTIAL_MAKEFILES := 
+BSP_PARALLEL_MAKEFILES := $(filter-out $(BSP_SEQUENTIAL_MAKEFILES),$(BSP_MAKEFILES))
+SEQ_SUBDIRS := $(patsubst %/Makefile, %, $(BSP_SEQUENTIAL_MAKEFILES))
+PAR_SUBDIRS := $(patsubst %/Makefile, %, $(BSP_PARALLEL_MAKEFILES))
+
+ifneq (,$(findstring win,$(RDI_PLATFORM)))
+ SHELL = CMD
+endif
+
+all: 
+	$(MAKE) --no-print-directory seq_libs
+	$(MAKE) -j 18 --no-print-directory par_libs
+	$(MAKE) --no-print-directory archive
+	@echo 'Finished building libraries'
+
+include: $(addsuffix /make.include,$(SUBDIRS))
+
+seq_libs: $(addsuffix /make.libs,$(SEQ_SUBDIRS))
+	@echo 'Finished building libraries sequentially.'
+
+par_libs: $(addsuffix /make.libs,$(PAR_SUBDIRS))
+	@echo 'Finished building libraries parallelly.'
+
+archive:
+	arm-none-eabi-ar -r  $(LIBRARIES) $(sort $(wildcard $(PROCESSOR)/lib/*.o))
+
+clean: $(addsuffix /make.clean,$(SUBDIRS))
+	rm -f ${PROCESSOR}/lib/libxil.a
+
+$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
+	cp -f $< $@
+
+%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
+	@echo "Running Make include in $(subst /make.include,,$@)"
+	$(MAKE) -C $(subst /make.include,,$@) -s include  "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
+
+%/make.libs: include
+	@echo "Running Make libs in $(subst /make.libs,,$@)"
+	$(MAKE) -C $(subst /make.libs,,$@) -s libs  "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
+
+%/make.clean: 
+	$(MAKE) -C $(subst /make.clean,,$@) -s clean 

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/ps7_cortexa9_0/standalone_domain/bsp/dep.mk

@@ -0,0 +1,3 @@
+#  generated by Xilinx.
+
+DEPENDENCY_FLAGS= -MMD -MP

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/_profile_timer_hw.h

@@ -0,0 +1,281 @@
+/******************************************************************************
+* Copyright (c) 2004 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+
+#ifndef PROFILE_TIMER_HW_H
+#define PROFILE_TIMER_HW_H
+
+#include "profile.h"
+
+#ifdef PROC_PPC
+#if defined __GNUC__
+#  define SYNCHRONIZE_IO __asm__ volatile ("eieio")
+#elif defined __DCC__
+#  define SYNCHRONIZE_IO __asm volatile(" eieio")
+#else
+#  define SYNCHRONIZE_IO
+#endif
+#endif
+
+#ifdef PROC_PPC
+#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
+#else
+#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
+#endif
+
+#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
+	ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] +	\
+			   (u32)(RegOffset)), (u32)(ValueToWrite))
+
+#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset)	\
+	ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
+
+#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
+	ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,     \
+					   (RegisterValue))
+
+#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber)		\
+	ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PROC_PPC
+#include "xexception_l.h"
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif	/* TIMER_CONNECT_INTC */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+#ifdef PROC_CORTEXA9
+#include "xscutimer_hw.h"
+#include "xscugic.h"
+#endif
+
+extern u32 timer_clk_ticks ;
+
+/*--------------------------------------------------------------------
+ * PowerPC Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_PPC
+
+#ifdef PPC_PIT_INTERRUPT
+u32 timer_lo_clk_ticks ;	/* Clk ticks when Timer is disabled in CG */
+#endif
+
+#ifdef PROC_PPC440
+#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
+#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
+#define XREG_SPR_PIT XREG_SPR_DEC
+#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
+#endif
+
+/* --------------------------------------------------------------------
+ * Disable the Timer - During Profiling
+ *
+ * For PIT Timer -
+ *	1. XTime_PITDisableInterrupt() ;
+ *	2. Store the remaining timer clk tick
+ *	3. Stop the PIT Timer
+ *-------------------------------------------------------------------- */
+
+#ifdef PPC_PIT_INTERRUPT
+#define disable_timer() 		\
+	{				\
+		u32 val;	\
+		val=mfspr(XREG_SPR_TCR);	\
+		mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE));	\
+		timer_lo_clk_ticks = mfspr(XREG_SPR_PIT);			\
+		mtspr(XREG_SPR_PIT, 0);	\
+	}
+#else
+#define disable_timer() 	\
+   { \
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+   }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer
+ *
+ * For PIT Timer -
+ *	1. Load the remaining timer clk ticks
+ *	2. XTime_PITEnableInterrupt() ;
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define enable_timer()				\
+	{					\
+		u32 val;		\
+		val=mfspr(XREG_SPR_TCR);	\
+		mtspr(XREG_SPR_PIT, timer_lo_clk_ticks);	\
+		mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
+	}
+#else
+#define enable_timer()						\
+	{							\
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v |  XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+	}
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ * For PIT Timer -
+ * 	1. Load the timer clk ticks
+ *	2. Enable AutoReload and Interrupt
+ *	3. Clear PIT Timer Status bits
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define timer_ack()							\
+	{								\
+		u32 val;					\
+		mtspr(XREG_SPR_PIT, timer_clk_ticks);			\
+		mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS);	\
+		val=mfspr(XREG_SPR_TCR);				\
+		mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
+	}
+#else
+#define timer_ack()				\
+	{						\
+		u32 csr;			\
+		csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0);	\
+		ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr);	\
+	}
+#endif
+
+/*-------------------------------------------------------------------- */
+#endif	/* PROC_PPC */
+/* -------------------------------------------------------------------- */
+
+
+
+
+/* --------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer()					\
+	{						\
+      u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+	  Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+	  Addr += (u32)XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(Addr); \
+      tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
+      u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
+      OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+      OutAddr += (u32)XTC_TCSR_OFFSET; \
+      ProfIo_Out32(OutAddr, (u32)tmp_v); \
+    }
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer()					\
+	{						\
+      u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+	  Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+	  Addr += (u32)XTC_TCSR_OFFSET; \
+      u32 tmp_v = (u32)ProfIo_In32(Addr); \
+      tmp_v = tmp_v |  (u32)XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
+	}
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack()				\
+	{						\
+		u32 csr;			\
+		csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0);	\
+		ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr);	\
+	}
+
+/*-------------------------------------------------------------------- */
+#endif	/* PROC_MICROBLAZE */
+/*-------------------------------------------------------------------- */
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer()							\
+{								\
+	u32 Reg;							\
+	Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+	Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
+	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer()							\
+{								\
+	u32 Reg;							\
+	Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+	Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
+	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack()						\
+{							\
+	Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
+		(u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
+}
+
+/*-------------------------------------------------------------------- */
+#endif	/* PROC_CORTEXA9 */
+/*-------------------------------------------------------------------- */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/bspconfig.h

@@ -0,0 +1,24 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2023.2.1
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2024 Xilinx, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT 
+
+* 
+* Description: Configurations for Standalone BSP
+*
+*******************************************************************/
+
+#ifndef BSPCONFIG_H  /* prevent circular inclusions */
+#define BSPCONFIG_H  /* by using protection macros */
+
+#define MICROBLAZE_PVR_NONE
+
+/* Definition for hard-float ABI */
+#define FPU_HARD_FLOAT_ABI_ENABLED 1
+
+#endif /*end of __BSPCONFIG_H_*/

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/mblaze_nt_types.h

@@ -0,0 +1,28 @@
+/******************************************************************************
+* Copyright (c) 2002 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+
+
+#ifndef _MBLAZE_NT_TYPES_H
+#define _MBLAZE_NT_TYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef char            byte;
+typedef short           half;
+typedef int             word;
+typedef unsigned char   ubyte;
+typedef unsigned short  uhalf;
+typedef unsigned int    uword;
+typedef ubyte           boolean;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/pm_api_version.h

@@ -0,0 +1,269 @@
+/******************************************************************************
+* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+ * @file pm_api_version.h
+ *
+ * @addtogroup xpm_versal_apis XilPM APIs
+ *****************************************************************************/
+
+
+#ifndef PM_API_VERSION_H_
+#define PM_API_VERSION_H_
+
+/*****************************************************************************/
+/**
+ * @section EEMI_API_DETAIL XilPM EEMI API Version Detail
+ *
+ * This section provides details of EEMI API version and it's history for PM APIs of XilPM library.
+ *
+ * | NAME			| ID	| Platform	| Version| Description								     |
+ * |----------------------------|-------|---------------|:------:|---------------------------------------------------------------------------|
+ * | PM_GET_API_VERSION		| 0x1   | Both		| 1	 | The API is used to request the version number of the API		     |
+ * | PM_SET_CONFIGURATION	| 0x2	| ZynqMP	| 1	 | The API is used to configure the power management framework		     |
+ * | ^				| ^	| ^		| ^	 | Note: Deprecated in Versal but supported in ZynqMP			     |
+ * | PM_GET_NODE_STATUS		| 0x3	| Both		| 1	 | The API is used to obtain information about current status of a device    |
+ * | PM_GET_OP_CHARACTERISTIC	| 0x4	| Both		| 2	 | V1 - The API is used to get operating characteristics of a device	     |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of bitmask functionality, user can check the supported\n									"type" first before performing the actual functionality				       |
+ * | PM_REGISTER_NOTIFIER	| 0x5	| Both		| 2	 | V1 - The API is used to register a subsystem to be notified about the\n									device event									       |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of event management functionality			     |
+ * | ^				| ^	| ^		| ^	 | Note: V2 is supported in Versal but ZynqMP supports only V1		     |
+ * | PM_REQUEST_SUSPEND		| 0x6	| Both		| 1	 | The API is used to send suspend request to another subsystem		     |
+ * | PM_SELF_SUSPEND		| 0x7	| Both		| 2	 | V1 - The API is used to suspend a child subsystem			     |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of cpu idle functionality during force powerdown	     |
+ * | ^				| ^	| ^		| ^	 | Note: V2 is supported in Versal but ZynqMP supports only V1		     |
+ * | PM_FORCE_POWERDOWN		| 0x8	| Both		| 2	 | V1 - The API is used to Powerdown other processor or node		     |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of cpu idle functionality	during force powerdown	     |
+ * | ^				| ^	| ^		| ^	 | Note: V2 is supported in Versal but ZynqMP supports only V1		     |
+ * | PM_ABORT_SUSPEND		| 0x9	| Both		| 1	 | The API is used by a subsystem to abort suspend of a child subsystem	     |
+ * | PM_REQUEST_WAKEUP		| 0xA	| Both		| 1	 | The API is used to start-up and wake-up a child subsystem		     |
+ * | PM_SET_WAKEUP_SOURCE	| 0xB	| Both		| 1	 | The API is used to set wakeup source					     |
+ * | PM_SYSTEM_SHUTDOWN		| 0xC	| Both		| 1	 | The API is used to shutdown or restart the system			     |
+ * | PM_REQUEST_NODE		| 0xD	| Both		| 2	 | V1 - The API is used to request the usage of a device		     |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of security policy handling during request device	     |
+ * | ^				| ^	| ^		| ^	 | Note: V2 is supported in Versal but ZynqMP supports only V1		     |
+ * | PM_RELEASE_NODE		| 0xE	| Both		| 2	 | V1 - The API is used to release the usage of a device		     |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of security policy handling during request device      |
+ * | ^				| ^	| ^		| ^	 | Note: V2 is supported in Versal but ZynqMP supports only V1		     |
+ * | PM_SET_REQUIREMENT		| 0xF	| Both		| 1	 | The API is used to announce a change in requirement for a specific slave\n									node which is currently in use							       |
+ * | PM_SET_MAX_LATENCY		| 0x10	| Both		| 1	 | The API is used to set maximum allowed latency for the device	     |
+ * | PM_RESET_ASSERT		| 0x11	| Both		| 1	 | The API is used to reset or de-reset a device			     |
+ * | PM_RESET_GET_STATUS	| 0x12	| Both		| 1	 | The API is used to read the device reset state			     |
+ * | PM_MMIO_WRITE		| 0x13	| ZynqMP	| 1	 | The API is used to write a value into a register			     |
+ * | ^				| ^	| ^		| ^	 | Note: Deprecated in Versal but supported in ZynqMP			     |
+ * | PM_MMIO_READ		| 0x14	| ZynqMP	| 1	 | The API is used to read a value from a register			     |
+ * | ^				| ^	| ^		| ^	 | Note: Deprecated in Versal but supported in ZynqMP			     |
+ * | PM_INIT_FINALIZE		| 0x15	| Both		| 1	 | The API is used to initialize subsystem and release unused devices	     |
+ * | PM_GET_CHIPID		| 0x18	| Both		| 1	 | The API is used to request the version and ID code of a chip		     |
+ * | PM_PINCTRL_REQUEST		| 0x1C	| Both		| 1	 | The API is used to request the pin					     |
+ * | PM_PINCTRL_RELEASE		| 0x1D	| Both		| 1	 | The API is used to release the pin					     |
+ * | PM_PINCTRL_GET_FUNCTION	| 0x1E	| Both		| 1	 | The API is used to read the pin function				     |
+ * | PM_PINCTRL_SET_FUNCTION	| 0x1F	| Both		| 1	 | The API is used to set the pin function				     |
+ * | PM_PINCTRL_CONFIG_PARAM_GET| 0x20	| Both		| 1	 | The API is used to read the pin parameter value			     |
+ * | PM_PINCTRL_CONFIG_PARAM_SET| 0x21	| Both		| 2	 | V1 - The API is used to set the pin parameter value			     |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of MIO tri-state controlling functionality	     |
+ * | ^				| ^	| ^		| ^	 | Note: V2 is supported in ZynqMP but Versal supports only V1		     |
+ * | PM_IOCTL			| 0x22	| Both		| 3	 | V1 - The API is used to perform driver-like IOCTL functions on shared\n									system devices									       |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of bitmask functionality, user can check the supported\n									ID first before performing the actual functionality				       |
+ * | ^				| ^	| ^		| ^	 | V3 - Add support of zeroization of AIE data and program memory separately |
+ * | ^				| ^	| ^		| ^	 | Note: V3 is supported in Versal but ZynqMP supports only V2	             |
+ * | PM_QUERY_DATA		| 0x23	| Both		| 2	 | V1 - The API is used to query information about the platform resources  |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of bitmask functionality, user can check the supported\n									ID first before performing the actual functionality				       |
+ * | PM_CLOCK_ENABLE		| 0x24	| Both		| 1	 | The API is used to enable the clock					     |
+ * | PM_CLOCK_DISABLE		| 0x25	| Both		| 1	 | The API is used to disable the clock					     |
+ * | PM_CLOCK_GETSTATE		| 0x26	| Both		| 1	 | The API is used to read the clock state				     |
+ * | PM_CLOCK_SETDIVIDER	| 0x27	| Both		| 1	 | The API is used to set the divider value of the clock		     |
+ * | PM_CLOCK_GETDIVIDER	| 0x28	| Both		| 1	 | The API is used to read the clock divider				     |
+ * | PM_CLOCK_SETPARENT		| 0x2B	| Both		| 1	 | The API is used to set the parent of the clock			     |
+ * | PM_CLOCK_GETPARENT		| 0x2C	| Both		| 1	 | The API is used to read the clock parent				     |
+ * | PM_PLL_SET_PARAM		| 0x30	| Both		| 1	 | The API is used to set the parameter of PLL clock			     |
+ * | PM_PLL_GET_PARAM		| 0x31	| Both		| 1	 | The API is used to read the parameter of PLL clock			     |
+ * | PM_PLL_SET_MODE		| 0x32	| Both		| 1	 | The API is used to set the mode of PLL clock				     |
+ * | PM_PLL_GET_MODE		| 0x33	| Both		| 1	 | The API is used to read the mode of PLL clock			     |
+ * | PM_REGISTER_ACCESS		| 0x34	| ZynqMP	| 1	 | The API is used for register read/write access data			     |
+ * | ^				| ^	| ^		| ^	 | Note: Deprecated in Versal but supported in ZynqMP			     |
+ * | PM_EFUSE_ACCESS		| 0x35	| ZynqMP	| 1	 | The API is used to provide access to efuse memory			     |
+ * | ^				| ^	| ^		| ^	 | Note: Deprecated in Versal but supported in ZynqMP			     |
+ * | PM_FEATURE_CHECK		| 0x3F	| Both		| 2	 | V1 - The API is used to return supported version of the given API	     |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of bitmask payload functionality			     |
+ *
+ *****************************************************************************/
+
+/*****************************************************************************/
+/**
+ * @section IOCTL_ID_DETAIL XilPM IOCTL IDs Detail
+ *
+ * This section provides the details of the IOCTL IDs which are supported across the different platforms and their brief descriptions.
+ *
+ * | Name				| ID	| Platform	| Description				|
+ * |------------------------------------|-------|---------------|---------------------------------------|
+ * | IOCTL_GET_RPU_OPER_MODE		| 0	| Both		| Get RPU mode				|
+ * | IOCTL_SET_RPU_OPER_MODE		| 1	| Both		| Set RPU mode				|
+ * | IOCTL_RPU_BOOT_ADDR_CONFIG		| 2	| Both		| RPU boot address config		|
+ * | IOCTL_TCM_COMB_CONFIG		| 3	| Both		| TCM config				|
+ * | IOCTL_SET_TAPDELAY_BYPASS		| 4	| Both		| TAP delay bypass			|
+ * | IOCTL_SET_SGMII_MODE		| 5	| ZynqMP	| SGMII mode				|
+ * | IOCTL_SD_DLL_RESET			| 6	| Both		| SD DLL reset				|
+ * | IOCTL_SET_SD_TAPDELAY		| 7	| Both		| SD TAP delay				|
+ * | IOCTL_SET_PLL_FRAC_MODE		| 8	| Both		| Set PLL frac mode			|
+ * | IOCTL_GET_PLL_FRAC_MODE		| 9	| Both		| Get PLL frac mode			|
+ * | IOCTL_SET_PLL_FRAC_DATA		| 10	| Both		| Set PLL frac data			|
+ * | IOCTL_GET_PLL_FRAC_DATA		| 11	| Both		| Get PLL frac data			|
+ * | IOCTL_WRITE_GGS			| 12	| Both		| Write GGS				|
+ * | IOCTL_READ_GGS			| 13	| Both		| Read GGS				|
+ * | IOCTL_WRITE_PGGS			| 14	| Both		| Write PGGS				|
+ * | IOCTL_READ_PGGS			| 15	| Both		| Read PGGS				|
+ * | IOCTL_ULPI_RESET			| 16	| ZynqMP	| ULPI reset				|
+ * | IOCTL_SET_BOOT_HEALTH_STATUS	| 17	| Both		| Set boot status			|
+ * | IOCTL_AFI				| 18	| ZynqMP	| AFI					|
+ * | IOCTL_PROBE_COUNTER_READ		| 19	| Versal	| Probe counter read			|
+ * | IOCTL_PROBE_COUNTER_WRITE		| 20	| Versal	| Probe counter write			|
+ * | IOCTL_OSPI_MUX_SELECT		| 21	| Versal	| OSPI mux select			|
+ * | IOCTL_USB_SET_STATE		| 22	| Versal	| USB set state				|
+ * | IOCTL_GET_LAST_RESET_REASON	| 23	| Versal	| Get last reset reason			|
+ * | IOCTL_AIE_ISR_CLEAR		| 24	| Versal	| AIE ISR clear				|
+ * | IOCTL_REGISTER_SGI			| 25	| None		| Register SGI to ATF			|
+ * | IOCTL_SET_FEATURE_CONFIG		| 26	| ZynqMP	| Set runtime feature config		|
+ * | IOCTL_GET_FEATURE_CONFIG		| 27	| ZynqMP	| Get runtime feature config		|
+ * | IOCTL_READ_REG			| 28	| Versal	| Read a 32-bit register		|
+ * | IOCTL_MASK_WRITE_REG		| 29	| Versal	| RMW a 32-bit register			|
+ * | IOCTL_SET_SD_CONFIG		| 30	| ZynqMP	| Set SD config register value		|
+ * | IOCTL_SET_GEM_CONFIG		| 31	| ZynqMP	| Set GEM config register value		|
+ * | IOCTL_SET_USB_CONFIG		| 32	| ZynqMP	| Set USB config register value		|
+ * | IOCTL_AIE_OPS			| 33	| Versal	| AIE1/AIEML Run Time Operations	|
+ * | IOCTL_GET_QOS			| 34	| Versal	| Get Device QoS value			|
+ * | IOCTL_GET_APU_OPER_MODE		| 35	| Versal	| Get APU operation mode		|
+ * | IOCTL_SET_APU_OPER_MODE		| 36	| Versal	| Set APU operation mode		|
+ * | IOCTL_PREPARE_DDR_SHUTDOWN		| 37	| Versal	| Prepare DDR for shut down		|
+ * | IOCTL_GET_SSIT_TEMP		| 38	| Versal	| Get secondary SLR min/max temperature |
+ *
+ *****************************************************************************/
+
+/*****************************************************************************/
+/**
+ * @section QUERY_ID_DETAIL XilPM QUERY IDs Detail
+ *
+ * This section provides the details of the QUERY IDs which are supported across the different platforms and their brief descriptions.
+ *
+ * | Name					| ID	| Platform	| Description				|
+ * |--------------------------------------------|-------|---------------|---------------------------------------|
+ * | XPM_QID_INVALID				| 0	| Both		| Invalid Query ID			|
+ * | XPM_QID_CLOCK_GET_NAME			| 1	| Both		| Get clock name			|
+ * | XPM_QID_CLOCK_GET_TOPOLOGY			| 2	| Both		| Get clock topology			|
+ * | XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS	| 3	| Both		| Get clock fixedfactor parameter	|
+ * | XPM_QID_CLOCK_GET_MUXSOURCES		| 4	| Both		| Get clock mux sources			|
+ * | XPM_QID_CLOCK_GET_ATTRIBUTES		| 5	| Both		| Get clock attributes			|
+ * | XPM_QID_PINCTRL_GET_NUM_PINS		| 6	| Both		| Get total pins			|
+ * | XPM_QID_PINCTRL_GET_NUM_FUNCTIONS		| 7	| Both		| Get total pin functions		|
+ * | XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS	| 8	| Both		| Get total pin function groups		|
+ * | XPM_QID_PINCTRL_GET_FUNCTION_NAME		| 9	| Both		| Get pin function name			|
+ * | XPM_QID_PINCTRL_GET_FUNCTION_GROUPS	| 10	| Both		| Get pin function groups		|
+ * | XPM_QID_PINCTRL_GET_PIN_GROUPS		| 11	| Both		| Get pin groups			|
+ * | XPM_QID_CLOCK_GET_NUM_CLOCKS		| 12	| Both		| Get number of clocks			|
+ * | XPM_QID_CLOCK_GET_MAX_DIVISOR		| 13	| Both		| Get max clock divisor			|
+ * | XPM_QID_PLD_GET_PARENT			| 14	| Versal	| Get PLD parent			|
+ * | XPM_QID_PINCTRL_GET_ATTRIBUTES		| 15	| Versal	| Get pin attributes			|
+ *
+ *****************************************************************************/
+
+
+/*****************************************************************************/
+/**
+ * @section GET_OP_CHAR_DETAIL XilPM GET_OP_CHAR IDs Detail
+ *
+ * This section provides the details of the GET_OP_CHAR IDs which are supported across the different platforms and their brief descriptions.
+ *
+ * | Name				| ID	| Platform	| Description					|
+ * |------------------------------------|-------|---------------|-----------------------------------------------|
+ * | PM_OPCHAR_TYPE_POWER		| 1	| ZynqMP	| Operating characteristic ID power		|
+ * | PM_OPCHAR_TYPE_TEMP		| 2	| Versal	| Operating characteristic ID temperature	|
+ * | PM_OPCHAR_TYPE_LATENCY		| 3	| Both		| Operating characteristic ID latency		|
+ *
+ *****************************************************************************/
+
+
+/**
+ * PM API IDs
+ */
+typedef enum {
+	PM_API_MIN,					/**< 0x0 */
+	PM_GET_API_VERSION,				/**< 0x1 */
+	PM_SET_CONFIGURATION,				/**< 0x2 */
+	PM_GET_NODE_STATUS,				/**< 0x3 */
+	PM_GET_OP_CHARACTERISTIC,			/**< 0x4 */
+	PM_REGISTER_NOTIFIER,				/**< 0x5 */
+	PM_REQUEST_SUSPEND,				/**< 0x6 */
+	PM_SELF_SUSPEND,				/**< 0x7 */
+	PM_FORCE_POWERDOWN,				/**< 0x8 */
+	PM_ABORT_SUSPEND,				/**< 0x9 */
+	PM_REQUEST_WAKEUP,				/**< 0xA */
+	PM_SET_WAKEUP_SOURCE,				/**< 0xB */
+	PM_SYSTEM_SHUTDOWN,				/**< 0xC */
+	PM_REQUEST_NODE,				/**< 0xD */
+	PM_RELEASE_NODE,				/**< 0xE */
+	PM_SET_REQUIREMENT,				/**< 0xF */
+	PM_SET_MAX_LATENCY,				/**< 0x10 */
+	PM_RESET_ASSERT,				/**< 0x11 */
+	PM_RESET_GET_STATUS,				/**< 0x12 */
+	PM_MMIO_WRITE,					/**< 0x13 */
+	PM_MMIO_READ,					/**< 0x14 */
+	PM_INIT_FINALIZE,				/**< 0x15 */
+	PM_FPGA_LOAD,					/**< 0x16 */
+	PM_FPGA_GET_STATUS,				/**< 0x17 */
+	PM_GET_CHIPID,					/**< 0x18 */
+	PM_SECURE_RSA_AES,				/**< 0x19 */
+	PM_SECURE_SHA,					/**< 0x1A */
+	PM_SECURE_RSA,					/**< 0x1B */
+	PM_PINCTRL_REQUEST,				/**< 0x1C */
+	PM_PINCTRL_RELEASE,				/**< 0x1D */
+	PM_PINCTRL_GET_FUNCTION,			/**< 0x1E */
+	PM_PINCTRL_SET_FUNCTION,			/**< 0x1F */
+	PM_PINCTRL_CONFIG_PARAM_GET,			/**< 0x20 */
+	PM_PINCTRL_CONFIG_PARAM_SET,			/**< 0x21 */
+	PM_IOCTL,					/**< 0x22 */
+	PM_QUERY_DATA,					/**< 0x23 */
+	PM_CLOCK_ENABLE,				/**< 0x24 */
+	PM_CLOCK_DISABLE,				/**< 0x25 */
+	PM_CLOCK_GETSTATE,				/**< 0x26 */
+	PM_CLOCK_SETDIVIDER,				/**< 0x27 */
+	PM_CLOCK_GETDIVIDER,				/**< 0x28 */
+	PM_CLOCK_SETRATE,				/**< 0x29 */
+	PM_CLOCK_GETRATE,				/**< 0x2A */
+	PM_CLOCK_SETPARENT,				/**< 0x2B */
+	PM_CLOCK_GETPARENT,				/**< 0x2C */
+	PM_SECURE_IMAGE,				/**< 0x2D */
+	PM_FPGA_READ,					/**< 0x2E */
+	PM_SECURE_AES,					/**< 0x2F */
+	PM_PLL_SET_PARAMETER,				/**< 0x30 */
+	PM_PLL_GET_PARAMETER,				/**< 0x31 */
+	PM_PLL_SET_MODE,				/**< 0x32 */
+	PM_PLL_GET_MODE,				/**< 0x33 */
+	PM_REGISTER_ACCESS,				/**< 0x34 */
+	PM_EFUSE_ACCESS,				/**< 0x35 */
+	PM_ADD_SUBSYSTEM,				/**< 0x36 */
+	PM_DESTROY_SUBSYSTEM,				/**< 0x37 */
+	PM_DESCRIBE_NODES,				/**< 0x38 */
+	PM_ADD_NODE,					/**< 0x39 */
+	PM_ADD_NODE_PARENT,				/**< 0x3A */
+	PM_ADD_NODE_NAME,				/**< 0x3B */
+	PM_ADD_REQUIREMENT,				/**< 0x3C */
+	PM_SET_CURRENT_SUBSYSTEM,			/**< 0x3D */
+	PM_INIT_NODE,					/**< 0x3E */
+	PM_FEATURE_CHECK,				/**< 0x3F */
+	PM_ISO_CONTROL,					/**< 0x40 */
+	PM_ACTIVATE_SUBSYSTEM,				/**< 0x41 */
+	PM_SET_NODE_ACCESS,				/**< 0x42 */
+	PM_BISR,					/**< 0x43 */
+	PM_APPLY_TRIM,					/**< 0x44 */
+	PM_NOC_CLOCK_ENABLE,				/**< 0x45 */
+	PM_IF_NOC_CLOCK_ENABLE,				/**< 0x46 */
+	PM_FORCE_HOUSECLEAN,				/**< 0x47 */
+	PM_FPGA_GET_VERSION,				/**< 0x48 */
+	PM_FPGA_GET_FEATURE_LIST,			/**< 0x49 */
+	PM_API_MAX					/**< 0x4A */
+} XPm_ApiId;
+
+#endif  /* PM_API_VERSION_H_ */

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/profile.h

@@ -0,0 +1,105 @@
+/******************************************************************************
+* Copyright (c) 2002 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+
+#ifndef	PROFILE_H
+#define	PROFILE_H	1
+
+#include <stdio.h>
+#include "xil_types.h"
+#include "profile_config.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _system_init( void ) ;
+void _system_clean( void ) ;
+void mcount(u32 frompc, u32 selfpc);
+void profile_intr_handler( void ) ;
+void _profile_init( void );
+
+
+
+/****************************************************************************
+ * Profiling on hardware - Hash table maintained on hardware and data sent
+ * to xmd for gmon.out generation.
+ ****************************************************************************/
+/*
+ * histogram counters are unsigned shorts (according to the kernel).
+ */
+#define	HISTCOUNTER	u16
+
+struct tostruct {
+	u32  selfpc;
+	s32	 count;
+	s16  link;
+	u16	 pad;
+};
+
+struct fromstruct {
+	u32 frompc ;
+	s16 link ;
+	u16 pad ;
+} ;
+
+/*
+ * general rounding functions.
+ */
+#define ROUNDDOWN(x,y)	(((x)/(y))*(y))
+#define ROUNDUP(x,y)	((((x)+(y)-1)/(y))*(y))
+
+/*
+ * The profiling data structures are housed in this structure.
+ */
+struct gmonparam {
+	s32		state;
+
+	/* Histogram Information */
+	u16		*kcount;	/* No. of bins in histogram */
+	u32		kcountsize;	/* Histogram samples */
+
+	/* Call-graph Information */
+	struct fromstruct	*froms;
+	u32		fromssize;
+	struct tostruct		*tos;
+	u32		tossize;
+
+	/* Initialization I/Ps */
+	u32    	lowpc;
+	u32		highpc;
+	u32		textsize;
+	/* u32 		cg_froms, */
+	/* u32 		cg_tos, */
+};
+extern struct gmonparam *_gmonparam;
+extern s32 n_gmon_sections;
+
+/*
+ * Possible states of profiling.
+ */
+#define	GMON_PROF_ON	0
+#define	GMON_PROF_BUSY	1
+#define	GMON_PROF_ERROR	2
+#define	GMON_PROF_OFF	3
+
+/*
+ * Sysctl definitions for extracting profiling information from the kernel.
+ */
+#define	GPROF_STATE	0	/* int: profiling enabling variable */
+#define	GPROF_COUNT	1	/* struct: profile tick count buffer */
+#define	GPROF_FROMS	2	/* struct: from location hash bucket */
+#define	GPROF_TOS	3	/* struct: destination/count structure */
+#define	GPROF_GMONPARAM	4	/* struct: profiling parameters (see above) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 		/* PROFILE_H */

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/sleep.h

@@ -0,0 +1,109 @@
+/******************************************************************************
+* Copyright (C) 2014 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+
+/*****************************************************************************/
+/**
+* @file sleep.h
+*
+*  This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
+*  related APIs.
+*
+* <pre>
+* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6   srm  11/02/17 Added processor specific sleep routines
+*								 function prototypes.
+* 7.7	sk   01/10/22 Typecast sleep declaration argument from unsigned int to
+* 		      u32 to fix misra_c_2012_directive_4_6 violation.
+* 7.7	sk   01/10/22 Modify the return type of sleep_R5 and usleep_R5 from
+* 		      unsigned to void to fix misra_c_2012_rule_17_7 violation.
+* 8.0	sk   03/02/22 Update usleep_R5 and usleep parameter types to fix misra_
+*		      c_2012_directive_4_6 violation.
+* 8.0	sk   03/17/22 Modify the return type of usleep_MB from int to void and
+*		      sleep_MB from unsigned to void to fix misra_c_2012_rule_
+*		      17_7 violation.
+* 8.0	sk   03/17/22 Modify sleep_MB parameter type from unsigned int to
+*		      u32 and usleep_MB parameter type from unsigned long to
+*		      ULONG to fix misra_c_2012_rule_4_6 violation.
+* 9.0   ml   03/03/23 Add description to fix doxygen warnings.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This macro polls an address periodically until a condition is met or till the
+* timeout occurs.
+* The minimum timeout for calling this macro is 100us. If the timeout is less
+* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
+* If the timeout is not a multiple of 100us, it waits for a timeout of
+* the next usec value which is a multiple of 100us.
+*
+* @param            IO_func - accessor function to read the register contents.
+*                   Depends on the register width.
+* @param            ADDR - Address to be polled
+* @param            VALUE - variable to read the value
+* @param            COND - Condition to checked (usually involves VALUE)
+* @param            TIMEOUT_US - timeout in micro seconds
+*
+* @return           0 - when the condition is met
+*                   -1 - when the condition is not met till the timeout period
+*
+* @note             none
+*
+*****************************************************************************/
+#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
+ ( {	  \
+	u64 timeout = TIMEOUT_US/100;    \
+	if(TIMEOUT_US%100!=0)	\
+		timeout++;   \
+	for(;;) { \
+		VALUE = IO_func(ADDR); \
+		if(COND) \
+			break; \
+		else {    \
+			usleep(100);  \
+			timeout--; \
+			if(timeout==0) \
+			break;  \
+		}  \
+	}    \
+	(timeout>0) ? 0 : -1;  \
+ }  )
+
+/************************** Function Prototypes ******************************/
+void usleep(ULONG useconds);
+void sleep(u32 seconds);
+void usleep_R5(ULONG useconds);
+void sleep_R5(u32 seconds);
+void usleep_MB(ULONG useconds);
+void sleep_MB(u32 seconds);
+int usleep_A53(unsigned long useconds);
+unsigned sleep_A53(unsigned int seconds);
+int usleep_A9(unsigned long useconds);
+unsigned sleep_A9(unsigned int seconds);
+
+/*****************************************************************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/smc.h

@@ -0,0 +1,97 @@
+/******************************************************************************
+* Copyright (c) 2010 - 2021 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file smc.h
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  11/03/09 Initial release.
+* 4.2	pkp	 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
+*					  as smc.c is removed
+* </pre>
+*
+* @note		None.
+*
+******************************************************************************/
+
+/**
+ *@cond nocomments
+ */
+
+#ifndef SMC_H /* prevent circular inclusions */
+#define SMC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory controller configuration register offset */
+#define XSMCPSS_MC_STATUS		0x000U	/* Controller status reg, RO */
+#define XSMCPSS_MC_INTERFACE_CONFIG	0x004U	/* Interface config reg, RO */
+#define XSMCPSS_MC_SET_CONFIG		0x008U	/* Set configuration reg, WO */
+#define XSMCPSS_MC_CLR_CONFIG		0x00CU	/* Clear config reg, WO */
+#define XSMCPSS_MC_DIRECT_CMD		0x010U	/* Direct command reg, WO */
+#define XSMCPSS_MC_SET_CYCLES		0x014U	/* Set cycles register, WO */
+#define XSMCPSS_MC_SET_OPMODE		0x018U	/* Set opmode register, WO */
+#define XSMCPSS_MC_REFRESH_PERIOD_0	0x020U	/* Refresh period_0 reg, RW */
+#define XSMCPSS_MC_REFRESH_PERIOD_1	0x024U	/* Refresh period_1 reg, RW */
+
+/* Chip select configuration register offset */
+#define XSMCPSS_CS_IF0_CHIP_0_OFFSET	0x100U	/* Interface 0 chip 0 config */
+#define XSMCPSS_CS_IF0_CHIP_1_OFFSET	0x120U	/* Interface 0 chip 1 config */
+#define XSMCPSS_CS_IF0_CHIP_2_OFFSET	0x140U	/* Interface 0 chip 2 config */
+#define XSMCPSS_CS_IF0_CHIP_3_OFFSET	0x160U	/* Interface 0 chip 3 config */
+#define XSMCPSS_CS_IF1_CHIP_0_OFFSET	0x180U	/* Interface 1 chip 0 config */
+#define XSMCPSS_CS_IF1_CHIP_1_OFFSET	0x1A0U	/* Interface 1 chip 1 config */
+#define XSMCPSS_CS_IF1_CHIP_2_OFFSET	0x1C0U	/* Interface 1 chip 2 config */
+#define XSMCPSS_CS_IF1_CHIP_3_OFFSET	0x1E0U	/* Interface 1 chip 3 config */
+
+/* User configuration register offset */
+#define XSMCPSS_UC_STATUS_OFFSET	0x200U	/* User status reg, RO */
+#define XSMCPSS_UC_CONFIG_OFFSET	0x204U	/* User config reg, WO */
+
+/* Integration test register offset */
+#define XSMCPSS_IT_OFFSET		0xE00U
+
+/* ID configuration register offset */
+#define XSMCPSS_ID_PERIP_0_OFFSET	0xFE0U
+#define XSMCPSS_ID_PERIP_1_OFFSET	0xFE4U
+#define XSMCPSS_ID_PERIP_2_OFFSET	0xFE8U
+#define XSMCPSS_ID_PERIP_3_OFFSET	0xFECU
+#define XSMCPSS_ID_PCELL_0_OFFSET	0xFF0U
+#define XSMCPSS_ID_PCELL_1_OFFSET	0xFF4U
+#define XSMCPSS_ID_PCELL_2_OFFSET	0xFF8U
+#define XSMCPSS_ID_PCELL_3_OFFSET	0xFFCU
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SMC_H */
+
+/**
+ *@endcond
+  */

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/vectors.h

@@ -0,0 +1,64 @@
+/******************************************************************************
+* Copyright (c) 2009 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file vectors.h
+*
+* This file contains the C level vector prototypes for the ARM Cortex A9 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/10 Initial version, moved over from bsp area
+* 6.0   mus  07/27/16 Consolidated vectors for a9,a53 and r5 processors
+* 8.0	sk   03/02/22 Update _VECTORS_H_ with VECTORS_H_ to fix misra_c_
+* 		      2012_rule_21_1 violation.
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef VECTORS_H_
+#define VECTORS_H_
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void FIQInterrupt(void);
+void IRQInterrupt(void);
+#if !defined (__aarch64__)
+void SWInterrupt(void);
+void DataAbortInterrupt(void);
+void PrefetchAbortInterrupt(void);
+void UndefinedException(void);
+#else
+void SynchronousInterrupt(void);
+void SErrorInterrupt(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xadcps.h

@@ -0,0 +1,582 @@
+/******************************************************************************
+* Copyright (C) 2011 - 2020 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* @file xadcps.h
+* @addtogroup Overview
+* @{
+* @details
+*
+* The XAdcPs driver supports the Xilinx XADC/ADC device.
+*
+* The XADC/ADC device has the following features:
+*	- 10-bit, 200-KSPS (kilo samples per second)
+*		Analog-to-Digital Converter (ADC)
+*	- Monitoring of on-chip supply voltages and temperature
+*	- 1 dedicated differential analog-input pair and
+*	  16 auxiliary differential analog-input pairs
+*	- Automatic alarms based on user defined limits for the on-chip
+*	  supply voltages and temperature
+*	- Automatic Channel Sequencer, programmable averaging, programmable
+*	  acquisition time for the external inputs, unipolar or differential
+*	  input selection for the external inputs
+*	- Inbuilt Calibration
+*	- Optional interrupt request generation
+*
+*
+* The user should refer to the hardware device specification for detailed
+* information about the device.
+*
+* This header file contains the prototypes of driver functions that can
+* be used to access the XADC/ADC device.
+*
+*
+* <b> XADC Channel Sequencer Modes </b>
+*
+* The  XADC Channel Sequencer supports the following operating modes:
+*
+*   - <b> Default </b>: This is the default mode after power up.
+*		In this mode of operation the XADC operates in
+*		a sequence mode, monitoring the on chip sensors:
+*		Temperature, VCCINT, and VCCAUX.
+*   - <b> One pass through sequence </b>: In this mode the XADC
+*		converts the channels enabled in the Sequencer Channel Enable
+*		registers for a single pass and then stops.
+*   - <b> Continuous cycling of sequence </b>: In this mode the XADC
+*		converts the channels enabled in the Sequencer Channel Enable
+*		registers continuously.
+*   - <b> Single channel mode</b>: In this mode the XADC Channel
+*		Sequencer is disabled and the XADC operates in a
+*		Single Channel Mode.
+*		The XADC can operate either in a Continuous or Event
+*		driven sampling mode in the single channel mode.
+*   - <b> Simultaneous Sampling Mode</b>: In this mode the XADC Channel
+*		Sequencer will automatically sequence through eight fixed pairs
+*		of auxiliary analog input channels for simulataneous conversion.
+*   - <b> Independent ADC mode</b>: In this mode the first ADC (A) is used to
+*		is used to implement a fixed monitoring mode similar to the
+*		default mode but the alarm fucntions ar eenabled.
+*		The second ADC (B) is available to be used with external analog
+*		input channels only.
+*
+* Read the XADC spec for more information about the sequencer modes.
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the XADC/ADC device.
+*
+* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
+* device. The user needs to first call the XAdcPs_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XAdcPs_CfgInitialize() API.
+*
+*
+* <b>Interrupts</b>
+*
+* The XADC/ADC device supports interrupt driven mode and the default
+* operation mode is polling mode.
+*
+* The interrupt mode is available only if hardware is configured to support
+* interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* device in interrupt mode.
+*
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*
+* <b> Building the driver </b>
+*
+* The XAdcPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* <b> Limitations of the driver </b>
+*
+* XADC/ADC device can be accessed through the JTAG port and the PLB
+* interface. The driver implementation does not support the simultaneous access
+* of the device by both these interfaces. The user has to care of this situation
+* in the user application code.
+*
+* <br><br>
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss    02/18/13	Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+*			XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+*			in xadcps.c to fix CR #693371
+* 1.03a bss    11/01/13 Modified xadcps_hw.h to use correct Register offsets
+*			CR#749687
+* 2.1   bss    08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
+*			XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
+*			XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
+*			functions.
+*			Modified Assert for XAdcPs_SetSingleChParams in
+*			xadcps.c to fix CR #807563.
+* 2.2   bss    04/27/14 Modified to use correct Device Config base address in
+*						xadcps.c (CR#854437).
+*       ms     01/23/17 Added xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+*       ms     04/05/17 Modified Comment lines in functions of xadcps
+*                       examples to recognize it as documentation block
+*                       for doxygen generation.
+* 2.3   mn     07/09/18 Fix Doxygen warning
+* 2.6   aad    11/02/20 Fix MISRAC Mandatory and Advisory errors.
+*       aad    12/17/20 Added missing function declarations and removed
+*			functions with no definitions.
+* 2.7   cog    07/24/23 Added support for SDT flow
+*
+*
+* </pre>
+*
+*****************************************************************************/
+#ifndef XADCPS_H /* Prevent circular inclusions */
+#define XADCPS_H /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xadcps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**
+ * @name Indexes for the different channels.
+ * @{
+ */
+#define XADCPS_CH_TEMP		0x0U  /**< On Chip Temperature */
+#define XADCPS_CH_VCCINT	0x1U  /**< VCCINT */
+#define XADCPS_CH_VCCAUX	0x2U  /**< VCCAUX */
+#define XADCPS_CH_VPVN		0x3U  /**< VP/VN Dedicated analog inputs */
+#define XADCPS_CH_VREFP		0x4U  /**< VREFP */
+#define XADCPS_CH_VREFN		0x5U  /**< VREFN */
+#define XADCPS_CH_VBRAM		0x6U  /**< On-chip VBRAM Data Reg, 7 series */
+#define XADCPS_CH_SUPPLY_CALIB	0x07U /**< Supply Calib Data Reg */
+#define XADCPS_CH_ADC_CALIB	0x08U /**< ADC Offset Channel Reg */
+#define XADCPS_CH_GAINERR_CALIB 0x09U /**< Gain Error Channel Reg  */
+#define XADCPS_CH_VCCPINT	0x0DU /**< On-chip PS VCCPINT Channel , Zynq */
+#define XADCPS_CH_VCCPAUX	0x0EU /**< On-chip PS VCCPAUX Channel , Zynq */
+#define XADCPS_CH_VCCPDRO	0x0FU /**< On-chip PS VCCPDRO Channel , Zynq */
+#define XADCPS_CH_AUX_MIN	 16U /**< Channel number for 1st Aux Channel */
+#define XADCPS_CH_AUX_MAX	 31U /**< Channel number for Last Aux channel */
+
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Calibration Coefficient Data.
+ * @{
+ */
+#define XADCPS_CALIB_SUPPLY_COEFF     0U /**< Supply Offset Calib Coefficient */
+#define XADCPS_CALIB_ADC_COEFF        1U /**< ADC Offset Calib Coefficient */
+#define XADCPS_CALIB_GAIN_ERROR_COEFF 2U /**< Gain Error Calib Coefficient*/
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Minimum/Maximum Measurement Data.
+ * @{
+ */
+#define XADCPS_MAX_TEMP		0U /**< Maximum Temperature Data */
+#define XADCPS_MAX_VCCINT	1U /**< Maximum VCCINT Data */
+#define XADCPS_MAX_VCCAUX	2U /**< Maximum VCCAUX Data */
+#define XADCPS_MAX_VBRAM	3U /**< Maximum VBRAM Data */
+#define XADCPS_MIN_TEMP		4U /**< Minimum Temperature Data */
+#define XADCPS_MIN_VCCINT	5U /**< Minimum VCCINT Data */
+#define XADCPS_MIN_VCCAUX	6U /**< Minimum VCCAUX Data */
+#define XADCPS_MIN_VBRAM	7U /**< Minimum VBRAM Data */
+#define XADCPS_MAX_VCCPINT	8U /**< Maximum VCCPINT Register , Zynq */
+#define XADCPS_MAX_VCCPAUX	9U /**< Maximum VCCPAUX Register , Zynq */
+#define XADCPS_MAX_VCCPDRO	0xAU /**< Maximum VCCPDRO Register , Zynq */
+#define XADCPS_MIN_VCCPINT	0xCU /**< Minimum VCCPINT Register , Zynq */
+#define XADCPS_MIN_VCCPAUX	0xDU /**< Minimum VCCPAUX Register , Zynq */
+#define XADCPS_MIN_VCCPDRO	0xEU /**< Minimum VCCPDRO Register , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Alarm Threshold(Limit) Register (ATR) indexes.
+ * @{
+ */
+#define XADCPS_ATR_TEMP_UPPER	 0U /**< High user Temperature */
+#define XADCPS_ATR_VCCINT_UPPER  1U /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_UPPER  2U /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_OT_UPPER	 3U /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_TEMP_LOWER	 4U /**< Upper Over Temperature limit Reg */
+#define XADCPS_ATR_VCCINT_LOWER	 5U /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_LOWER	 6U /**< VCCAUX low voltage limit register  */
+#define XADCPS_ATR_OT_LOWER	 7U /**< Lower Over Temperature limit */
+#define XADCPS_ATR_VBRAM_UPPER_  8U /**< VRBAM Upper Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_UPPER 9U /**< VCCPINT Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER 0xAU /**< VCCPAUX Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER 0xBU /**< VCCPDRO Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER	 0xCU /**< VRBAM Lower Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER 0xDU /**< VCCPINT Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER 0xEU /**< VCCPAUX Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER 0xFU /**< VCCPDRO Lower Alarm Reg , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Averaging to be done for the channels.
+ * @{
+ */
+#define XADCPS_AVG_0_SAMPLES	0U  /**< No Averaging */
+#define XADCPS_AVG_16_SAMPLES	1U  /**< Average 16 samples */
+#define XADCPS_AVG_64_SAMPLES	2U  /**< Average 64 samples */
+#define XADCPS_AVG_256_SAMPLES	3U  /**< Average 256 samples */
+
+/*@}*/
+
+
+/**
+ * @name Channel Sequencer Modes of operation
+ * @{
+ */
+#define XADCPS_SEQ_MODE_SAFE		0U  /**< Default Safe Mode */
+#define XADCPS_SEQ_MODE_ONEPASS		1U  /**< Onepass through Sequencer */
+#define XADCPS_SEQ_MODE_CONTINPASS	2U  /**< Continuous Cycling Sequencer */
+#define XADCPS_SEQ_MODE_SINGCHAN	3U  /**< Single channel -No Sequencing */
+#define XADCPS_SEQ_MODE_SIMUL_SAMPLING	4U  /**< Simultaneous sampling */
+#define XADCPS_SEQ_MODE_INDEPENDENT	8U  /**< Independent mode */
+
+/*@}*/
+
+
+
+/**
+ * @name Power Down Modes
+ * @{
+ */
+#define XADCPS_PD_MODE_NONE		0U  /**< No Power Down  */
+#define XADCPS_PD_MODE_ADCB		1U  /**< Power Down ADC B */
+#define XADCPS_PD_MODE_XADC		2U  /**< Power Down ADC A and ADC B */
+/*@}*/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the XADC/ADC
+ * device.
+ */
+typedef struct {
+#ifndef SDT
+	u16  DeviceId;		/**< Unique ID of device */
+#else
+	char *Name;
+#endif
+	u32  BaseAddress;	/**< Device base address */
+} XAdcPs_Config;
+
+
+/**
+ * The driver's instance data. The user is required to allocate a variable
+ * of this type for every XADC/ADC device in the system. A pointer to
+ * a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XAdcPs_Config Config;	/**< XAdcPs_Config of current device */
+	u32  IsReady;		/**< Device is initialized and ready  */
+
+} XAdcPs;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in Event Sampling mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+*		- TRUE if the device is in Event Sampling Mode.
+*		- FALSE if the device is in Continuous Sampling Mode.
+*
+* @note		C-Style signature:
+*		int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsEventSamplingModeSet(InstancePtr)			\
+	(((XAdcPs_ReadInternalReg(InstancePtr,	 			\
+			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ?	\
+			TRUE : FALSE))
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in External Mux mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+*		- TRUE if the device is in External Mux Mode.
+*		- FALSE if the device is NOT in External Mux Mode.
+*
+* @note		C-Style signature:
+*		int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsExternalMuxModeSet(InstancePtr)			\
+	(((XAdcPs_ReadInternalReg(InstancePtr,	 			\
+			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ?	\
+			TRUE : FALSE))
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC Raw Data to Temperature(centigrades).
+*
+* @param	AdcData is the Raw ADC Data from XADC.
+*
+* @return 	The Temperature in centigrades.
+*
+* @note		C-Style signature:
+*		float XAdcPs_RawToTemperature(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToTemperature(AdcData)				\
+	((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC/ADC Raw Data to Voltage(volts).
+*
+* @param	AdcData is the XADC/ADC Raw Data.
+*
+* @return 	The Voltage in volts.
+*
+* @note		C-Style signature:
+*		float XAdcPs_RawToVoltage(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToVoltage(AdcData) 					\
+	((((float)(AdcData))* (3.0f))/65536.0f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
+*
+* @param	Temperature is the Temperature in centigrades to be
+*		converted to XADC/ADC Raw Data.
+*
+* @return 	The XADC/ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XAdcPs_TemperatureToRaw(float Temperature);
+*
+*****************************************************************************/
+#define XAdcPs_TemperatureToRaw(Temperature)				\
+	((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
+
+/****************************************************************************/
+/**
+*
+* This macro converts Voltage in Volts to XADC/ADC Raw Data.
+*
+* @param	Voltage is the Voltage in volts to be converted to
+*		XADC/ADC Raw Data.
+*
+* @return 	The XADC/ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XAdcPs_VoltageToRaw(float Voltage);
+*
+*****************************************************************************/
+#define XAdcPs_VoltageToRaw(Voltage)			 		\
+	((int)((Voltage)*65536.0f/3.0f))
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for writing to the XADC Registers using the
+* command FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Data is the value to be written to XADC register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
+*
+*****************************************************************************/
+#define XAdcPs_WriteFifo(InstancePtr, Data)				\
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,		\
+			  XADCPS_CMDFIFO_OFFSET, Data);
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for reading from the XADC Registers using the
+* data FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	Data read from the FIFO
+*
+* @note		C-Style signature:
+*		u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_ReadFifo(InstancePtr)				\
+	XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,	\
+			  XADCPS_RDFIFO_OFFSET);
+
+
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ * Functions in xadcps_sinit.c
+ */
+#ifndef SDT
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
+#else
+XAdcPs_Config *XAdcPs_LookupConfig(u32 BaseAddress);
+#endif
+
+/**
+ * Functions in xadcps.c
+ */
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
+				XAdcPs_Config *ConfigPtr,
+				u32 EffectiveAddr);
+
+void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data);
+u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr);
+
+u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr);
+
+void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data);
+u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr);
+
+void XAdcPs_Reset(XAdcPs *InstancePtr);
+
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
+
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
+
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
+
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+				u8 Channel,
+				int IncreaseAcqCycles,
+				int IsEventMode,
+				int IsDifferentialMode);
+
+
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
+
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
+
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
+
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
+
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_selftest.c
+ */
+int XAdcPs_SelfTest(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_intr.c
+ */
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
+
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* End of protection macro. */
+/** @} */

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xadcps_hw.h

@@ -0,0 +1,478 @@
+/******************************************************************************
+* Copyright (C) 2011 - 2020 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* @file xadcps_hw.h
+* @addtogroup Overview
+* @{
+*
+* This header file contains identifiers and basic driver functions (or
+* macros) that can be used to access the XADC device through the Device
+* Config Interface of the Zynq.
+*
+*
+* Refer to the device specification for more information about this driver.
+*
+* @note	 None.
+*
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.03a bss    11/01/13 Modified macros to use correct Register offsets
+*			CR#749687
+* 2.6   aad    11/02/20 Fix MISRAC Mandatory and Advisory errors.
+*
+* </pre>
+*
+*****************************************************************************/
+#ifndef XADCPS_HW_H /* Prevent circular inclusions */
+#define XADCPS_HW_H /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**@name Register offsets of XADC in the Device Config
+ *
+ * The following constants provide access to each of the registers of the
+ * XADC device.
+ * @{
+ */
+
+#define XADCPS_CFG_OFFSET	 0x00U /**< Configuration Register */
+#define XADCPS_INT_STS_OFFSET	 0x04U /**< Interrupt Status Register */
+#define XADCPS_INT_MASK_OFFSET	 0x08U /**< Interrupt Mask Register */
+#define XADCPS_MSTS_OFFSET	 0x0CU /**< Misc status register */
+#define XADCPS_CMDFIFO_OFFSET	 0x10U /**< Command FIFO Register */
+#define XADCPS_RDFIFO_OFFSET	 0x14U /**< Read FIFO Register */
+#define XADCPS_MCTL_OFFSET	 0x18U /**< Misc control register */
+
+/* @} */
+
+
+
+
+
+/** @name XADC Config Register Bit definitions
+  * @{
+ */
+#define XADCPS_CFG_ENABLE_MASK	 0x80000000U /**< Enable access from PS mask */
+#define XADCPS_CFG_CFIFOTH_MASK  0x00F00000U /**< Command FIFO Threshold mask */
+#define XADCPS_CFG_DFIFOTH_MASK  0x000F0000U /**< Data FIFO Threshold mask */
+#define XADCPS_CFG_WEDGE_MASK	 0x00002000U /**< Write Edge Mask */
+#define XADCPS_CFG_REDGE_MASK	 0x00001000U /**< Read Edge Mask */
+#define XADCPS_CFG_TCKRATE_MASK  0x00000300U /**< Clock freq control */
+#define XADCPS_CFG_IGAP_MASK	 0x0000001FU /**< Idle Gap between
+						* successive commands */
+/* @} */
+
+
+/** @name XADC Interrupt Status/Mask Register Bit definitions
+  *
+  * The definitions are same for the Interrupt Status Register and
+  * Interrupt Mask Register. They are defined only once.
+  * @{
+ */
+#define XADCPS_INTX_ALL_MASK   	   0x000003FFU /**< Alarm Signals Mask  */
+#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200U /**< CMD FIFO less than threshold */
+#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100U /**< Data FIFO greater than threshold */
+#define XADCPS_INTX_OT_MASK	   0x00000080U /**< Over temperature Alarm Status */
+#define XADCPS_INTX_ALM_ALL_MASK   0x0000007FU /**< Alarm Signals Mask  */
+#define XADCPS_INTX_ALM6_MASK	   0x00000040U /**< Alarm 6 Mask  */
+#define XADCPS_INTX_ALM5_MASK	   0x00000020U /**< Alarm 5 Mask  */
+#define XADCPS_INTX_ALM4_MASK	   0x00000010U /**< Alarm 4 Mask  */
+#define XADCPS_INTX_ALM3_MASK	   0x00000008U /**< Alarm 3 Mask  */
+#define XADCPS_INTX_ALM2_MASK	   0x00000004U /**< Alarm 2 Mask  */
+#define XADCPS_INTX_ALM1_MASK	   0x00000002U /**< Alarm 1 Mask  */
+#define XADCPS_INTX_ALM0_MASK	   0x00000001U /**< Alarm 0 Mask  */
+
+/* @} */
+
+
+/** @name XADC Miscellaneous Register Bit definitions
+  * @{
+ */
+#define XADCPS_MSTS_CFIFO_LVL_MASK  0x000F0000U /**< Command FIFO Level mask */
+#define XADCPS_MSTS_DFIFO_LVL_MASK  0x0000F000U /**< Data FIFO Level Mask  */
+#define XADCPS_MSTS_CFIFOF_MASK     0x00000800U /**< Command FIFO Full Mask  */
+#define XADCPS_MSTS_CFIFOE_MASK     0x00000400U /**< Command FIFO Empty Mask  */
+#define XADCPS_MSTS_DFIFOF_MASK     0x00000200U /**< Data FIFO Full Mask  */
+#define XADCPS_MSTS_DFIFOE_MASK     0x00000100U /**< Data FIFO Empty Mask  */
+#define XADCPS_MSTS_OT_MASK	    0x00000080U /**< Over Temperature Mask */
+#define XADCPS_MSTS_ALM_MASK	    0x0000007FU /**< Alarms Mask  */
+/* @} */
+
+
+/** @name XADC Miscellaneous Control Register Bit definitions
+  * @{
+ */
+#define XADCPS_MCTL_RESET_MASK      0x00000010U /**< Reset XADC */
+#define XADCPS_MCTL_FLUSH_MASK      0x00000001U /**< Flush the FIFOs */
+/* @} */
+
+
+/**@name Internal Register offsets of the XADC
+ *
+ * The following constants provide access to each of the internal registers of
+ * the XADC device.
+ * @{
+ */
+
+/*
+ * XADC Internal Channel Registers
+ */
+#define XADCPS_TEMP_OFFSET		  0x00U /**< On-chip Temperature Reg */
+#define XADCPS_VCCINT_OFFSET		  0x01U /**< On-chip VCCINT Data Reg */
+#define XADCPS_VCCAUX_OFFSET		  0x02U /**< On-chip VCCAUX Data Reg */
+#define XADCPS_VPVN_OFFSET		  0x03U /**< ADC out of VP/VN	   */
+#define XADCPS_VREFP_OFFSET		  0x04U /**< On-chip VREFP Data Reg */
+#define XADCPS_VREFN_OFFSET		  0x05U /**< On-chip VREFN Data Reg */
+#define XADCPS_VBRAM_OFFSET		  0x06U /**< On-chip VBRAM , 7 Series */
+#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET  0x08U /**< ADC A Supply Offset Reg */
+#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET  0x09U /**< ADC A Offset Data Reg */
+#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0AU /**< ADC A Gain Error Reg  */
+#define XADCPS_VCCPINT_OFFSET		  0x0DU /**< On-chip VCCPINT Reg, Zynq */
+#define XADCPS_VCCPAUX_OFFSET		  0x0EU /**< On-chip VCCPAUX Reg, Zynq */
+#define XADCPS_VCCPDRO_OFFSET		  0x0FU /**< On-chip VCCPDRO Reg, Zynq */
+
+/*
+ * XADC External Channel Registers
+ */
+#define XADCPS_AUX00_OFFSET	0x10U /**< ADC out of VAUXP0/VAUXN0 */
+#define XADCPS_AUX01_OFFSET	0x11U /**< ADC out of VAUXP1/VAUXN1 */
+#define XADCPS_AUX02_OFFSET	0x12U /**< ADC out of VAUXP2/VAUXN2 */
+#define XADCPS_AUX03_OFFSET	0x13U /**< ADC out of VAUXP3/VAUXN3 */
+#define XADCPS_AUX04_OFFSET	0x14U /**< ADC out of VAUXP4/VAUXN4 */
+#define XADCPS_AUX05_OFFSET	0x15U /**< ADC out of VAUXP5/VAUXN5 */
+#define XADCPS_AUX06_OFFSET	0x16U /**< ADC out of VAUXP6/VAUXN6 */
+#define XADCPS_AUX07_OFFSET	0x17U /**< ADC out of VAUXP7/VAUXN7 */
+#define XADCPS_AUX08_OFFSET	0x18U /**< ADC out of VAUXP8/VAUXN8 */
+#define XADCPS_AUX09_OFFSET	0x19U /**< ADC out of VAUXP9/VAUXN9 */
+#define XADCPS_AUX10_OFFSET	0x1AU /**< ADC out of VAUXP10/VAUXN10 */
+#define XADCPS_AUX11_OFFSET	0x1BU /**< ADC out of VAUXP11/VAUXN11 */
+#define XADCPS_AUX12_OFFSET	0x1CU /**< ADC out of VAUXP12/VAUXN12 */
+#define XADCPS_AUX13_OFFSET	0x1DU /**< ADC out of VAUXP13/VAUXN13 */
+#define XADCPS_AUX14_OFFSET	0x1EU /**< ADC out of VAUXP14/VAUXN14 */
+#define XADCPS_AUX15_OFFSET	0x1FU /**< ADC out of VAUXP15/VAUXN15 */
+
+/*
+ * XADC Registers for Maximum/Minimum data captured for the
+ * on chip Temperature/VCCINT/VCCAUX data.
+ */
+#define XADCPS_MAX_TEMP_OFFSET		0x20U /**< Max Temperature Reg */
+#define XADCPS_MAX_VCCINT_OFFSET	0x21U /**< Max VCCINT Register */
+#define XADCPS_MAX_VCCAUX_OFFSET	0x22U /**< Max VCCAUX Register */
+#define XADCPS_MAX_VCCBRAM_OFFSET	0x23U /**< Max BRAM Register, 7 series */
+#define XADCPS_MIN_TEMP_OFFSET		0x24U /**< Min Temperature Reg */
+#define XADCPS_MIN_VCCINT_OFFSET	0x25U /**< Min VCCINT Register */
+#define XADCPS_MIN_VCCAUX_OFFSET	0x26U /**< Min VCCAUX Register */
+#define XADCPS_MIN_VCCBRAM_OFFSET	0x27U /**< Min BRAM Register, 7 series */
+#define XADCPS_MAX_VCCPINT_OFFSET	0x28U /**< Max VCCPINT Register, Zynq */
+#define XADCPS_MAX_VCCPAUX_OFFSET	0x29U /**< Max VCCPAUX Register, Zynq */
+#define XADCPS_MAX_VCCPDRO_OFFSET	0x2AU /**< Max VCCPDRO Register, Zynq */
+#define XADCPS_MIN_VCCPINT_OFFSET	0x2CU /**< Min VCCPINT Register, Zynq */
+#define XADCPS_MIN_VCCPAUX_OFFSET	0x2DU /**< Min VCCPAUX Register, Zynq */
+#define XADCPS_MIN_VCCPDRO_OFFSET	0x2EU /**< Min VCCPDRO Register,Zynq */
+ /* Undefined 0x2F to 0x3E */
+#define XADCPS_FLAG_OFFSET		0x3FU /**< Flag Register */
+
+/*
+ * XADC Configuration Registers
+ */
+#define XADCPS_CFR0_OFFSET	0x40U	/**< Configuration Register 0 */
+#define XADCPS_CFR1_OFFSET	0x41U	/**< Configuration Register 1 */
+#define XADCPS_CFR2_OFFSET	0x42U	/**< Configuration Register 2 */
+
+/* Test Registers 0x43 to 0x47 */
+
+/*
+ * XADC Sequence Registers
+ */
+#define XADCPS_SEQ00_OFFSET	0x48U /**< Seq Reg 00 Adc Channel Selection */
+#define XADCPS_SEQ01_OFFSET	0x49U /**< Seq Reg 01 Adc Channel Selection */
+#define XADCPS_SEQ02_OFFSET	0x4AU /**< Seq Reg 02 Adc Average Enable */
+#define XADCPS_SEQ03_OFFSET	0x4BU /**< Seq Reg 03 Adc Average Enable */
+#define XADCPS_SEQ04_OFFSET	0x4CU /**< Seq Reg 04 Adc Input Mode Select */
+#define XADCPS_SEQ05_OFFSET	0x4DU /**< Seq Reg 05 Adc Input Mode Select */
+#define XADCPS_SEQ06_OFFSET	0x4EU /**< Seq Reg 06 Adc Acquisition Select */
+#define XADCPS_SEQ07_OFFSET	0x4FU /**< Seq Reg 07 Adc Acquisition Select */
+
+/*
+ * XADC Alarm Threshold/Limit Registers (ATR)
+ */
+#define XADCPS_ATR_TEMP_UPPER_OFFSET	0x50U /**< Temp Upper Alarm Register */
+#define XADCPS_ATR_VCCINT_UPPER_OFFSET	0x51U /**< VCCINT Upper Alarm Reg */
+#define XADCPS_ATR_VCCAUX_UPPER_OFFSET	0x52U /**< VCCAUX Upper Alarm Reg */
+#define XADCPS_ATR_OT_UPPER_OFFSET	0x53U /**< Over Temp Upper Alarm Reg */
+#define XADCPS_ATR_TEMP_LOWER_OFFSET	0x54U /**< Temp Lower Alarm Register */
+#define XADCPS_ATR_VCCINT_LOWER_OFFSET	0x55U /**< VCCINT Lower Alarm Reg */
+#define XADCPS_ATR_VCCAUX_LOWER_OFFSET	0x56U /**< VCCAUX Lower Alarm Reg */
+#define XADCPS_ATR_OT_LOWER_OFFSET	0x57U /**< Over Temp Lower Alarm Reg */
+#define XADCPS_ATR_VBRAM_UPPER_OFFSET	0x58U /**< VBRAM Upper Alarm, 7 series */
+#define XADCPS_ATR_VCCPINT_UPPER_OFFSET	0x59U /**< VCCPINT Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET	0x5AU /**< VCCPAUX Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET	0x5BU /**< VCCPDRO Upper Alarm, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER_OFFSET	0x5CU /**< VRBAM Lower Alarm, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER_OFFSET	0x5DU /**< VCCPINT Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET	0x5EU /**< VCCPAUX Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET	0x5FU /**< VCCPDRO Lower Alarm, Zynq */
+
+/* Undefined 0x60 to 0x7F */
+
+/*@}*/
+
+
+
+/**
+ * @name Configuration Register 0 (CFR0) mask(s)
+ * @{
+ */
+#define XADCPS_CFR0_CAL_AVG_MASK	0x00008000U /**< Averaging enable Mask */
+#define XADCPS_CFR0_AVG_VALID_MASK	0x00003000U /**< Averaging bit Mask */
+#define XADCPS_CFR0_AVG1_MASK		0x00000000U /**< No Averaging */
+#define XADCPS_CFR0_AVG16_MASK		0x00001000U /**< Average 16 samples */
+#define XADCPS_CFR0_AVG64_MASK	 	0x00002000U /**< Average 64 samples */
+#define XADCPS_CFR0_AVG256_MASK 	0x00003000U /**< Average 256 samples */
+#define XADCPS_CFR0_AVG_SHIFT	 	12U     /**< Averaging bits shift */
+#define XADCPS_CFR0_MUX_MASK	 	0x00000800U /**< External Mask Enable */
+#define XADCPS_CFR0_DU_MASK	 	0x00000400U /**< Bipolar/Unipolar mode */
+#define XADCPS_CFR0_EC_MASK	 	0x00000200U /**< Event driven/
+						 *  Continuous mode selection
+						 */
+#define XADCPS_CFR0_ACQ_MASK	 	0x00000100U /**< Add acquisition by 6 ADCCLK */
+#define XADCPS_CFR0_CHANNEL_MASK	0x0000001FU /**< Channel number bit Mask */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 1 (CFR1) mask(s)
+ * @{
+ */
+#define XADCPS_CFR1_SEQ_VALID_MASK	  0x0000F000U /**< Sequence bit Mask */
+#define XADCPS_CFR1_SEQ_SAFEMODE_MASK	  0x00000000U /**< Default Safe Mode */
+#define XADCPS_CFR1_SEQ_ONEPASS_MASK	  0x00001000U /**< Onepass through Seq */
+#define XADCPS_CFR1_SEQ_CONTINPASS_MASK	     0x00002000U /**< Continuous Cycling Seq */
+#define XADCPS_CFR1_SEQ_SINGCHAN_MASK	     0x00003000U /**< Single channel - No Seq */
+#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK  0x00004000U /**< Simulataneous Sampling Mask */
+#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK  0x00008000U /**< Independent Mode */
+#define XADCPS_CFR1_SEQ_SHIFT		  12U     /**< Sequence bit shift */
+#define XADCPS_CFR1_ALM_VCCPDRO_MASK	  0x00000800U /**< Alm 6 - VCCPDRO, Zynq  */
+#define XADCPS_CFR1_ALM_VCCPAUX_MASK	  0x00000400U /**< Alm 5 - VCCPAUX, Zynq */
+#define XADCPS_CFR1_ALM_VCCPINT_MASK	  0x00000200U /**< Alm 4 - VCCPINT, Zynq */
+#define XADCPS_CFR1_ALM_VBRAM_MASK	  0x00000100U /**< Alm 3 - VBRAM, 7 series */
+#define XADCPS_CFR1_CAL_VALID_MASK	  0x000000F0U /**< Valid Calibration Mask */
+#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK  0x00000080U /**< Calibration 3 -Power
+							Supply Gain/Offset
+							Enable */
+#define XADCPS_CFR1_CAL_PS_OFFSET_MASK	  0x00000040U /**< Calibration 2 -Power
+							Supply Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x00000020U /**< Calibration 1 -ADC Gain
+							Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK	 0x00000010U /**< Calibration 0 -ADC Offset
+							Enable */
+#define XADCPS_CFR1_CAL_DISABLE_MASK	0x00000000U /**< No Calibration */
+#define XADCPS_CFR1_ALM_ALL_MASK	0x00000F0FU /**< Mask for all alarms */
+#define XADCPS_CFR1_ALM_VCCAUX_MASK	0x00000008U /**< Alarm 2 - VCCAUX Enable */
+#define XADCPS_CFR1_ALM_VCCINT_MASK	0x00000004U /**< Alarm 1 - VCCINT Enable */
+#define XADCPS_CFR1_ALM_TEMP_MASK	0x00000002U /**< Alarm 0 - Temperature */
+#define XADCPS_CFR1_OT_MASK		0x00000001U /**< Over Temperature Enable */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 2 (CFR2) mask(s)
+ * @{
+ */
+#define XADCPS_CFR2_CD_VALID_MASK	0xFF00U  /**<Clock Divisor bit Mask   */
+#define XADCPS_CFR2_CD_SHIFT		8U	/**<Num of shift on division */
+#define XADCPS_CFR2_CD_MIN		8U	/**<Minimum value of divisor */
+#define XADCPS_CFR2_CD_MAX		255U	/**<Maximum value of divisor */
+
+#define XADCPS_CFR2_CD_MIN		8U	/**<Minimum value of divisor */
+#define XADCPS_CFR2_PD_MASK		0x0030U	/**<Power Down Mask */
+#define XADCPS_CFR2_PD_XADC_MASK	0x0030U	/**<Power Down XADC Mask */
+#define XADCPS_CFR2_PD_ADC1_MASK	0x0020U	/**<Power Down ADC1 Mask */
+#define XADCPS_CFR2_PD_SHIFT		4U	/**<Power Down Shift */
+/*@}*/
+
+/**
+ * @name Sequence Register (SEQ) Bit Definitions
+ * @{
+ */
+#define XADCPS_SEQ_CH_CALIB	0x00000001U /**< ADC Calibration Channel */
+#define XADCPS_SEQ_CH_VCCPINT	0x00000020U /**< VCCPINT, Zynq Only */
+#define XADCPS_SEQ_CH_VCCPAUX	0x00000040U /**< VCCPAUX, Zynq Only */
+#define XADCPS_SEQ_CH_VCCPDRO	0x00000080U /**< VCCPDRO, Zynq Only */
+#define XADCPS_SEQ_CH_TEMP	0x00000100U /**< On Chip Temperature Channel */
+#define XADCPS_SEQ_CH_VCCINT	0x00000200U /**< VCCINT Channel */
+#define XADCPS_SEQ_CH_VCCAUX	0x00000400U /**< VCCAUX Channel */
+#define XADCPS_SEQ_CH_VPVN	0x00000800U /**< VP/VN analog inputs Channel */
+#define XADCPS_SEQ_CH_VREFP	0x00001000U /**< VREFP Channel */
+#define XADCPS_SEQ_CH_VREFN	0x00002000U /**< VREFN Channel */
+#define XADCPS_SEQ_CH_VBRAM	0x00004000U /**< VBRAM Channel, 7 series */
+#define XADCPS_SEQ_CH_AUX00	0x00010000U /**< 1st Aux Channel */
+#define XADCPS_SEQ_CH_AUX01	0x00020000U /**< 2nd Aux Channel */
+#define XADCPS_SEQ_CH_AUX02	0x00040000U /**< 3rd Aux Channel */
+#define XADCPS_SEQ_CH_AUX03	0x00080000U /**< 4th Aux Channel */
+#define XADCPS_SEQ_CH_AUX04	0x00100000U /**< 5th Aux Channel */
+#define XADCPS_SEQ_CH_AUX05	0x00200000U /**< 6th Aux Channel */
+#define XADCPS_SEQ_CH_AUX06	0x00400000U /**< 7th Aux Channel */
+#define XADCPS_SEQ_CH_AUX07	0x00800000U /**< 8th Aux Channel */
+#define XADCPS_SEQ_CH_AUX08	0x01000000U /**< 9th Aux Channel */
+#define XADCPS_SEQ_CH_AUX09	0x02000000U /**< 10th Aux Channel */
+#define XADCPS_SEQ_CH_AUX10	0x04000000U /**< 11th Aux Channel */
+#define XADCPS_SEQ_CH_AUX11	0x08000000U /**< 12th Aux Channel */
+#define XADCPS_SEQ_CH_AUX12	0x10000000U /**< 13th Aux Channel */
+#define XADCPS_SEQ_CH_AUX13	0x20000000U /**< 14th Aux Channel */
+#define XADCPS_SEQ_CH_AUX14	0x40000000U /**< 15th Aux Channel */
+#define XADCPS_SEQ_CH_AUX15	0x80000000U /**< 16th Aux Channel */
+
+#define XADCPS_SEQ00_CH_VALID_MASK  0x7FE1U /**< Mask for the valid channels */
+#define XADCPS_SEQ01_CH_VALID_MASK  0xFFFFU /**< Mask for the valid channels */
+
+#define XADCPS_SEQ02_CH_VALID_MASK  0x7FE0U /**< Mask for the valid channels */
+#define XADCPS_SEQ03_CH_VALID_MASK  0xFFFFU /**< Mask for the valid channels */
+
+#define XADCPS_SEQ04_CH_VALID_MASK  0x0800U /**< Mask for the valid channels */
+#define XADCPS_SEQ05_CH_VALID_MASK  0xFFFFU /**< Mask for the valid channels */
+
+#define XADCPS_SEQ06_CH_VALID_MASK  0x0800U /**< Mask for the valid channels */
+#define XADCPS_SEQ07_CH_VALID_MASK  0xFFFFU /**< Mask for the valid channels */
+
+
+#define XADCPS_SEQ_CH_AUX_SHIFT	16U /**< Shift for the Aux Channel */
+
+/*@}*/
+
+/**
+ * @name OT Upper Alarm Threshold Register Bit Definitions
+ * @{
+ */
+
+#define XADCPS_ATR_OT_UPPER_ENB_MASK	0x000FU /**< Mask for OT enable */
+#define XADCPS_ATR_OT_UPPER_VAL_MASK	0xFFF0U /**< Mask for OT value */
+#define XADCPS_ATR_OT_UPPER_VAL_SHIFT	4U      /**< Shift for OT value */
+#define XADCPS_ATR_OT_UPPER_ENB_VAL	0x0003U /**< Value for OT enable */
+#define XADCPS_ATR_OT_UPPER_VAL_MAX	0x0FFFU /**< Max OT value */
+
+/*@}*/
+
+
+/**
+ * @name JTAG DRP Bit Definitions
+ * @{
+ */
+#define XADCPS_JTAG_DATA_MASK		0x0000FFFFU /**< Mask for the Data */
+#define XADCPS_JTAG_ADDR_MASK		0x03FF0000U /**< Mask for the Addr */
+#define XADCPS_JTAG_ADDR_SHIFT		16U	   /**< Shift for the Addr */
+#define XADCPS_JTAG_CMD_MASK		0x3C000000U /**< Mask for the Cmd */
+#define XADCPS_JTAG_CMD_WRITE_MASK	0x08000000U /**< Mask for CMD Write */
+#define XADCPS_JTAG_CMD_READ_MASK	0x04000000U /**< Mask for CMD Read */
+#define XADCPS_JTAG_CMD_SHIFT		26U	   /**< Shift for the Cmd */
+
+/*@}*/
+
+/** @name Unlock Register Definitions
+  * @{
+ */
+ #define XADCPS_UNLK_OFFSET	 0x034U /**< Unlock Register */
+ #define XADCPS_UNLK_VALUE	 0x757BDF0DU /**< Unlock Value */
+
+ /* @} */
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* Read a register of the XADC device. This macro provides register
+* access to all registers using the register offsets defined above.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset is the offset of the register to read.
+*
+* @return	The contents of the register.
+*
+* @note		C-style Signature:
+*		u32 XAdcPs_ReadReg(u32 BaseAddress, u32 RegOffset);
+*
+******************************************************************************/
+#define XAdcPs_ReadReg(BaseAddress, RegOffset) \
+			(Xil_In32((BaseAddress) + (RegOffset)))
+
+/*****************************************************************************/
+/**
+*
+* Write a register of the XADC device. This macro provides
+* register access to all registers using the register offsets defined above.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset is the offset of the register to write.
+* @param	Data is the value to write to the register.
+*
+* @return	None.
+*
+* @note 	C-style Signature:
+*		void XAdcPs_WriteReg(u32 BaseAddress,
+*					u32 RegOffset,u32 Data)
+*
+******************************************************************************/
+#define XAdcPs_WriteReg(BaseAddress, RegOffset, Data) \
+		(Xil_Out32((BaseAddress) + (RegOffset), (Data)))
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Formats the data to be written to the the XADC registers.
+*
+* @param	RegOffset is the offset of the Register
+* @param	Data is the data to be written to the Register if it is
+*		a write.
+* @param	ReadWrite specifies whether it is a Read or a Write.
+*		Use 0 for Read, 1 for Write.
+*
+* @return	None.
+*
+* @note 	C-style Signature:
+*		void XAdcPs_FormatWriteData(u32 RegOffset,
+*					     u16 Data, int ReadWrite)
+*
+******************************************************************************/
+#define XAdcPs_FormatWriteData(RegOffset, Data, ReadWrite) 	    \
+    ((ReadWrite ? XADCPS_JTAG_CMD_WRITE_MASK : XADCPS_JTAG_CMD_READ_MASK ) | \
+     ((RegOffset << XADCPS_JTAG_ADDR_SHIFT) & XADCPS_JTAG_ADDR_MASK) | 	     \
+     (Data & XADCPS_JTAG_DATA_MASK))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* End of protection macro. */
+/** @} */

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xbasic_types.h

@@ -0,0 +1,113 @@
+/******************************************************************************
+* Copyright (c) 2010 - 2021 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+*
+*
+* @note  Dummy File for backwards compatibility
+*
+
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk   1/31/14  Added in bsp common folder for backward compatibility
+* 7.0   aru   01/21/19 Modified the typedef of u32,u16,u8
+* 7.0 	aru   02/06/19 Included stdint.h and stddef.h
+* </pre>
+*
+******************************************************************************/
+
+/**
+ *@cond nocomments
+ */
+
+#ifndef XBASIC_TYPES_H	/* prevent circular inclusions */
+#define XBASIC_TYPES_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef uint8_t	Xuint8;		/**< unsigned 8-bit */
+typedef char		Xint8;		/**< signed 8-bit */
+typedef uint16_t	Xuint16;	/**< unsigned 16-bit */
+typedef short		Xint16;		/**< signed 16-bit */
+typedef uint32_t	Xuint32;	/**< unsigned 32-bit */
+typedef long		Xint32;		/**< signed 32-bit */
+typedef float		Xfloat32;	/**< 32-bit floating point */
+typedef double		Xfloat64;	/**< 64-bit double precision FP */
+typedef unsigned long	Xboolean;	/**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+	Xuint32 Upper;
+	Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32         u32;
+typedef Xuint16         u16;
+typedef Xuint8          u8;
+#endif
+#else
+#include <linux/types.h>
+#endif
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+/*
+ * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
+ * Please use NULL, TRUE and FALSE
+ */
+#define XNULL		NULL
+#define XTRUE		TRUE
+#define XFALSE		FALSE
+
+/*
+ * This file is deprecated and users
+ * should use xil_types.h and xil_assert.h\n\r
+ */
+#warning  The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
+#warning  Please refer the Standalone BSP UG647 for further details
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+
+/**
+ *@endcond
+ */

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h

@@ -0,0 +1,53 @@
+/******************************************************************************
+* Copyright (C) 2015 - 2020 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xcoresightpsdcc.h
+* @addtogroup coresightps_dcc Overview
+* @{
+* @details
+*
+* CoreSight driver component.
+*
+* The coresight is a part of debug communication channel (DCC) group. Jtag UART
+* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
+* ARM target in XSDB console before running the jtag terminal command. Using the
+* coresight driver component, the output stream can be directed to a log file.
+*
+* @note 	None.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date		Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    02/14/15 First release
+* 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
+*       kvn    08/18/15 Modified Makefile according to compiler changes.
+* 1.3   asa    07/01/16 Made changes to ensure that the file does not compile
+*                       for MB BSPs. Instead it throws up a warning. This
+*                       fixes the CR#953056.
+* 1.5   sne    01/19/19 Fixed MISRA-C Violations CR#1025101.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifndef XCORESIGHTPSDCC_H                /* prevent circular inclusions */
+#define XCORESIGHTPSDCC_H                /* by using protection macros */
+#ifndef __MICROBLAZE__
+#include <xil_types.h>
+
+void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
+
+u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
+#endif
+#endif
+/** @} */

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xcortexa9.h

@@ -0,0 +1,18 @@
+/******************************************************************************
+* Copyright (c) 2021-2022 Xilinx, Inc.  All rights reserved.
+* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+#ifndef XIL_XCORTEXA9_H_ /* prevent circular inclusions */
+#define XIL_XCORTEXA9_H_ /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+/**************************** Type Definitions ******************************/
+typedef struct {
+		u32 CpuFreq;
+} XCortexa9_Config;
+
+#endif /* XIL_XCORTEXA9_H_ */

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xcortexa9_config.h

@@ -0,0 +1,18 @@
+/******************************************************************************
+* Copyright (c) 2021-2022 Xilinx, Inc.  All rights reserved.
+* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+#ifndef XIL_XCORTEXA9_CONFIG_H_ /* prevent circular inclusions */
+#define XIL_XCORTEXA9_CONFIG_H_ /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xcortexa9.h"
+
+/************************** Variable Definitions ****************************/
+extern XCortexa9_Config XCortexa9_ConfigTable;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+#define XGet_CpuFreq() XCortexa9_ConfigTable.CpuFreq
+#endif /* XIL_XCORTEXA9_CONFIG_H_ */

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h

@@ -0,0 +1,26 @@
+/******************************************************************************
+* Copyright (C) 2011 - 2021 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xcpu_cortexa9.h
+* @addtogroup cpu_cortexa9 Overview
+* @{
+* @details
+*
+* dummy file
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 2.5   ms   04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
+*                     parameter of cpu_cortexa9 in xparameters.h
+# 2.7   mus  07/03/18 Updated tcl to not to add default flags forcefully into
+#                     extra compiler flags. Now, user can remove default flags
+#                     from extra compiler flags. It fixes CR#998768.
+******************************************************************************/
+/** @} */

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xddrps.h

@@ -0,0 +1,41 @@
+/*******************************************************************************
+* Copyright (C) 2015 - 2020 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+*******************************************************************************/
+
+/******************************************************************************/
+/**
+ *
+ * @file xddrps.h
+ * @addtogroup ddrps Overview
+ * @{
+ * @details
+ *
+ * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps
+ * IP core.
+ *
+ * @note	None.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0	 nsk  08/06/15 First Release
+ * 1.0	 nsk  08/20/15 Updated define_addr_params in ddrps.tcl
+ *		       to support PBD Designs (CR #876857)
+ *
+ * </pre>
+ *
+*******************************************************************************/
+
+#ifndef XDDRPS_H_
+/* Prevent circular inclusions by using protection macros. */
+#define XDDRPS_H_
+
+/******************************* Include Files ********************************/
+
+
+#endif /* XDDRPS_H_ */
+/** @} */

projects/ax7020/ax7020_spi_loopback/vitis/ax7020_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xdebug.h

@@ -0,0 +1,78 @@
+/******************************************************************************
+* Copyright (C) 2002 - 2021 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+
+#ifndef XDEBUG
+#define XDEBUG
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_printf.h"
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+int printf(const char *format, ...);
+
+#define XDBG_DEBUG_ERROR             0x00000001U    /* error  condition messages */
+#define XDBG_DEBUG_GENERAL           0x00000002U    /* general debug  messages */
+#define XDBG_DEBUG_ALL               0xFFFFFFFFU    /* all debugging data */
+
+#define XDBG_DEBUG_FIFO_REG          0x00000100U    /* display register reads/writes */
+#define XDBG_DEBUG_FIFO_RX           0x00000101U    /* receive debug messages */
+#define XDBG_DEBUG_FIFO_TX           0x00000102U    /* transmit debug messages */
+#define XDBG_DEBUG_FIFO_ALL          0x0000010FU    /* all fifo debug messages */
+
+#define XDBG_DEBUG_TEMAC_REG         0x00000400U    /* display register reads/writes */
+#define XDBG_DEBUG_TEMAC_RX          0x00000401U    /* receive debug messages */
+#define XDBG_DEBUG_TEMAC_TX          0x00000402U    /* transmit debug messages */
+#define XDBG_DEBUG_TEMAC_ALL         0x0000040FU    /* all temac  debug messages */
+
+#define XDBG_DEBUG_TEMAC_ADPT_RX     0x00000800U    /* receive debug messages */
+#define XDBG_DEBUG_TEMAC_ADPT_TX     0x00000801U    /* transmit debug messages */
+#define XDBG_DEBUG_TEMAC_ADPT_IOCTL  0x00000802U    /* ioctl debug messages */
+#define XDBG_DEBUG_TEMAC_ADPT_MISC   0x00000803U    /* debug msg for other routines */
+#define XDBG_DEBUG_TEMAC_ADPT_ALL    0x0000080FU    /* all temac adapter debug messages */
+
+
+#define xdbg_current_types (XDBG_DEBUG_GENERAL | XDBG_DEBUG_ERROR | XDBG_DEBUG_TEMAC_REG | XDBG_DEBUG_FIFO_RX | XDBG_DEBUG_FIFO_TX | XDBG_DEBUG_FIFO_REG)
+
+#define xdbg_stmnt(x)  x
+
+/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for
+ * macros that accept variable number of arguments
+ */
+#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
+#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0)
+#else /* ANSI Syntax */
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+#endif
+
+#define xdbg_exception_printf(type, ...) (((type) & xdbg_current_types) ? xil_printf (__VA_ARGS__) : 0)
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x) /**< Debug statement */
+
+/* See VxWorks comments above */
+#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
+#define xdbg_printf(type, args...)
+#else /* ANSI Syntax */
+#define xdbg_printf(...) /**< Debug printf */
+#endif
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XDEBUG */