analog.com user axi_clock_monitor 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW reset RST reset s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_clock_monitor xilinx_anylanguagesynthesis_view_fileset viewChecksum c0944db9 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_clock_monitor xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum b16a94ea xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum fb7ff6a0 clock_0 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation clock_1 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false clock_2 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false clock_3 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false clock_4 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false clock_5 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false clock_6 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false clock_7 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false clock_8 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false clock_9 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false clock_10 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false clock_11 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false clock_12 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false clock_13 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false clock_14 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false clock_15 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false reset out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ID Id 0 NUM_OF_CLOCKS Num Of Clocks 1 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset ../xilinx/common/up_clock_mon_constr.xdc xdc ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource axi_clock_monitor.v verilogSource CHECKSUM_7a2faf0d xilinx_anylanguagebehavioralsimulation_view_fileset ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource axi_clock_monitor.v verilogSource xilinx_xpgui_view_fileset xgui/axi_clock_monitor_v1_0.tcl tclSource CHECKSUM_fb7ff6a0 XGUI_VERSION_2 axi_clock_monitor_v1_0 ID Id 0 NUM_OF_CLOCKS Num Of Clocks 1 Component_Name axi_clock_monitor_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices axi_clock_monitor_v1_0 level_2 package_project Analog Devices https://wiki.analog.com/resources/fpga/docs/axi_clock_monitor 1 2024-06-06T03:01:25Z 2024.1