analog.com user util_axis_resize 1.0 s_axis TVALID s_valid TREADY s_ready TDATA s_data m_axis TVALID m_valid TREADY m_ready TDATA m_data s_axis_m_axis_signal_clock s_axis_m_axis_signal_clock CLK clk ASSOCIATED_BUSIF s_axis:m_axis ASSOCIATED_RESET resetn s_axis_m_axis_signal_reset s_axis_m_axis_signal_reset RST resetn POLARITY ACTIVE_LOW xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_axis_resize xilinx_anylanguagesynthesis_view_fileset viewChecksum 6714e933 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_axis_resize xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 6714e933 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 9664bffc clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation resetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_data in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_data out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation MASTER_DATA_WIDTH Master Data Width 64 SLAVE_DATA_WIDTH Slave Data Width 64 BIG_ENDIAN Big Endian 0 xilinx_anylanguagesynthesis_view_fileset util_axis_resize.v verilogSource CHECKSUM_6714e933 xilinx_anylanguagebehavioralsimulation_view_fileset util_axis_resize.v verilogSource xilinx_xpgui_view_fileset xgui/util_axis_resize_v1_0.tcl tclSource CHECKSUM_9664bffc XGUI_VERSION_2 util_axis_resize_v1_0 MASTER_DATA_WIDTH Master Data Width 64 SLAVE_DATA_WIDTH Slave Data Width 64 BIG_ENDIAN Big Endian 0 Component_Name util_axis_resize_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices util_axis_resize_v1_0 level_2 package_project Analog Devices http://www.analog.com 1 2024-06-06T03:11:11Z 2024.1