analog.com user util_cdc 1.0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog sync_event xilinx_anylanguagesynthesis_view_fileset viewChecksum c325f2fc xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog sync_event xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum c325f2fc xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 3416f698 in_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation in_event in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation out_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation out_event out 0 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation NUM_OF_EVENTS Num Of Events 1 ASYNC_CLK Async Clk 1 xilinx_anylanguagesynthesis_view_fileset sync_gray.v verilogSource sync_bits.v verilogSource sync_data.v verilogSource sync_event.v verilogSource CHECKSUM_fece0fbd xilinx_anylanguagebehavioralsimulation_view_fileset sync_gray.v verilogSource sync_bits.v verilogSource sync_data.v verilogSource sync_event.v verilogSource xilinx_xpgui_view_fileset xgui/sync_event_v1_0.tcl tclSource CHECKSUM_3416f698 XGUI_VERSION_2 ADI Clock-Domain-Crossing Utils NUM_OF_EVENTS Num Of Events 1 ASYNC_CLK Async Clk 1 Component_Name sync_event_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices ADI Clock-Domain-Crossing Utils true level_2 package_project Analog Devices http://www.analog.com 1 2024-06-06T02:53:53Z 2024.1