analog.com user axi_ad9361 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW clk CLK clk ASSOCIATED_RESET rst l_clk CLK l_clk delay_clk CLK delay_clk rst RST rst POLARITY ACTIVE_HIGH gps_pps_irq INTERRUPT gps_pps_irq SENSITIVITY LEVEL_HIGH s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_ad9361 xilinx_anylanguagesynthesis_view_fileset viewChecksum 2de5525c xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_ad9361 xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 93e7a57e xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum aba2bc91 xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_view_fileset rx_clk_in_p in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true rx_clk_in_n in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true rx_frame_in_p in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true rx_frame_in_n in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true rx_data_in_p in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true rx_data_in_n in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true rx_clk_in in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false rx_frame_in in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false rx_data_in in 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false tx_clk_out_p out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true tx_clk_out_n out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true tx_frame_out_p out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true tx_frame_out_n out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true tx_data_out_p out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true tx_data_out_n out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true tx_clk_out out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false tx_frame_out out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false tx_data_out out 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation txnrx out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_sync_in in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dac_sync_out out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tdd_sync in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 tdd_sync_cntr out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation gps_pps in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 gps_pps_irq out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 delay_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation l_clk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rst out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_enable_i0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_valid_i0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data_i0 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_enable_q0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_valid_q0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data_q0 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_enable_i1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_valid_i1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data_i1 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_enable_q1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_valid_q1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data_q1 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_dovf in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 adc_r1_mode out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_enable_i0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_valid_i0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_data_i0 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dac_enable_q0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_valid_q0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_data_q0 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dac_enable_i1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_valid_i1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_data_i1 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dac_enable_q1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_valid_q1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_data_q1 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dac_dunf in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dac_r1_mode out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_enable in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_txnrx in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_dac_gpio_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_dac_gpio_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_adc_gpio_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_adc_gpio_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ID Id 0 MODE_1R1T Mode 1r1t 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 TDD_DISABLE Tdd Disable 0 PPS_RECEIVER_ENABLE Pps Receiver Enable 0 CMOS_OR_LVDS_N Cmos Or Lvds N 0 ADC_INIT_DELAY Adc Init Delay 0 ADC_DATAPATH_DISABLE Adc Datapath Disable 0 ADC_USERPORTS_DISABLE Adc Userports Disable 0 ADC_DATAFORMAT_DISABLE Adc Dataformat Disable 0 ADC_DCFILTER_DISABLE Adc Dcfilter Disable 0 ADC_IQCORRECTION_DISABLE Adc Iqcorrection Disable 0 DAC_INIT_DELAY Dac Init Delay 0 DAC_CLK_EDGE_SEL Dac Clk Edge Sel 0 DAC_IODELAY_ENABLE Dac Iodelay Enable 0 DAC_DATAPATH_DISABLE Dac Datapath Disable 0 DAC_DDS_DISABLE Dac Dds Disable 0 DAC_DDS_TYPE Dac Dds Type 1 DAC_DDS_PHASE_DW Dac Dds Phase Dw 16 DAC_DDS_CORDIC_DW Dac Dds Cordic Dw 14 DAC_DDS_CORDIC_PHASE_DW Dac Dds Cordic Phase Dw 13 DAC_USERPORTS_DISABLE Dac Userports Disable 0 DAC_IQCORRECTION_DISABLE Dac Iqcorrection Disable 0 IO_DELAY_GROUP Io Delay Group dev_if_delay_group IODELAY_CTRL Iodelay Ctrl 1 MIMO_ENABLE Mimo Enable 0 USE_SSI_CLK Use Ssi Clk 1 DELAY_REFCLK_FREQUENCY Delay Refclk Frequency 200 RX_NODPA Rx Nodpa 0 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_list_9ca20931 LEVEL_HIGH LEVEL_LOW EDGE_RISING EDGE_FALLING choice_pairs_00ecfe9a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 choice_pairs_19f99f31 0 10 11 12 13 14 20 21 22 23 24 25 30 choice_pairs_28f798a2 0 1 2 3 4 choice_pairs_fc01a186 0 1 2 3 4 5 6 xilinx_anylanguagesynthesis_view_fileset ../common/ad_pps_receiver_constr.ttcl ttcl ../xilinx/common/up_xfer_cntrl_constr.xdc xdc ../xilinx/common/ad_rst_constr.xdc xdc ../xilinx/common/up_xfer_status_constr.xdc xdc ../xilinx/common/up_clock_mon_constr.xdc xdc axi_ad9361_constr.xdc xdc ../common/ad_addsub.v verilogSource ../xilinx/common/ad_data_clk.v verilogSource ../xilinx/common/ad_data_in.v verilogSource ../xilinx/common/ad_data_out.v verilogSource ../common/ad_datafmt.v verilogSource ../xilinx/common/ad_dcfilter.v verilogSource ../common/ad_dds.v verilogSource ../common/ad_dds_1.v verilogSource ../common/ad_dds_2.v verilogSource ../common/ad_dds_cordic_pipe.v verilogSource ../common/ad_dds_sine.v verilogSource ../common/ad_dds_sine_cordic.v verilogSource ../common/ad_iqcor.v verilogSource ../xilinx/common/ad_mul.v verilogSource ../common/ad_pnmon.v verilogSource ../common/ad_pps_receiver.v verilogSource ../common/ad_rst.v verilogSource ../common/ad_tdd_control.v verilogSource xilinx/axi_ad9361_cmos_if.v verilogSource xilinx/axi_ad9361_lvds_if.v verilogSource axi_ad9361_rx.v verilogSource axi_ad9361_rx_channel.v verilogSource axi_ad9361_rx_pnmon.v verilogSource axi_ad9361_tdd.v verilogSource axi_ad9361_tdd_if.v verilogSource axi_ad9361_tx.v verilogSource axi_ad9361_tx_channel.v verilogSource ../common/up_adc_channel.v verilogSource ../common/up_adc_common.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_dac_channel.v verilogSource ../common/up_dac_common.v verilogSource ../common/up_delay_cntrl.v verilogSource ../common/up_tdd_cntrl.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_ad9361.v verilogSource CHECKSUM_c067097f xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_addsub.v verilogSource ../xilinx/common/ad_data_clk.v verilogSource ../xilinx/common/ad_data_in.v verilogSource ../xilinx/common/ad_data_out.v verilogSource ../common/ad_datafmt.v verilogSource ../xilinx/common/ad_dcfilter.v verilogSource ../common/ad_dds.v verilogSource ../common/ad_dds_1.v verilogSource ../common/ad_dds_2.v verilogSource ../common/ad_dds_cordic_pipe.v verilogSource ../common/ad_dds_sine.v verilogSource ../common/ad_dds_sine_cordic.v verilogSource ../common/ad_iqcor.v verilogSource ../xilinx/common/ad_mul.v verilogSource ../common/ad_pnmon.v verilogSource ../common/ad_pps_receiver.v verilogSource ../common/ad_rst.v verilogSource ../common/ad_tdd_control.v verilogSource xilinx/axi_ad9361_cmos_if.v verilogSource xilinx/axi_ad9361_lvds_if.v verilogSource axi_ad9361_rx.v verilogSource axi_ad9361_rx_channel.v verilogSource axi_ad9361_rx_pnmon.v verilogSource axi_ad9361_tdd.v verilogSource axi_ad9361_tdd_if.v verilogSource axi_ad9361_tx.v verilogSource axi_ad9361_tx_channel.v verilogSource ../common/up_adc_channel.v verilogSource ../common/up_adc_common.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_dac_channel.v verilogSource ../common/up_dac_common.v verilogSource ../common/up_delay_cntrl.v verilogSource ../common/up_tdd_cntrl.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_ad9361.v verilogSource xilinx_xpgui_view_fileset xgui/axi_ad9361_v1_0.tcl tclSource CHECKSUM_4ea9eb31 XGUI_VERSION_2 xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource axi_ad9361_v1_0 ID Id 0 MODE_1R1T Mode 1r1t 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 TDD_DISABLE Tdd Disable 0 PPS_RECEIVER_ENABLE Pps Receiver Enable 0 CMOS_OR_LVDS_N Cmos Or Lvds N 0 ADC_INIT_DELAY Adc Init Delay 0 ADC_DATAPATH_DISABLE Adc Datapath Disable 0 ADC_USERPORTS_DISABLE Adc Userports Disable 0 ADC_DATAFORMAT_DISABLE Adc Dataformat Disable 0 ADC_DCFILTER_DISABLE Adc Dcfilter Disable 0 ADC_IQCORRECTION_DISABLE Adc Iqcorrection Disable 0 DAC_INIT_DELAY Dac Init Delay 0 DAC_CLK_EDGE_SEL Dac Clk Edge Sel 0 DAC_IODELAY_ENABLE Dac Iodelay Enable 0 DAC_DATAPATH_DISABLE Dac Datapath Disable 0 DAC_DDS_DISABLE Dac Dds Disable 0 DAC_DDS_TYPE Dac Dds Type 1 DAC_DDS_PHASE_DW Dac Dds Phase Dw 16 DAC_DDS_CORDIC_DW Dac Dds Cordic Dw 14 DAC_DDS_CORDIC_PHASE_DW Dac Dds Cordic Phase Dw 13 DAC_USERPORTS_DISABLE Dac Userports Disable 0 DAC_IQCORRECTION_DISABLE Dac Iqcorrection Disable 0 IO_DELAY_GROUP Io Delay Group dev_if_delay_group IODELAY_CTRL Iodelay Ctrl 1 MIMO_ENABLE Mimo Enable 0 USE_SSI_CLK Use Ssi Clk 1 DELAY_REFCLK_FREQUENCY Delay Refclk Frequency 200 RX_NODPA Rx Nodpa 0 Component_Name axi_ad9361_v1_0 virtex7 /Analog_Devices axi_ad9361_v1_0 level_2 package_project Analog Devices https://wiki.analog.com/resources/fpga/docs/axi_ad9361 1 2024-01-14T03:41:10Z 2023.2.1