analog.com user axi_ad9783 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_ad9783 xilinx_anylanguagesynthesis_view_fileset viewChecksum 9bcf1355 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_ad9783 xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 363a7ee4 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum acfb27cb xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_view_fileset dac_clk_in_p in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_clk_in_n in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_clk_out_p out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_clk_out_n out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_data_out_p out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_data_out_n out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_div_clk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_rst out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_enable_0 out std_logic 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xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ID Id 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 DAC_DDS_TYPE Dac Dds Type 2 DAC_DDS_CORDIC_DW Dac Dds Cordic Dw 16 DAC_DDS_CORDIC_PHASE_DW Dac Dds Cordic Phase Dw 16 DAC_DATAPATH_DISABLE Dac Datapath Disable 0 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_pairs_00ecfe9a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 choice_pairs_19f99f31 0 10 11 12 13 14 20 21 22 23 24 25 30 choice_pairs_28f798a2 0 1 2 3 4 choice_pairs_fc01a186 0 1 2 3 4 5 6 xilinx_anylanguagesynthesis_view_fileset ../xilinx/common/up_xfer_cntrl_constr.xdc xdc ../xilinx/common/ad_rst_constr.xdc xdc ../xilinx/common/up_xfer_status_constr.xdc xdc ../xilinx/common/up_clock_mon_constr.xdc xdc ../common/ad_dds.v verilogSource ../common/ad_dds_1.v verilogSource ../common/ad_dds_2.v verilogSource ../common/ad_dds_cordic_pipe.v verilogSource ../common/ad_dds_sine.v verilogSource ../common/ad_dds_sine_cordic.v verilogSource ../xilinx/common/ad_mul.v verilogSource ../common/ad_rst.v verilogSource ../xilinx/common/ad_serdes_out.v verilogSource axi_ad9783_channel.v verilogSource axi_ad9783_core.v verilogSource axi_ad9783_if.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_dac_channel.v verilogSource ../common/up_dac_common.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_ad9783.v verilogSource CHECKSUM_43e249c6 xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_dds.v verilogSource ../common/ad_dds_1.v verilogSource ../common/ad_dds_2.v verilogSource ../common/ad_dds_cordic_pipe.v verilogSource ../common/ad_dds_sine.v verilogSource ../common/ad_dds_sine_cordic.v verilogSource ../xilinx/common/ad_mul.v verilogSource ../common/ad_rst.v verilogSource ../xilinx/common/ad_serdes_out.v verilogSource axi_ad9783_channel.v verilogSource axi_ad9783_core.v verilogSource axi_ad9783_if.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_dac_channel.v verilogSource ../common/up_dac_common.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_ad9783.v verilogSource xilinx_xpgui_view_fileset xgui/axi_ad9783_v1_0.tcl tclSource CHECKSUM_668e552f XGUI_VERSION_2 xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource axi_ad9783_v1_0 ID Id 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 DAC_DDS_TYPE Dac Dds Type 2 DAC_DDS_CORDIC_DW Dac Dds Cordic Dw 16 DAC_DDS_CORDIC_PHASE_DW Dac Dds Cordic Phase Dw 16 DAC_DATAPATH_DISABLE Dac Datapath Disable 0 Component_Name axi_ad9783_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices axi_ad9783_v1_0 level_2 package_project Analog Devices https://wiki.analog.com/resources/fpga/docs/axi_ad9783 1 2024-01-14T03:43:14Z 2023.2.1