analog.com user sysid_rom 1.0 clk CLK clk xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog sysid_rom xilinx_anylanguagesynthesis_view_fileset viewChecksum c025daf5 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog sysid_rom xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum c025daf5 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 8f178b19 clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rom_addr in 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rom_data out 31 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ROM_WIDTH Rom Width 32 ROM_ADDR_BITS Rom Addr Bits 6 PATH_TO_FILE Path To File path_to_mem_init_file xilinx_anylanguagesynthesis_view_fileset sysid_rom.v verilogSource CHECKSUM_c025daf5 xilinx_anylanguagebehavioralsimulation_view_fileset sysid_rom.v verilogSource xilinx_xpgui_view_fileset xgui/sysid_rom_v1_0.tcl tclSource CHECKSUM_8f178b19 XGUI_VERSION_2 sysid_rom_v1_0 ROM_WIDTH Rom Width 32 ROM_ADDR_BITS Rom Addr Bits 6 PATH_TO_FILE Path To File path_to_mem_init_file Component_Name sysid_rom_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices sysid_rom_v1_0 level_2 package_project Analog Devices http://www.analog.com 1 2024-01-14T03:53:11Z 2023.2.1