analog.com user axi_adxcvr 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi:m_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW m_axi AWADDR m_axi_awaddr AWPROT m_axi_awprot AWVALID m_axi_awvalid AWREADY m_axi_awready WDATA m_axi_wdata WSTRB m_axi_wstrb WVALID m_axi_wvalid WREADY m_axi_wready BRESP m_axi_bresp BVALID m_axi_bvalid BREADY m_axi_bready ARADDR m_axi_araddr ARPROT m_axi_arprot ARVALID m_axi_arvalid ARREADY m_axi_arready RDATA m_axi_rdata RRESP m_axi_rresp RVALID m_axi_rvalid RREADY m_axi_rready true up_pll_rst RST up_pll_rst POLARITY ACTIVE_HIGH up_cm_0 enb up_cm_enb_0 addr up_cm_addr_0 wr up_cm_wr_0 wdata up_cm_wdata_0 rdata up_cm_rdata_0 ready up_cm_ready_0 true up_es_0 enb up_es_enb_0 addr up_es_addr_0 wr up_es_wr_0 reset up_es_reset_0 wdata up_es_wdata_0 rdata up_es_rdata_0 ready up_es_ready_0 true up_ch_0 pll_locked up_ch_pll_locked_0 rst up_ch_rst_0 user_ready up_ch_user_ready_0 rst_done up_ch_rst_done_0 prbsforceerr up_ch_prbsforceerr_0 prbssel up_ch_prbssel_0 prbscntreset up_ch_prbscntreset_0 prbserr up_ch_prbserr_0 prbslocked up_ch_prbslocked_0 bufstatus up_ch_bufstatus_0 bufstatus_rst up_ch_bufstatus_rst_0 lpm_dfe_n up_ch_lpm_dfe_n_0 rate up_ch_rate_0 sys_clk_sel up_ch_sys_clk_sel_0 out_clk_sel up_ch_out_clk_sel_0 tx_diffctrl up_ch_tx_diffctrl_0 tx_postcursor up_ch_tx_postcursor_0 tx_precursor up_ch_tx_precursor_0 enb up_ch_enb_0 addr up_ch_addr_0 wr up_ch_wr_0 wdata up_ch_wdata_0 rdata up_ch_rdata_0 ready up_ch_ready_0 true up_es_1 enb up_es_enb_1 addr up_es_addr_1 wr up_es_wr_1 reset up_es_reset_1 wdata up_es_wdata_1 rdata up_es_rdata_1 ready up_es_ready_1 true up_ch_1 pll_locked up_ch_pll_locked_1 rst up_ch_rst_1 user_ready up_ch_user_ready_1 rst_done up_ch_rst_done_1 prbsforceerr up_ch_prbsforceerr_1 prbssel up_ch_prbssel_1 prbscntreset up_ch_prbscntreset_1 prbserr up_ch_prbserr_1 prbslocked up_ch_prbslocked_1 bufstatus up_ch_bufstatus_1 bufstatus_rst up_ch_bufstatus_rst_1 lpm_dfe_n up_ch_lpm_dfe_n_1 rate up_ch_rate_1 sys_clk_sel up_ch_sys_clk_sel_1 out_clk_sel up_ch_out_clk_sel_1 tx_diffctrl up_ch_tx_diffctrl_1 tx_postcursor up_ch_tx_postcursor_1 tx_precursor up_ch_tx_precursor_1 enb up_ch_enb_1 addr up_ch_addr_1 wr up_ch_wr_1 wdata up_ch_wdata_1 rdata up_ch_rdata_1 ready up_ch_ready_1 true up_es_2 enb up_es_enb_2 addr up_es_addr_2 wr up_es_wr_2 reset up_es_reset_2 wdata up_es_wdata_2 rdata up_es_rdata_2 ready up_es_ready_2 true up_ch_2 pll_locked up_ch_pll_locked_2 rst up_ch_rst_2 user_ready up_ch_user_ready_2 rst_done up_ch_rst_done_2 prbsforceerr up_ch_prbsforceerr_2 prbssel up_ch_prbssel_2 prbscntreset up_ch_prbscntreset_2 prbserr up_ch_prbserr_2 prbslocked up_ch_prbslocked_2 bufstatus up_ch_bufstatus_2 bufstatus_rst up_ch_bufstatus_rst_2 lpm_dfe_n up_ch_lpm_dfe_n_2 rate up_ch_rate_2 sys_clk_sel up_ch_sys_clk_sel_2 out_clk_sel up_ch_out_clk_sel_2 tx_diffctrl up_ch_tx_diffctrl_2 tx_postcursor up_ch_tx_postcursor_2 tx_precursor up_ch_tx_precursor_2 enb up_ch_enb_2 addr up_ch_addr_2 wr up_ch_wr_2 wdata up_ch_wdata_2 rdata up_ch_rdata_2 ready up_ch_ready_2 true up_es_3 enb up_es_enb_3 addr up_es_addr_3 wr up_es_wr_3 reset up_es_reset_3 wdata up_es_wdata_3 rdata up_es_rdata_3 ready up_es_ready_3 true up_ch_3 pll_locked up_ch_pll_locked_3 rst up_ch_rst_3 user_ready up_ch_user_ready_3 rst_done up_ch_rst_done_3 prbsforceerr up_ch_prbsforceerr_3 prbssel up_ch_prbssel_3 prbscntreset up_ch_prbscntreset_3 prbserr up_ch_prbserr_3 prbslocked up_ch_prbslocked_3 bufstatus up_ch_bufstatus_3 bufstatus_rst up_ch_bufstatus_rst_3 lpm_dfe_n up_ch_lpm_dfe_n_3 rate up_ch_rate_3 sys_clk_sel up_ch_sys_clk_sel_3 out_clk_sel up_ch_out_clk_sel_3 tx_diffctrl up_ch_tx_diffctrl_3 tx_postcursor up_ch_tx_postcursor_3 tx_precursor up_ch_tx_precursor_3 enb up_ch_enb_3 addr up_ch_addr_3 wr up_ch_wr_3 wdata up_ch_wdata_3 rdata up_ch_rdata_3 ready up_ch_ready_3 true up_cm_4 enb up_cm_enb_4 addr up_cm_addr_4 wr up_cm_wr_4 wdata up_cm_wdata_4 rdata up_cm_rdata_4 ready up_cm_ready_4 true up_es_4 enb up_es_enb_4 addr up_es_addr_4 wr up_es_wr_4 reset up_es_reset_4 wdata up_es_wdata_4 rdata up_es_rdata_4 ready up_es_ready_4 true up_ch_4 pll_locked up_ch_pll_locked_4 rst up_ch_rst_4 user_ready up_ch_user_ready_4 rst_done up_ch_rst_done_4 prbsforceerr up_ch_prbsforceerr_4 prbssel up_ch_prbssel_4 prbscntreset up_ch_prbscntreset_4 prbserr up_ch_prbserr_4 prbslocked up_ch_prbslocked_4 bufstatus up_ch_bufstatus_4 bufstatus_rst up_ch_bufstatus_rst_4 lpm_dfe_n up_ch_lpm_dfe_n_4 rate up_ch_rate_4 sys_clk_sel up_ch_sys_clk_sel_4 out_clk_sel up_ch_out_clk_sel_4 tx_diffctrl up_ch_tx_diffctrl_4 tx_postcursor up_ch_tx_postcursor_4 tx_precursor up_ch_tx_precursor_4 enb up_ch_enb_4 addr up_ch_addr_4 wr up_ch_wr_4 wdata up_ch_wdata_4 rdata up_ch_rdata_4 ready up_ch_ready_4 true up_es_5 enb up_es_enb_5 addr up_es_addr_5 wr up_es_wr_5 reset up_es_reset_5 wdata up_es_wdata_5 rdata up_es_rdata_5 ready up_es_ready_5 true up_ch_5 pll_locked up_ch_pll_locked_5 rst up_ch_rst_5 user_ready up_ch_user_ready_5 rst_done up_ch_rst_done_5 prbsforceerr up_ch_prbsforceerr_5 prbssel up_ch_prbssel_5 prbscntreset up_ch_prbscntreset_5 prbserr up_ch_prbserr_5 prbslocked up_ch_prbslocked_5 bufstatus up_ch_bufstatus_5 bufstatus_rst up_ch_bufstatus_rst_5 lpm_dfe_n up_ch_lpm_dfe_n_5 rate up_ch_rate_5 sys_clk_sel up_ch_sys_clk_sel_5 out_clk_sel up_ch_out_clk_sel_5 tx_diffctrl up_ch_tx_diffctrl_5 tx_postcursor up_ch_tx_postcursor_5 tx_precursor up_ch_tx_precursor_5 enb up_ch_enb_5 addr up_ch_addr_5 wr up_ch_wr_5 wdata up_ch_wdata_5 rdata up_ch_rdata_5 ready up_ch_ready_5 true up_es_6 enb up_es_enb_6 addr up_es_addr_6 wr up_es_wr_6 reset up_es_reset_6 wdata up_es_wdata_6 rdata up_es_rdata_6 ready up_es_ready_6 true up_ch_6 pll_locked up_ch_pll_locked_6 rst up_ch_rst_6 user_ready up_ch_user_ready_6 rst_done up_ch_rst_done_6 prbsforceerr up_ch_prbsforceerr_6 prbssel up_ch_prbssel_6 prbscntreset up_ch_prbscntreset_6 prbserr up_ch_prbserr_6 prbslocked up_ch_prbslocked_6 bufstatus up_ch_bufstatus_6 bufstatus_rst up_ch_bufstatus_rst_6 lpm_dfe_n up_ch_lpm_dfe_n_6 rate up_ch_rate_6 sys_clk_sel up_ch_sys_clk_sel_6 out_clk_sel up_ch_out_clk_sel_6 tx_diffctrl up_ch_tx_diffctrl_6 tx_postcursor up_ch_tx_postcursor_6 tx_precursor up_ch_tx_precursor_6 enb up_ch_enb_6 addr up_ch_addr_6 wr up_ch_wr_6 wdata up_ch_wdata_6 rdata up_ch_rdata_6 ready up_ch_ready_6 true up_es_7 enb up_es_enb_7 addr up_es_addr_7 wr up_es_wr_7 reset up_es_reset_7 wdata up_es_wdata_7 rdata up_es_rdata_7 ready up_es_ready_7 true up_ch_7 pll_locked up_ch_pll_locked_7 rst up_ch_rst_7 user_ready up_ch_user_ready_7 rst_done up_ch_rst_done_7 prbsforceerr up_ch_prbsforceerr_7 prbssel up_ch_prbssel_7 prbscntreset up_ch_prbscntreset_7 prbserr up_ch_prbserr_7 prbslocked up_ch_prbslocked_7 bufstatus up_ch_bufstatus_7 bufstatus_rst up_ch_bufstatus_rst_7 lpm_dfe_n up_ch_lpm_dfe_n_7 rate up_ch_rate_7 sys_clk_sel up_ch_sys_clk_sel_7 out_clk_sel up_ch_out_clk_sel_7 tx_diffctrl up_ch_tx_diffctrl_7 tx_postcursor up_ch_tx_postcursor_7 tx_precursor up_ch_tx_precursor_7 enb up_ch_enb_7 addr up_ch_addr_7 wr up_ch_wr_7 wdata up_ch_wdata_7 rdata up_ch_rdata_7 ready up_ch_ready_7 true up_cm_8 enb up_cm_enb_8 addr up_cm_addr_8 wr up_cm_wr_8 wdata up_cm_wdata_8 rdata up_cm_rdata_8 ready up_cm_ready_8 false up_es_8 enb up_es_enb_8 addr up_es_addr_8 wr up_es_wr_8 reset up_es_reset_8 wdata up_es_wdata_8 rdata up_es_rdata_8 ready up_es_ready_8 false up_ch_8 pll_locked up_ch_pll_locked_8 rst up_ch_rst_8 user_ready up_ch_user_ready_8 rst_done up_ch_rst_done_8 prbsforceerr up_ch_prbsforceerr_8 prbssel up_ch_prbssel_8 prbscntreset up_ch_prbscntreset_8 prbserr up_ch_prbserr_8 prbslocked up_ch_prbslocked_8 bufstatus up_ch_bufstatus_8 bufstatus_rst up_ch_bufstatus_rst_8 lpm_dfe_n up_ch_lpm_dfe_n_8 rate up_ch_rate_8 sys_clk_sel up_ch_sys_clk_sel_8 out_clk_sel up_ch_out_clk_sel_8 tx_diffctrl up_ch_tx_diffctrl_8 tx_postcursor up_ch_tx_postcursor_8 tx_precursor up_ch_tx_precursor_8 enb up_ch_enb_8 addr up_ch_addr_8 wr up_ch_wr_8 wdata up_ch_wdata_8 rdata up_ch_rdata_8 ready up_ch_ready_8 false up_es_9 enb up_es_enb_9 addr up_es_addr_9 wr up_es_wr_9 reset up_es_reset_9 wdata up_es_wdata_9 rdata up_es_rdata_9 ready up_es_ready_9 false up_ch_9 pll_locked up_ch_pll_locked_9 rst up_ch_rst_9 user_ready up_ch_user_ready_9 rst_done up_ch_rst_done_9 prbsforceerr up_ch_prbsforceerr_9 prbssel up_ch_prbssel_9 prbscntreset up_ch_prbscntreset_9 prbserr up_ch_prbserr_9 prbslocked up_ch_prbslocked_9 bufstatus up_ch_bufstatus_9 bufstatus_rst up_ch_bufstatus_rst_9 lpm_dfe_n up_ch_lpm_dfe_n_9 rate up_ch_rate_9 sys_clk_sel up_ch_sys_clk_sel_9 out_clk_sel up_ch_out_clk_sel_9 tx_diffctrl up_ch_tx_diffctrl_9 tx_postcursor up_ch_tx_postcursor_9 tx_precursor up_ch_tx_precursor_9 enb up_ch_enb_9 addr up_ch_addr_9 wr up_ch_wr_9 wdata up_ch_wdata_9 rdata up_ch_rdata_9 ready up_ch_ready_9 false up_es_10 enb up_es_enb_10 addr up_es_addr_10 wr up_es_wr_10 reset up_es_reset_10 wdata up_es_wdata_10 rdata up_es_rdata_10 ready up_es_ready_10 false up_ch_10 pll_locked up_ch_pll_locked_10 rst up_ch_rst_10 user_ready up_ch_user_ready_10 rst_done up_ch_rst_done_10 prbsforceerr up_ch_prbsforceerr_10 prbssel up_ch_prbssel_10 prbscntreset up_ch_prbscntreset_10 prbserr up_ch_prbserr_10 prbslocked up_ch_prbslocked_10 bufstatus up_ch_bufstatus_10 bufstatus_rst up_ch_bufstatus_rst_10 lpm_dfe_n up_ch_lpm_dfe_n_10 rate up_ch_rate_10 sys_clk_sel up_ch_sys_clk_sel_10 out_clk_sel up_ch_out_clk_sel_10 tx_diffctrl up_ch_tx_diffctrl_10 tx_postcursor up_ch_tx_postcursor_10 tx_precursor up_ch_tx_precursor_10 enb up_ch_enb_10 addr up_ch_addr_10 wr up_ch_wr_10 wdata up_ch_wdata_10 rdata up_ch_rdata_10 ready up_ch_ready_10 false up_es_11 enb up_es_enb_11 addr up_es_addr_11 wr up_es_wr_11 reset up_es_reset_11 wdata up_es_wdata_11 rdata up_es_rdata_11 ready up_es_ready_11 false up_ch_11 pll_locked up_ch_pll_locked_11 rst up_ch_rst_11 user_ready up_ch_user_ready_11 rst_done up_ch_rst_done_11 prbsforceerr up_ch_prbsforceerr_11 prbssel up_ch_prbssel_11 prbscntreset up_ch_prbscntreset_11 prbserr up_ch_prbserr_11 prbslocked up_ch_prbslocked_11 bufstatus up_ch_bufstatus_11 bufstatus_rst up_ch_bufstatus_rst_11 lpm_dfe_n up_ch_lpm_dfe_n_11 rate up_ch_rate_11 sys_clk_sel up_ch_sys_clk_sel_11 out_clk_sel up_ch_out_clk_sel_11 tx_diffctrl up_ch_tx_diffctrl_11 tx_postcursor up_ch_tx_postcursor_11 tx_precursor up_ch_tx_precursor_11 enb up_ch_enb_11 addr up_ch_addr_11 wr up_ch_wr_11 wdata up_ch_wdata_11 rdata up_ch_rdata_11 ready up_ch_ready_11 false up_cm_12 enb up_cm_enb_12 addr up_cm_addr_12 wr up_cm_wr_12 wdata up_cm_wdata_12 rdata up_cm_rdata_12 ready up_cm_ready_12 false up_es_12 enb up_es_enb_12 addr up_es_addr_12 wr up_es_wr_12 reset up_es_reset_12 wdata up_es_wdata_12 rdata up_es_rdata_12 ready up_es_ready_12 false up_ch_12 pll_locked up_ch_pll_locked_12 rst up_ch_rst_12 user_ready up_ch_user_ready_12 rst_done up_ch_rst_done_12 prbsforceerr up_ch_prbsforceerr_12 prbssel up_ch_prbssel_12 prbscntreset up_ch_prbscntreset_12 prbserr up_ch_prbserr_12 prbslocked up_ch_prbslocked_12 bufstatus up_ch_bufstatus_12 bufstatus_rst up_ch_bufstatus_rst_12 lpm_dfe_n up_ch_lpm_dfe_n_12 rate up_ch_rate_12 sys_clk_sel up_ch_sys_clk_sel_12 out_clk_sel up_ch_out_clk_sel_12 tx_diffctrl up_ch_tx_diffctrl_12 tx_postcursor up_ch_tx_postcursor_12 tx_precursor up_ch_tx_precursor_12 enb up_ch_enb_12 addr up_ch_addr_12 wr up_ch_wr_12 wdata up_ch_wdata_12 rdata up_ch_rdata_12 ready up_ch_ready_12 false up_es_13 enb up_es_enb_13 addr up_es_addr_13 wr up_es_wr_13 reset up_es_reset_13 wdata up_es_wdata_13 rdata up_es_rdata_13 ready up_es_ready_13 false up_ch_13 pll_locked up_ch_pll_locked_13 rst up_ch_rst_13 user_ready up_ch_user_ready_13 rst_done up_ch_rst_done_13 prbsforceerr up_ch_prbsforceerr_13 prbssel up_ch_prbssel_13 prbscntreset up_ch_prbscntreset_13 prbserr up_ch_prbserr_13 prbslocked up_ch_prbslocked_13 bufstatus up_ch_bufstatus_13 bufstatus_rst up_ch_bufstatus_rst_13 lpm_dfe_n up_ch_lpm_dfe_n_13 rate up_ch_rate_13 sys_clk_sel up_ch_sys_clk_sel_13 out_clk_sel up_ch_out_clk_sel_13 tx_diffctrl up_ch_tx_diffctrl_13 tx_postcursor up_ch_tx_postcursor_13 tx_precursor up_ch_tx_precursor_13 enb up_ch_enb_13 addr up_ch_addr_13 wr up_ch_wr_13 wdata up_ch_wdata_13 rdata up_ch_rdata_13 ready up_ch_ready_13 false up_es_14 enb up_es_enb_14 addr up_es_addr_14 wr up_es_wr_14 reset up_es_reset_14 wdata up_es_wdata_14 rdata up_es_rdata_14 ready up_es_ready_14 false up_ch_14 pll_locked up_ch_pll_locked_14 rst up_ch_rst_14 user_ready up_ch_user_ready_14 rst_done up_ch_rst_done_14 prbsforceerr up_ch_prbsforceerr_14 prbssel up_ch_prbssel_14 prbscntreset up_ch_prbscntreset_14 prbserr up_ch_prbserr_14 prbslocked up_ch_prbslocked_14 bufstatus up_ch_bufstatus_14 bufstatus_rst up_ch_bufstatus_rst_14 lpm_dfe_n up_ch_lpm_dfe_n_14 rate up_ch_rate_14 sys_clk_sel up_ch_sys_clk_sel_14 out_clk_sel up_ch_out_clk_sel_14 tx_diffctrl up_ch_tx_diffctrl_14 tx_postcursor up_ch_tx_postcursor_14 tx_precursor up_ch_tx_precursor_14 enb up_ch_enb_14 addr up_ch_addr_14 wr up_ch_wr_14 wdata up_ch_wdata_14 rdata up_ch_rdata_14 ready up_ch_ready_14 false up_es_15 enb up_es_enb_15 addr up_es_addr_15 wr up_es_wr_15 reset up_es_reset_15 wdata up_es_wdata_15 rdata up_es_rdata_15 ready up_es_ready_15 false up_ch_15 pll_locked up_ch_pll_locked_15 rst up_ch_rst_15 user_ready up_ch_user_ready_15 rst_done up_ch_rst_done_15 prbsforceerr up_ch_prbsforceerr_15 prbssel up_ch_prbssel_15 prbscntreset up_ch_prbscntreset_15 prbserr up_ch_prbserr_15 prbslocked up_ch_prbslocked_15 bufstatus up_ch_bufstatus_15 bufstatus_rst up_ch_bufstatus_rst_15 lpm_dfe_n up_ch_lpm_dfe_n_15 rate up_ch_rate_15 sys_clk_sel up_ch_sys_clk_sel_15 out_clk_sel up_ch_out_clk_sel_15 tx_diffctrl up_ch_tx_diffctrl_15 tx_postcursor up_ch_tx_postcursor_15 tx_precursor up_ch_tx_precursor_15 enb up_ch_enb_15 addr up_ch_addr_15 wr up_ch_wr_15 wdata up_ch_wdata_15 rdata up_ch_rdata_15 ready up_ch_ready_15 false up_cm_16 enb up_cm_enb_16 addr up_cm_addr_16 wr up_cm_wr_16 wdata up_cm_wdata_16 rdata up_cm_rdata_16 ready up_cm_ready_16 false up_es_16 enb up_es_enb_16 addr up_es_addr_16 wr up_es_wr_16 reset up_es_reset_16 wdata up_es_wdata_16 rdata up_es_rdata_16 ready up_es_ready_16 false up_ch_16 pll_locked up_ch_pll_locked_16 rst up_ch_rst_16 user_ready up_ch_user_ready_16 rst_done up_ch_rst_done_16 prbsforceerr up_ch_prbsforceerr_16 prbssel up_ch_prbssel_16 prbscntreset up_ch_prbscntreset_16 prbserr up_ch_prbserr_16 prbslocked up_ch_prbslocked_16 bufstatus up_ch_bufstatus_16 bufstatus_rst up_ch_bufstatus_rst_16 lpm_dfe_n up_ch_lpm_dfe_n_16 rate up_ch_rate_16 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9 10 11 12 13 14 15 16 17 18 19 20 choice_pairs_07421b06 0 1 2 3 4 5 6 7 8 9 10 choice_pairs_1942b210 2 1 choice_pairs_19f99f31 0 10 11 12 13 14 20 21 22 23 24 25 30 choice_pairs_28f798a2 0 1 2 3 4 choice_pairs_fc01a186 0 1 2 3 4 5 6 xilinx_anylanguagesynthesis_view_fileset axi_adxcvr_es.v verilogSource axi_adxcvr_mdrp.v verilogSource axi_adxcvr_mstatus.v verilogSource axi_adxcvr_up.v verilogSource ../../common/up_axi.v verilogSource ../../scripts/adi_xilinx_device_info_enc.tcl tclSource axi_adxcvr.v verilogSource CHECKSUM_7c4853b1 xilinx_anylanguagebehavioralsimulation_view_fileset axi_adxcvr_es.v verilogSource axi_adxcvr_mdrp.v verilogSource axi_adxcvr_mstatus.v verilogSource axi_adxcvr_up.v verilogSource ../../common/up_axi.v verilogSource ../../scripts/adi_xilinx_device_info_enc.tcl tclSource axi_adxcvr.v verilogSource xilinx_xpgui_view_fileset xgui/axi_adxcvr_v1_0.tcl tclSource CHECKSUM_ab0e6f88 XGUI_VERSION_2 xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource axi_adxcvr_v1_0 ID Id 0 NUM_OF_LANES Num Of Lanes 8 XCVR_TYPE Xcvr Type 0 LINK_MODE Link Layer mode 1 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 FPGA_VOLTAGE Fpga Voltage 0 TX_OR_RX_N Tx Or Rx N 0 QPLL_ENABLE Qpll Enable 1 LPM_OR_DFE_N Lpm Or Dfe N 1 RATE Rate "000" TX_DIFFCTRL Tx Diffctrl "01000" TX_POSTCURSOR Tx Postcursor "00000" TX_PRECURSOR Tx Precursor "00000" SYS_CLK_SEL Sys Clk Sel "11" OUT_CLK_SEL Out Clk Sel "100" Component_Name axi_adxcvr_v1_0 virtex7 /Analog_Devices axi_adxcvr_v1_0 level_2 package_project Analog Devices https://wiki.analog.com/resources/fpga/docs/axi_adxcvr 1 2024-01-14T03:57:27Z 2023.2.1