analog.com user axi_gpreg 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis SystemVerilog axi_gpreg xilinx_anylanguagesynthesis_view_fileset viewChecksum c4ab9d05 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation SystemVerilog axi_gpreg xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 5ca46b5b xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 1616057c up_gp_ioenb_0 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true up_gp_out_0 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true up_gp_in_0 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true up_gp_ioenb_1 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true up_gp_out_1 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true up_gp_in_1 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true up_gp_ioenb_2 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true up_gp_out_2 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true up_gp_in_2 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true up_gp_ioenb_3 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true up_gp_out_3 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true up_gp_in_3 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true up_gp_ioenb_4 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true up_gp_out_4 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true up_gp_in_4 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true up_gp_ioenb_5 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true up_gp_out_5 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true up_gp_in_5 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true up_gp_ioenb_6 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true up_gp_out_6 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true up_gp_in_6 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true up_gp_ioenb_7 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true up_gp_out_7 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true up_gp_in_7 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true d_clk_0 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true d_clk_1 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true d_clk_2 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true d_clk_3 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true d_clk_4 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true d_clk_5 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true d_clk_6 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true d_clk_7 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ID Id 0 NUM_OF_IO Num Of Io 8 NUM_OF_CLK_MONS Num Of Clk Mons 8 BUF_ENABLE_0 Buf Enable 0 1 BUF_ENABLE_1 Buf Enable 1 1 BUF_ENABLE_2 Buf Enable 2 1 BUF_ENABLE_3 Buf Enable 3 1 BUF_ENABLE_4 Buf Enable 4 1 BUF_ENABLE_5 Buf Enable 5 1 BUF_ENABLE_6 Buf Enable 6 1 BUF_ENABLE_7 Buf Enable 7 1 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset axi_gpreg_constr.ttcl ttcl ../xilinx/common/ad_rst_constr.xdc xdc ../common/ad_rst.v verilogSource axi_gpreg_clock_mon.v verilogSource axi_gpreg_io.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource axi_gpreg.v systemVerilogSource CHECKSUM_eb2994e4 xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_rst.v verilogSource axi_gpreg_clock_mon.v verilogSource axi_gpreg_io.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource axi_gpreg.v systemVerilogSource xilinx_xpgui_view_fileset xgui/axi_gpreg_v1_0.tcl tclSource CHECKSUM_1616057c XGUI_VERSION_2 axi_gpreg_v1_0 ID Id 0 NUM_OF_IO Num Of Io 8 NUM_OF_CLK_MONS Num Of Clk Mons 8 BUF_ENABLE_0 Buf Enable 0 1 BUF_ENABLE_1 Buf Enable 1 1 BUF_ENABLE_2 Buf Enable 2 1 BUF_ENABLE_3 Buf Enable 3 1 BUF_ENABLE_4 Buf Enable 4 1 BUF_ENABLE_5 Buf Enable 5 1 BUF_ENABLE_6 Buf Enable 6 1 BUF_ENABLE_7 Buf Enable 7 1 Component_Name axi_gpreg_v1_0 virtex7 /Analog_Devices axi_gpreg_v1_0 level_2 package_project Analog Devices http://www.analog.com 1 2024-01-14T03:46:51Z 2023.2.1