analog.com user jesd204_tx 1.0 tx_data TVALID tx_valid TREADY tx_ready TDATA tx_data tx_phy0 txdata phy_data 31 0 txcharisk phy_charisk 3 0 txheader phy_header 1 0 true tx_phy1 txdata phy_data 63 32 txcharisk phy_charisk 7 4 txheader phy_header 3 2 false tx_phy2 txdata phy_data 95 64 txcharisk phy_charisk 11 8 txheader phy_header 5 4 false tx_phy3 txdata phy_data 127 96 txcharisk phy_charisk 15 12 txheader phy_header 7 6 false tx_phy4 txdata phy_data 159 128 txcharisk phy_charisk 19 16 txheader phy_header 9 8 false tx_phy5 txdata phy_data 191 160 txcharisk phy_charisk 23 20 txheader phy_header 11 10 false tx_phy6 txdata phy_data 223 192 txcharisk phy_charisk 27 24 txheader phy_header 13 12 false tx_phy7 txdata phy_data 255 224 txcharisk phy_charisk 31 28 txheader phy_header 15 14 false tx_phy8 txdata phy_data 287 256 txcharisk phy_charisk 35 32 txheader phy_header 17 16 false tx_phy9 txdata phy_data 319 288 txcharisk phy_charisk 39 36 txheader phy_header 19 18 false tx_phy10 txdata phy_data 351 320 txcharisk phy_charisk 43 40 txheader phy_header 21 20 false tx_phy11 txdata phy_data 383 352 txcharisk phy_charisk 47 44 txheader phy_header 23 22 false tx_phy12 txdata phy_data 415 384 txcharisk phy_charisk 51 48 txheader phy_header 25 24 false tx_phy13 txdata phy_data 447 416 txcharisk phy_charisk 55 52 txheader phy_header 27 26 false tx_phy14 txdata phy_data 479 448 txcharisk phy_charisk 59 56 txheader phy_header 29 28 false tx_phy15 txdata phy_data 511 480 txcharisk phy_charisk 63 60 txheader phy_header 31 30 false tx_phy16 txdata phy_data 543 512 txcharisk phy_charisk 67 64 txheader phy_header 33 32 false tx_phy17 txdata phy_data 575 544 txcharisk phy_charisk 71 68 txheader phy_header 35 34 false tx_phy18 txdata phy_data 607 576 txcharisk phy_charisk 75 72 txheader phy_header 37 36 false tx_phy19 txdata phy_data 639 608 txcharisk phy_charisk 79 76 txheader phy_header 39 38 false tx_phy20 txdata phy_data 671 640 txcharisk phy_charisk 83 80 txheader phy_header 41 40 false tx_phy21 txdata phy_data 703 672 txcharisk phy_charisk 87 84 txheader phy_header 43 42 false tx_phy22 txdata phy_data 735 704 txcharisk phy_charisk 91 88 txheader phy_header 45 44 false tx_phy23 txdata phy_data 767 736 txcharisk phy_charisk 95 92 txheader phy_header 47 46 false tx_phy24 txdata phy_data 799 768 txcharisk phy_charisk 99 96 txheader phy_header 49 48 false tx_phy25 txdata phy_data 831 800 txcharisk phy_charisk 103 100 txheader phy_header 51 50 false tx_phy26 txdata phy_data 863 832 txcharisk phy_charisk 107 104 txheader phy_header 53 52 false tx_phy27 txdata phy_data 895 864 txcharisk phy_charisk 111 108 txheader phy_header 55 54 false tx_phy28 txdata phy_data 927 896 txcharisk phy_charisk 115 112 txheader phy_header 57 56 false tx_phy29 txdata phy_data 959 928 txcharisk phy_charisk 119 116 txheader phy_header 59 58 false tx_phy30 txdata phy_data 991 960 txcharisk phy_charisk 123 120 txheader phy_header 61 60 false tx_phy31 txdata phy_data 1023 992 txcharisk phy_charisk 127 124 txheader phy_header 63 62 false tx_cfg lanes_disable cfg_lanes_disable links_disable cfg_links_disable octets_per_multiframe cfg_octets_per_multiframe octets_per_frame cfg_octets_per_frame continuous_cgs cfg_continuous_cgs continuous_ilas cfg_continuous_ilas skip_ilas cfg_skip_ilas mframes_per_ilas cfg_mframes_per_ilas disable_char_replacement cfg_disable_char_replacement disable_scrambler cfg_disable_scrambler device_octets_per_multiframe device_cfg_octets_per_multiframe device_octets_per_frame device_cfg_octets_per_frame device_beats_per_multiframe device_cfg_beats_per_multiframe device_lmfc_offset device_cfg_lmfc_offset device_sysref_oneshot device_cfg_sysref_oneshot device_sysref_disable device_cfg_sysref_disable tx_ilas_config rd ilas_config_rd addr ilas_config_addr data ilas_config_data true tx_event sysref_alignment_error device_event_sysref_alignment_error sysref_edge device_event_sysref_edge tx_status state status_state sync status_sync synth_params0 status_synth_params0 synth_params1 status_synth_params1 synth_params2 status_synth_params2 tx_ctrl manual_sync_request ctrl_manual_sync_request true tx_cfg_tx_ilas_config_tx_event_tx_status_tx_ctrl_signal_clock tx_cfg_tx_ilas_config_tx_event_tx_status_tx_ctrl_signal_clock CLK clk ASSOCIATED_BUSIF tx_cfg:tx_ilas_config:tx_event:tx_status:tx_ctrl ASSOCIATED_RESET reset tx_cfg_tx_ilas_config_tx_event_tx_status_tx_ctrl_signal_reset tx_cfg_tx_ilas_config_tx_event_tx_status_tx_ctrl_signal_reset RST reset POLARITY ACTIVE_HIGH tx_data_signal_clock tx_data_signal_clock CLK device_clk ASSOCIATED_BUSIF tx_data ASSOCIATED_RESET device_reset tx_data_signal_reset tx_data_signal_reset RST device_reset POLARITY ACTIVE_HIGH xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog jesd204_tx xilinx_anylanguagesynthesis_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum df6c408b xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog jesd204_tx xilinx_anylanguagebehavioralsimulation_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum df6c408b xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum e83e8551 xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_blockdiagram_view_fileset xilinx_utilityxitfiles Utility XIT/TTCL :vivado.xilinx.com:xit.util xilinx_utilityxitfiles_view_fileset clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation phy_data out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation phy_charisk out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation phy_header out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sysref in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation lmfc_edge out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation lmfc_clk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true tx_data in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 tx_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tx_eof out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tx_sof out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tx_somf out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tx_eomf out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tx_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_lanes_disable in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_links_disable in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_octets_per_multiframe in 9 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_octets_per_frame in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_continuous_cgs in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_continuous_ilas in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_skip_ilas in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_mframes_per_ilas in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_disable_char_replacement in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_disable_scrambler in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_octets_per_multiframe in 9 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_octets_per_frame in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_beats_per_multiframe in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_lmfc_offset in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_sysref_oneshot in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_sysref_disable in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ilas_config_rd out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ilas_config_addr out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ilas_config_data in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ctrl_manual_sync_request in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 device_event_sysref_edge out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_event_sysref_alignment_error out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_sync out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_state out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_synth_params0 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_synth_params1 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_synth_params2 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 NUM_OUTPUT_PIPELINE Num Output Pipeline 0 LINK_MODE Link Mode 1 DATA_PATH_WIDTH Data Path Width 4 TPL_DATA_PATH_WIDTH Tpl Data Path Width 4 ENABLE_CHAR_REPLACE Enable Char Replace "0" ASYNC_CLK Async Clk 1 choice_pairs_1942b210 2 1 xilinx_anylanguagesynthesis_view_fileset jesd204_tx_ooc.ttcl ttcl jesd204_tx_constr.ttcl ttcl jesd204_tx_lane.v verilogSource jesd204_tx_lane_64b.v verilogSource jesd204_tx_header.v verilogSource jesd204_tx_gearbox.v verilogSource jesd204_tx_ctrl.v verilogSource ../../common/ad_pack.v verilogSource ../../common/ad_upack.v verilogSource bd/bd.tcl tclSource jesd204_tx.v verilogSource CHECKSUM_b8083ac0 xilinx_anylanguagesynthesis_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset jesd204_tx_lane.v verilogSource jesd204_tx_lane_64b.v verilogSource jesd204_tx_header.v verilogSource jesd204_tx_gearbox.v verilogSource jesd204_tx_ctrl.v verilogSource ../../common/ad_pack.v verilogSource ../../common/ad_upack.v verilogSource bd/bd.tcl tclSource jesd204_tx.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/jesd204_tx_v1_0.tcl tclSource CHECKSUM_62c3c738 XGUI_VERSION_2 xilinx_xpgui_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource xilinx_blockdiagram_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_utilityxitfiles_view_fileset gui/jesd204_tx_v1_0.gtcl GTCL ADI JESD204 Transmit NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 NUM_OUTPUT_PIPELINE Num Output Pipeline 0 LINK_MODE Link Layer mode 1 DATA_PATH_WIDTH Data Path Width 4 true TPL_DATA_PATH_WIDTH Tpl Data Path Width 4 ENABLE_CHAR_REPLACE Enable Char Replace "0" ASYNC_CLK Link and Device Clock Asynchronous 1 Component_Name jesd204_tx_v1_0 SYSREF_IOB Place SYSREF in IOB true virtex7 /Analog_Devices ADI JESD204 Transmit level_2 package_project Analog Devices http://www.analog.com 1 2024-01-14T03:52:01Z 2023.2.1