analog.com user util_cic 1.0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog cic_comb xilinx_anylanguagesynthesis_view_fileset viewChecksum 55312928 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog cic_comb xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 55312928 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum fe1ab863 clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ce in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation enable in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation DATA_WIDTH Data Width 32 SEQ Seq 1 STAGE_WIDTH Stage Width 1 NUM_STAGES Num Stages 1 xilinx_anylanguagesynthesis_view_fileset cic_int.v verilogSource cic_comb.v verilogSource CHECKSUM_17b13b1f xilinx_anylanguagebehavioralsimulation_view_fileset cic_int.v verilogSource cic_comb.v verilogSource xilinx_xpgui_view_fileset xgui/cic_comb_v1_0.tcl tclSource CHECKSUM_fe1ab863 XGUI_VERSION_2 CIC building blocks DATA_WIDTH Data Width 32 SEQ Seq 1 STAGE_WIDTH Stage Width 1 NUM_STAGES Num Stages 1 Component_Name cic_comb_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices CIC building blocks true level_2 package_project Analog Devices http://www.analog.com 1 2024-01-14T03:44:04Z 2023.2.1