analog.com user util_wfifo 1.0 din_clk CLK din_clk ASSOCIATED_RESET din_rst din_rst RST din_rst dout_clk CLK dout_clk ASSOCIATED_RESET dout_rstn dout_rstn RST dout_rstn POLARITY ACTIVE_LOW xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_wfifo xilinx_anylanguagesynthesis_view_fileset viewChecksum a2e0367c xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_wfifo xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 3ce14e9d xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 70b62934 din_rst in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation din_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation din_enable_0 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 din_valid_0 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 din_data_0 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 din_enable_1 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true din_valid_1 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true din_data_1 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true din_enable_2 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true din_valid_2 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true din_data_2 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true din_enable_3 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true din_valid_3 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true din_data_3 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true din_enable_4 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_valid_4 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_data_4 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_enable_5 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_valid_5 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_data_5 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_enable_6 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_valid_6 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_data_6 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_enable_7 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_valid_7 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_data_7 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_ovf out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dout_rstn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dout_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dout_enable_0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dout_valid_0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dout_data_0 out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dout_enable_1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true dout_valid_1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true dout_data_1 out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true dout_enable_2 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true dout_valid_2 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true dout_data_2 out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true dout_enable_3 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true dout_valid_3 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true dout_data_3 out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true dout_enable_4 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dout_valid_4 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dout_data_4 out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dout_enable_5 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dout_valid_5 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dout_data_5 out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dout_enable_6 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dout_valid_6 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dout_data_6 out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dout_enable_7 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dout_valid_7 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dout_data_7 out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dout_ovf in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 NUM_OF_CHANNELS Num Of Channels 4 DIN_DATA_WIDTH Din Data Width 32 DOUT_DATA_WIDTH Dout Data Width 64 DIN_ADDRESS_WIDTH Din Address Width 8 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset util_wfifo_constr.xdc xdc ../common/ad_mem.v verilogSource util_wfifo.v verilogSource CHECKSUM_5ef3b9cd xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_mem.v verilogSource util_wfifo.v verilogSource xilinx_xpgui_view_fileset xgui/util_wfifo_v1_0.tcl tclSource CHECKSUM_70b62934 XGUI_VERSION_2 util_wfifo_v1_0 NUM_OF_CHANNELS Num Of Channels 4 DIN_DATA_WIDTH Din Data Width 32 DOUT_DATA_WIDTH Dout Data Width 64 DIN_ADDRESS_WIDTH Din Address Width 8 Component_Name util_wfifo_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices util_wfifo_v1_0 level_2 package_project Analog Devices https://wiki.analog.com/resources/fpga/docs/util_wfifo 1 2024-06-06T03:14:40Z 2024.1