analog.com
user
axi_dacfifo
1.0
axi
AWID
axi_awid
AWADDR
axi_awaddr
AWLEN
axi_awlen
AWSIZE
axi_awsize
AWBURST
axi_awburst
AWLOCK
axi_awlock
AWCACHE
axi_awcache
AWPROT
axi_awprot
AWQOS
axi_awqos
AWVALID
axi_awvalid
AWREADY
axi_awready
WDATA
axi_wdata
WSTRB
axi_wstrb
WLAST
axi_wlast
WVALID
axi_wvalid
WREADY
axi_wready
BID
axi_bid
BRESP
axi_bresp
BVALID
axi_bvalid
BREADY
axi_bready
ARID
axi_arid
ARADDR
axi_araddr
ARLEN
axi_arlen
ARSIZE
axi_arsize
ARBURST
axi_arburst
ARLOCK
axi_arlock
ARCACHE
axi_arcache
ARPROT
axi_arprot
ARQOS
axi_arqos
ARVALID
axi_arvalid
ARREADY
axi_arready
RID
axi_rid
RDATA
axi_rdata
RRESP
axi_rresp
RLAST
axi_rlast
RVALID
axi_rvalid
RREADY
axi_rready
axi_clk
CLK
axi_clk
ASSOCIATED_BUSIF
axi
ASSOCIATED_RESET
axi_resetn
axi_resetn
RST
axi_resetn
POLARITY
ACTIVE_LOW
dma_clk
CLK
dma_clk
ASSOCIATED_RESET
dma_rst
dma_rst
RST
dma_rst
dac_clk
CLK
dac_clk
ASSOCIATED_RESET
dac_rst
dac_rst
RST
dac_rst
axi
4294967296
512
xilinx_anylanguagesynthesis
Synthesis
:vivado.xilinx.com:synthesis
Verilog
axi_dacfifo
xilinx_anylanguagesynthesis_view_fileset
viewChecksum
4534e2ce
xilinx_anylanguagebehavioralsimulation
Simulation
:vivado.xilinx.com:simulation
Verilog
axi_dacfifo
xilinx_anylanguagebehavioralsimulation_view_fileset
viewChecksum
0e1eccf3
xilinx_xpgui
UI Layout
:vivado.xilinx.com:xgui.ui
xilinx_xpgui_view_fileset
viewChecksum
bde7c6b3
dma_clk
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
dma_rst
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
dma_valid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
dma_data
in
63
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
dma_ready
out
reg
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
dma_xfer_req
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
dma_xfer_last
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
dac_clk
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
dac_rst
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
dac_valid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
dac_data
out
63
0
reg
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
dac_dunf
out
reg
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
dac_xfer_out
out
reg
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
bypass
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_clk
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_resetn
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_awvalid
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_awid
out
3
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_awburst
out
1
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_awlock
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_awcache
out
3
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_awprot
out
2
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_awqos
out
3
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_awlen
out
7
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_awsize
out
2
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_awaddr
out
31
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_awready
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
axi_wvalid
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_wdata
out
511
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_wstrb
out
63
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_wlast
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_wready
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
axi_bvalid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
axi_bid
in
3
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
axi_bresp
in
1
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
axi_bready
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_arvalid
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_arid
out
3
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_arburst
out
1
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_arlock
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_arcache
out
3
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_arprot
out
2
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_arqos
out
3
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_arlen
out
7
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_arsize
out
2
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_araddr
out
31
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
axi_arready
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
axi_rvalid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
axi_rid
in
3
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
axi_rresp
in
1
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
axi_rlast
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
axi_rdata
in
511
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
axi_rready
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
DAC_DATA_WIDTH
Dac Data Width
64
DMA_DATA_WIDTH
Dma Data Width
64
AXI_DATA_WIDTH
Axi Data Width
512
AXI_SIZE
Axi Size
2
AXI_LENGTH
Axi Length
15
AXI_ADDRESS
Axi Address
0x00000000
AXI_ADDRESS_LIMIT
Axi Address Limit
0xFFFFFFFF
choice_list_74b5137e
ACTIVE_HIGH
ACTIVE_LOW
xilinx_anylanguagesynthesis_view_fileset
axi_dacfifo_constr.xdc
xdc
../../common/ad_axis_inf_rx.v
verilogSource
../../common/ad_b2g.v
verilogSource
../../common/ad_g2b.v
verilogSource
../../common/ad_mem.v
verilogSource
../../common/ad_mem_asym.v
verilogSource
axi_dacfifo_address_buffer.v
verilogSource
axi_dacfifo_rd.v
verilogSource
axi_dacfifo_wr.v
verilogSource
../../util_dacfifo/util_dacfifo_bypass.v
verilogSource
axi_dacfifo.v
verilogSource
CHECKSUM_596be823
xilinx_anylanguagebehavioralsimulation_view_fileset
../../common/ad_axis_inf_rx.v
verilogSource
../../common/ad_b2g.v
verilogSource
../../common/ad_g2b.v
verilogSource
../../common/ad_mem.v
verilogSource
../../common/ad_mem_asym.v
verilogSource
axi_dacfifo_address_buffer.v
verilogSource
axi_dacfifo_rd.v
verilogSource
axi_dacfifo_wr.v
verilogSource
../../util_dacfifo/util_dacfifo_bypass.v
verilogSource
axi_dacfifo.v
verilogSource
xilinx_xpgui_view_fileset
xgui/axi_dacfifo_v1_0.tcl
tclSource
CHECKSUM_bde7c6b3
XGUI_VERSION_2
axi_dacfifo_v1_0
DAC_DATA_WIDTH
Dac Data Width
64
DMA_DATA_WIDTH
Dma Data Width
64
AXI_DATA_WIDTH
Axi Data Width
512
AXI_SIZE
Axi Size
2
AXI_LENGTH
Axi Length
15
AXI_ADDRESS
Axi Address
0x00000000
AXI_ADDRESS_LIMIT
Axi Address Limit
0xFFFFFFFF
Component_Name
axi_dacfifo_v1_0
virtex7
qvirtex7
versal
kintex7
kintex7l
qkintex7
qkintex7l
akintex7
artix7
artix7l
aartix7
qartix7
zynq
qzynq
azynq
spartan7
aspartan7
virtexu
zynquplus
virtexuplus
virtexuplusHBM
virtexuplus58g
kintexuplus
artixuplus
kintexu
/Analog_Devices
axi_dacfifo_v1_0
level_2
package_project
Analog Devices
http://www.analog.com
1
2024-06-06T03:15:22Z
2024.1