analog.com user axi_laser_driver 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW ext_clk CLK ext_clk s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_laser_driver xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_axi_pulse_gen_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum 6f3005fd xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_laser_driver xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_axi_pulse_gen_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 0bdfec18 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_axi_pulse_gen_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum ce5d3fb0 s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ext_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true driver_en_n out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation driver_pulse out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation driver_otw_n in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation driver_dp_reset out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tia_chsel out 7 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation irq out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ID Id 0 ASYNC_CLK_EN Async Clk En true PULSE_WIDTH Pulse Width 7 PULSE_PERIOD Pulse Period 10 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset ../axi_pulse_gen/axi_pulse_gen_constr.ttcl ttcl ../xilinx/common/up_clock_mon_constr.xdc xdc axi_laser_driver_constr.xdc xdc axi_laser_driver_regmap.v verilogSource ../common/up_clock_mon.v verilogSource axi_laser_driver.v verilogSource CHECKSUM_8a5a13b8 xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_axi_pulse_gen_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset axi_laser_driver_regmap.v verilogSource ../common/up_clock_mon.v verilogSource axi_laser_driver.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_axi_pulse_gen_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/axi_laser_driver_v1_0.tcl tclSource CHECKSUM_5aee8db5 XGUI_VERSION_2 xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_axi_pulse_gen_1_0__ref_view_fileset ADI AXI Laser Driver ID Id 0 ASYNC_CLK_EN ASYNC_CLK_EN true PULSE_WIDTH Pulse width 7 PULSE_PERIOD Pulse period 10 Component_Name axi_laser_driver_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices ADI AXI Laser Driver level_2 package_project Analog Devices https://wiki.analog.com/resources/fpga/docs/axi_laser_driver 1 2024-01-14T03:48:03Z 2023.2.1