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`ifndef if_gt_tx_v1_0
`define if_gt_tx_v1_0

interface if_gt_tx_v1_0();
  logic tx_p;                                            // 
  logic tx_n;                                            // 
  logic tx_rst;                                          // 
  logic tx_rst_m;                                        // 
  logic tx_pll_rst;                                      // 
  logic tx_gt_rst;                                       // 
  logic tx_gt_rst_m;                                     // 
  logic tx_pll_locked;                                   // 
  logic tx_pll_locked_m;                                 // 
  logic tx_user_ready;                                   // 
  logic tx_user_ready_m;                                 // 
  logic tx_rst_done;                                     // 
  logic tx_rst_done_m;                                   // 
  logic tx_out_clk;                                      // 
  logic tx_clk;                                          // 
  logic tx_sysref;                                       // 
  logic tx_sync;                                         // 
  logic [31:0] tx_data;                                   // 
  logic tx_ip_rst;                                       // 
  logic [31:0] tx_ip_data;                                // 
  logic tx_ip_sysref;                                    // 
  logic tx_ip_sync;                                      // 
  logic tx_ip_rst_done;                                  // 

  modport MASTER (
    input tx_p, tx_n, tx_rst, tx_pll_rst, tx_gt_rst, tx_pll_locked, tx_user_ready, tx_rst_done, tx_out_clk, tx_ip_rst, tx_ip_data, tx_ip_sysref, tx_ip_sync, tx_ip_rst_done, 
    output tx_rst_m, tx_gt_rst_m, tx_pll_locked_m, tx_user_ready_m, tx_rst_done_m, tx_clk, tx_sysref, tx_sync, tx_data
    );

  modport SLAVE (
    input tx_rst_m, tx_gt_rst_m, tx_pll_locked_m, tx_user_ready_m, tx_rst_done_m, tx_clk, tx_sysref, tx_sync, tx_data, 
    output tx_p, tx_n, tx_rst, tx_pll_rst, tx_gt_rst, tx_pll_locked, tx_user_ready, tx_rst_done, tx_out_clk, tx_ip_rst, tx_ip_data, tx_ip_sysref, tx_ip_sync, tx_ip_rst_done
    );

  modport MONITOR (
    input tx_p, tx_n, tx_rst, tx_rst_m, tx_pll_rst, tx_gt_rst, tx_gt_rst_m, tx_pll_locked, tx_pll_locked_m, tx_user_ready, tx_user_ready_m, tx_rst_done, tx_rst_done_m, tx_out_clk, tx_clk, tx_sysref, tx_sync, tx_data, tx_ip_rst, tx_ip_data, tx_ip_sysref, tx_ip_sync, tx_ip_rst_done
    );

endinterface // if_gt_tx_v1_0

`endif