analog.com user jesd204_rx_static_config 1.0 rx_cfg lanes_disable cfg_lanes_disable links_disable cfg_links_disable octets_per_multiframe cfg_octets_per_multiframe octets_per_frame cfg_octets_per_frame disable_char_replacement cfg_disable_char_replacement disable_scrambler cfg_disable_scrambler frame_align_err_threshold cfg_frame_align_err_threshold device_octets_per_multiframe device_cfg_octets_per_multiframe device_octets_per_frame device_cfg_octets_per_frame device_beats_per_multiframe device_cfg_beats_per_multiframe device_lmfc_offset device_cfg_lmfc_offset device_sysref_oneshot device_cfg_sysref_oneshot device_sysref_disable device_cfg_sysref_disable device_buffer_early_release device_cfg_buffer_early_release device_buffer_delay device_cfg_buffer_delay rx_cfg_signal_clock rx_cfg_signal_clock CLK clk ASSOCIATED_BUSIF rx_cfg xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog jesd204_rx_static_config xilinx_anylanguagesynthesis_view_fileset viewChecksum 047d5aaf xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog jesd204_rx_static_config xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 047d5aaf xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum c55d0be5 clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_lanes_disable out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_links_disable out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_octets_per_multiframe out 9 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_octets_per_frame out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_disable_scrambler out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_disable_char_replacement out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_frame_align_err_threshold out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_octets_per_multiframe out 9 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_octets_per_frame out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_beats_per_multiframe out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_lmfc_offset out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_sysref_oneshot out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_sysref_disable out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_buffer_early_release out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_buffer_delay out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 OCTETS_PER_FRAME Octets Per Frame 1 FRAMES_PER_MULTIFRAME Frames Per Multiframe 32 SCR Scr 1 BUFFER_EARLY_RELEASE Buffer Early Release 0 LINK_MODE Link Mode 1 SYSREF_DISABLE Sysref Disable 0 SYSREF_ONE_SHOT Sysref One Shot 0 DATA_PATH_WIDTH Data Path Width 4 TPL_DATA_PATH_WIDTH Tpl Data Path Width 4 xilinx_anylanguagesynthesis_view_fileset jesd204_rx_static_config.v verilogSource CHECKSUM_047d5aaf xilinx_anylanguagebehavioralsimulation_view_fileset jesd204_rx_static_config.v verilogSource xilinx_xpgui_view_fileset xgui/jesd204_rx_static_config_v1_0.tcl tclSource CHECKSUM_c55d0be5 XGUI_VERSION_2 jesd204_rx_static_config_v1_0 NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 OCTETS_PER_FRAME Octets Per Frame 1 FRAMES_PER_MULTIFRAME Frames Per Multiframe 32 SCR Scr 1 BUFFER_EARLY_RELEASE Buffer Early Release 0 LINK_MODE Link Mode 1 SYSREF_DISABLE Sysref Disable 0 SYSREF_ONE_SHOT Sysref One Shot 0 DATA_PATH_WIDTH Data Path Width 4 TPL_DATA_PATH_WIDTH Tpl Data Path Width 4 Component_Name jesd204_rx_static_config_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices jesd204_rx_static_config_v1_0 level_2 package_project Analog Devices http://www.analog.com 1 2024-01-14T03:51:47Z 2023.2.1