analog.com user axi_xcvrlb 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW s_axi axi_lite 0 1024 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_xcvrlb xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum 05fbea40 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_xcvrlb xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 61f424a5 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum b1ece077 xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_blockdiagram_view_fileset ref_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 rx_p in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 rx_n in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 tx_p out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tx_n out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 CPLL_FBDIV Cpll Fbdiv 1 CPLL_FBDIV_4_5 Cpll Fbdiv 4 5 5 NUM_OF_LANES Num Of Lanes 1 XCVR_TYPE Xcvr Type 2 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_pairs_07421b06 0 1 2 3 4 5 6 7 8 9 10 xilinx_anylanguagesynthesis_view_fileset axi_xcvrlb_constr.xdc xdc ../../common/ad_pnmon.v verilogSource axi_xcvrlb_1.v verilogSource ../../common/up_axi.v verilogSource ../../common/up_xfer_status.v verilogSource ../util_adxcvr/util_adxcvr_xch.v verilogSource axi_xcvrlb.v verilogSource CHECKSUM_4e7e40b2 xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset ../../common/ad_pnmon.v verilogSource axi_xcvrlb_1.v verilogSource ../../common/up_axi.v verilogSource ../../common/up_xfer_status.v verilogSource ../util_adxcvr/util_adxcvr_xch.v verilogSource axi_xcvrlb.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/axi_xcvrlb_v1_0.tcl tclSource CHECKSUM_b1ece077 XGUI_VERSION_2 xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset axi_xcvrlb_v1_0 CPLL_FBDIV Cpll Fbdiv 1 CPLL_FBDIV_4_5 Cpll Fbdiv 4 5 5 NUM_OF_LANES Num Of Lanes 1 XCVR_TYPE Xcvr Type 2 Component_Name axi_xcvrlb_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices axi_xcvrlb_v1_0 level_2 package_project Analog Devices http://www.analog.com 1 2024-01-14T03:57:51Z 2023.2.1