analog.com user axi_jesd204_common 1.0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog jesd204_up_sysref xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum c4c41562 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog jesd204_up_sysref xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum dd8aa7f3 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum f92e9879 up_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_raddr in 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_rdata out 31 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_wreq in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_waddr in 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_cfg_is_writeable in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_cfg_sysref_oneshot out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_cfg_lmfc_offset out 7 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_cfg_sysref_disable out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_event_sysref_alignment_error in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_event_sysref_edge in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation xilinx_anylanguagesynthesis_view_fileset ../../xilinx/common/up_clock_mon_constr.xdc xdc ../../common/up_clock_mon.v verilogSource jesd204_up_common.v verilogSource jesd204_up_sysref.v verilogSource CHECKSUM_682078ff xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset ../../common/up_clock_mon.v verilogSource jesd204_up_common.v verilogSource jesd204_up_sysref.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/jesd204_up_sysref_v1_0.tcl tclSource CHECKSUM_f92e9879 XGUI_VERSION_2 xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset ADI AXI JESD204B Common Library Component_Name jesd204_up_sysref_v1_0 virtex7 /Analog_Devices ADI AXI JESD204B Common Library true level_2 package_project Analog Devices http://www.analog.com 1 2024-01-14T03:50:49Z 2023.2.1