analog.com user jesd204_tx_static_config 1.0 tx_cfg lanes_disable cfg_lanes_disable links_disable cfg_links_disable octets_per_multiframe cfg_octets_per_multiframe octets_per_frame cfg_octets_per_frame continuous_cgs cfg_continuous_cgs continuous_ilas cfg_continuous_ilas skip_ilas cfg_skip_ilas mframes_per_ilas cfg_mframes_per_ilas disable_char_replacement cfg_disable_char_replacement disable_scrambler cfg_disable_scrambler device_octets_per_multiframe device_cfg_octets_per_multiframe device_octets_per_frame device_cfg_octets_per_frame device_beats_per_multiframe device_cfg_beats_per_multiframe device_lmfc_offset device_cfg_lmfc_offset device_sysref_oneshot device_cfg_sysref_oneshot device_sysref_disable device_cfg_sysref_disable tx_ilas_config rd ilas_config_rd addr ilas_config_addr data ilas_config_data tx_cfg_tx_ilas_config_signal_clock tx_cfg_tx_ilas_config_signal_clock CLK clk ASSOCIATED_BUSIF tx_cfg:tx_ilas_config xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog jesd204_tx_static_config xilinx_anylanguagesynthesis_view_fileset viewChecksum f2d29d60 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog jesd204_tx_static_config xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum f2d29d60 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 5557730d clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_lanes_disable out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_links_disable out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_octets_per_multiframe out 9 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_octets_per_frame out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_continuous_cgs out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_continuous_ilas out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_skip_ilas out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_mframes_per_ilas out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_disable_char_replacement out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_disable_scrambler out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_octets_per_multiframe out 9 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_octets_per_frame out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_beats_per_multiframe out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_lmfc_offset out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_sysref_oneshot out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_sysref_disable out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ilas_config_rd in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ilas_config_addr in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ilas_config_data out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 OCTETS_PER_FRAME Octets Per Frame 1 FRAMES_PER_MULTIFRAME Frames Per Multiframe 32 NUM_CONVERTERS Num Converters 1 N N 16 NP Np 16 HIGH_DENSITY High Density 1 SCR Scr 1 LINK_MODE Link Mode 1 SYSREF_DISABLE Sysref Disable 0 SYSREF_ONE_SHOT Sysref One Shot 0 DATA_PATH_WIDTH Data Path Width 4 TPL_DATA_PATH_WIDTH Tpl Data Path Width 4 xilinx_anylanguagesynthesis_view_fileset jesd204_ilas_cfg_static.v verilogSource jesd204_tx_static_config.v verilogSource CHECKSUM_c8a1b22f xilinx_anylanguagebehavioralsimulation_view_fileset jesd204_ilas_cfg_static.v verilogSource jesd204_tx_static_config.v verilogSource xilinx_xpgui_view_fileset xgui/jesd204_tx_static_config_v1_0.tcl tclSource CHECKSUM_5557730d XGUI_VERSION_2 jesd204_tx_static_config_v1_0 NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 OCTETS_PER_FRAME Octets Per Frame 1 FRAMES_PER_MULTIFRAME Frames Per Multiframe 32 NUM_CONVERTERS Num Converters 1 N N 16 NP Np 16 HIGH_DENSITY High Density 1 SCR Scr 1 LINK_MODE Link Mode 1 SYSREF_DISABLE Sysref Disable 0 SYSREF_ONE_SHOT Sysref One Shot 0 DATA_PATH_WIDTH Data Path Width 4 TPL_DATA_PATH_WIDTH Tpl Data Path Width 4 Component_Name jesd204_tx_static_config_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices jesd204_tx_static_config_v1_0 level_2 package_project Analog Devices http://www.analog.com 1 2024-01-14T03:52:09Z 2023.2.1