analog.com user util_dacfifo 1.0 dma_clk CLK dma_clk ASSOCIATED_RESET dma_rst dma_rst RST dma_rst dac_clk CLK dac_clk ASSOCIATED_RESET dac_rst dac_rst RST dac_rst xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_dacfifo xilinx_anylanguagesynthesis_view_fileset viewChecksum 71800a14 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_dacfifo xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum fb2fd7ae xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 7dfe8a5d dma_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_rst in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_data in 127 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dma_ready out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_xfer_req in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_xfer_last in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_rst in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_data out 127 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_dunf out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_xfer_out out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation bypass in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ADDRESS_WIDTH Address Width 6 DATA_WIDTH Data Width 128 xilinx_anylanguagesynthesis_view_fileset util_dacfifo_ooc.ttcl ttcl util_dacfifo_constr.xdc xdc ../common/ad_b2g.v verilogSource ../common/ad_g2b.v verilogSource ../common/ad_mem.v verilogSource ../common/ad_mem_asym.v verilogSource util_dacfifo_bypass.v verilogSource util_dacfifo.v verilogSource CHECKSUM_3ff18447 xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_b2g.v verilogSource ../common/ad_g2b.v verilogSource ../common/ad_mem.v verilogSource ../common/ad_mem_asym.v verilogSource util_dacfifo_bypass.v verilogSource util_dacfifo.v verilogSource xilinx_xpgui_view_fileset xgui/util_dacfifo_v1_0.tcl tclSource CHECKSUM_7dfe8a5d XGUI_VERSION_2 util_dacfifo_v1_0 ADDRESS_WIDTH Address Width 6 DATA_WIDTH Data Width 128 Component_Name util_dacfifo_v1_0 virtex7 /Analog_Devices util_dacfifo_v1_0 level_2 package_project Analog Devices http://www.analog.com 1 2024-01-14T03:53:57Z 2023.2.1