analog.com user util_dec256sinc24b 1.0 clk CLK clk ASSOCIATED_RESET reset reset RST reset xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_dec256sinc24b xilinx_anylanguagesynthesis_view_fileset viewChecksum 82712b89 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_dec256sinc24b xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 82712b89 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f92e9879 clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_in in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_out out 15 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_en out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dec_rate in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation xilinx_anylanguagesynthesis_view_fileset ../common/util_dec256sinc24b.v verilogSource CHECKSUM_82712b89 xilinx_anylanguagebehavioralsimulation_view_fileset ../common/util_dec256sinc24b.v verilogSource xilinx_xpgui_view_fileset xgui/util_dec256sinc24b_v1_0.tcl tclSource CHECKSUM_f92e9879 XGUI_VERSION_2 util_dec256sinc24b_v1_0 Component_Name util_dec256sinc24b_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices util_dec256sinc24b_v1_0 level_2 package_project Analog Devices http://www.analog.com 1 2024-01-14T03:54:12Z 2023.2.1