analog.com user util_mfifo 1.0 din_clk CLK din_clk ASSOCIATED_RESET din_rst din_rst RST din_rst dout_clk CLK dout_clk ASSOCIATED_RESET dout_rst dout_rst RST dout_rst xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_mfifo xilinx_anylanguagesynthesis_view_fileset viewChecksum d636a054 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_mfifo xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum d636a054 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum c91cec2f din_rst in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation din_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation din_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 din_data_0 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 din_data_1 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true din_data_2 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true din_data_3 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true din_data_4 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_data_5 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_data_6 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_data_7 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dout_rst in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dout_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dout_valid out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dout_data_0 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dout_data_1 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true dout_data_2 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true dout_data_3 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true dout_data_4 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dout_data_5 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dout_data_6 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dout_data_7 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false NUM_OF_CHANNELS Num Of Channels 4 DIN_DATA_WIDTH Din Data Width 32 ADDRESS_WIDTH Address Width 8 xilinx_anylanguagesynthesis_view_fileset ../common/ad_mem.v verilogSource util_mfifo.v verilogSource CHECKSUM_86db3630 xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_mem.v verilogSource util_mfifo.v verilogSource xilinx_xpgui_view_fileset xgui/util_mfifo_v1_0.tcl tclSource CHECKSUM_c91cec2f XGUI_VERSION_2 util_mfifo_v1_0 NUM_OF_CHANNELS Num Of Channels 4 DIN_DATA_WIDTH Din Data Width 32 ADDRESS_WIDTH Address Width 8 Component_Name util_mfifo_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices util_mfifo_v1_0 level_2 package_project Analog Devices http://www.analog.com 1 2024-01-14T03:55:35Z 2023.2.1