analog.com user axi_ad4858 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_ad4858 xilinx_anylanguagesynthesis_view_fileset viewChecksum 7f2fbafb xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_ad4858 xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum ba51c525 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 16549e88 xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_view_fileset xilinx_utilityxitfiles Utility XIT/TTCL :vivado.xilinx.com:xit.util xilinx_utilityxitfiles_view_fileset delay_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 external_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true external_fast_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 cnvs in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 busy in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 lvds_cmos_n out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation scki out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false scko in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false lane_0 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false lane_1 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false lane_2 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false lane_3 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false lane_4 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false lane_5 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false lane_6 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false lane_7 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false scki_p out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true scki_n out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true scko_p in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true scko_n in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true sdo_p in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true sdo_n in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 adc_dovf in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 adc_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_enable_0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_enable_1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_enable_2 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_enable_3 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_enable_4 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_enable_5 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_enable_6 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_enable_7 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data_0 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data_1 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data_2 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data_3 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data_4 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data_5 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data_6 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data_7 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation FPGA_TECHNOLOGY Fpga Technology 0 DELAY_REFCLK_FREQ Delay Refclk Freq 200 IODELAY_ENABLE Iodelay Enable 1 ID Id 0 LVDS_CMOS_N Lvds Cmos N 1 LANE_0_ENABLE Lane 0 Enable true false LANE_1_ENABLE Lane 1 Enable true false LANE_2_ENABLE Lane 2 Enable true false LANE_3_ENABLE Lane 3 Enable true false LANE_4_ENABLE Lane 4 Enable true false LANE_5_ENABLE Lane 5 Enable true false LANE_6_ENABLE Lane 6 Enable true false LANE_7_ENABLE Lane 7 Enable true false ECHO_CLK_EN Echo Clk En 1 EXTERNAL_CLK External Clk 1 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_pairs_28f798a2 0 1 2 3 4 choice_pairs_4191e6fe 0 1 xilinx_anylanguagesynthesis_view_fileset ../xilinx/common/up_xfer_cntrl_constr.xdc xdc ../xilinx/common/ad_rst_constr.xdc xdc ../xilinx/common/up_xfer_status_constr.xdc xdc ../xilinx/common/up_clock_mon_constr.xdc xdc ../xilinx/common/ad_data_in.v verilogSource ../common/ad_datafmt.v verilogSource ../common/ad_rst.v verilogSource ../xilinx/common/ad_serdes_out.v verilogSource axi_ad4858_channel.v verilogSource axi_ad4858_cmos.v verilogSource axi_ad4858_crc.v verilogSource axi_ad4858_lvds.v verilogSource ../common/up_adc_channel.v verilogSource ../common/up_adc_common.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_delay_cntrl.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_ad4858.v verilogSource CHECKSUM_86ad6d10 xilinx_anylanguagebehavioralsimulation_view_fileset ../xilinx/common/ad_data_in.v verilogSource ../common/ad_datafmt.v verilogSource ../common/ad_rst.v verilogSource ../xilinx/common/ad_serdes_out.v verilogSource axi_ad4858_channel.v verilogSource axi_ad4858_cmos.v verilogSource axi_ad4858_crc.v verilogSource axi_ad4858_lvds.v verilogSource ../common/up_adc_channel.v verilogSource ../common/up_adc_common.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_delay_cntrl.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_ad4858.v verilogSource xilinx_xpgui_view_fileset xgui/axi_ad4858_v1_0.tcl tclSource CHECKSUM_5a71ad18 XGUI_VERSION_2 xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource xilinx_utilityxitfiles_view_fileset gui/axi_ad4858_v1_0.gtcl GTCL axi_ad4858_v1_0 FPGA_TECHNOLOGY Fpga Technology 0 DELAY_REFCLK_FREQ Delay Refclk Freq 200 IODELAY_ENABLE Iodelay Enable 1 ID Id 0 LVDS_CMOS_N Interface type 1 LANE_0_ENABLE LANE_0_ENABLE true false LANE_1_ENABLE LANE_1_ENABLE true false LANE_2_ENABLE LANE_2_ENABLE true false LANE_3_ENABLE LANE_3_ENABLE true false LANE_4_ENABLE LANE_4_ENABLE true false LANE_5_ENABLE LANE_5_ENABLE true false LANE_6_ENABLE LANE_6_ENABLE true false LANE_7_ENABLE LANE_7_ENABLE true false ECHO_CLK_EN Echoed clock enabled 1 EXTERNAL_CLK EXTERNAL_CLK_EN 1 Component_Name axi_ad4858_v1_0 virtex7 /Analog_Devices axi_ad4858_v1_0 level_2 package_project Analog Devices https://wiki.analog.com/resources/fpga/docs/axi_ad4858 1 2024-06-06T02:53:40Z 2024.1