analog.com user axi_jesd204_rx 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW rx_cfg lanes_disable core_cfg_lanes_disable links_disable core_cfg_links_disable octets_per_multiframe core_cfg_octets_per_multiframe octets_per_frame core_cfg_octets_per_frame disable_char_replacement core_cfg_disable_char_replacement disable_scrambler core_cfg_disable_scrambler frame_align_err_threshold core_cfg_frame_align_err_threshold device_octets_per_multiframe device_cfg_octets_per_multiframe device_octets_per_frame device_cfg_octets_per_frame device_beats_per_multiframe device_cfg_beats_per_multiframe device_lmfc_offset device_cfg_lmfc_offset device_sysref_oneshot device_cfg_sysref_oneshot device_sysref_disable device_cfg_sysref_disable device_buffer_early_release device_cfg_buffer_early_release device_buffer_delay device_cfg_buffer_delay err_statistics_reset core_ctrl_err_statistics_reset err_statistics_mask core_ctrl_err_statistics_mask rx_ilas_config valid core_ilas_config_valid addr core_ilas_config_addr data core_ilas_config_data true rx_event sysref_alignment_error device_event_sysref_alignment_error sysref_edge device_event_sysref_edge frame_alignment_error core_event_frame_alignment_error unexpected_lane_state_error core_event_unexpected_lane_state_error rx_status ctrl_state core_status_ctrl_state lane_cgs_state core_status_lane_cgs_state lane_emb_state core_status_lane_emb_state lane_ifs_ready core_status_lane_ifs_ready lane_latency core_status_lane_latency lane_frame_align_err_cnt core_status_lane_frame_align_err_cnt err_statistics_cnt core_status_err_statistics_cnt synth_params0 status_synth_params0 synth_params1 status_synth_params1 synth_params2 status_synth_params2 irq INTERRUPT irq SENSITIVITY LEVEL_HIGH rx_status_rx_event_rx_ilas_config_rx_cfg_signal_clock rx_status_rx_event_rx_ilas_config_rx_cfg_signal_clock CLK core_clk ASSOCIATED_BUSIF rx_status:rx_event:rx_ilas_config:rx_cfg ASSOCIATED_RESET core_reset rx_status_rx_event_rx_ilas_config_rx_cfg_signal_reset rx_status_rx_event_rx_ilas_config_rx_cfg_signal_reset RST core_reset POLARITY ACTIVE_HIGH s_axi axi_lite 0 16384 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_jesd204_rx xilinx_anylanguagesynthesis_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum 34b2f2aa xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_jesd204_rx xilinx_anylanguagebehavioralsimulation_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 77c08331 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum 3df09e24 s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 13 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 13 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation irq out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_reset_ext in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 core_reset out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_reset out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_lanes_disable out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_links_disable out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_octets_per_multiframe out 9 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_octets_per_frame out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_disable_scrambler out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_disable_char_replacement out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_frame_align_err_threshold out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_octets_per_multiframe out 9 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_octets_per_frame out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_beats_per_multiframe out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_lmfc_offset out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_sysref_oneshot out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_sysref_disable out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_buffer_early_release out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_buffer_delay out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_ilas_config_valid in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_ilas_config_addr in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_ilas_config_data in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 device_event_sysref_alignment_error in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_event_sysref_edge in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_event_frame_alignment_error in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_event_unexpected_lane_state_error in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_ctrl_err_statistics_mask out 6 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_ctrl_err_statistics_reset out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_status_err_statistics_cnt in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_status_ctrl_state in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_status_lane_cgs_state in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_status_lane_emb_state in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_status_lane_ifs_ready in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_status_lane_latency in 13 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_status_lane_frame_align_err_cnt in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_synth_params0 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_synth_params1 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_synth_params2 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ID Id 0 NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 LINK_MODE Link Mode 1 ENABLE_LINK_STATS Enable Link Stats 0 DATA_PATH_WIDTH Data Path Width 4 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_list_9ca20931 LEVEL_HIGH LEVEL_LOW EDGE_RISING EDGE_FALLING choice_pairs_1942b210 2 1 xilinx_anylanguagesynthesis_view_fileset axi_jesd204_rx_ooc.ttcl ttcl axi_jesd204_rx_constr.xdc xdc processing_order late ../../common/up_axi.v verilogSource jesd204_up_rx.v verilogSource jesd204_up_rx_lane.v verilogSource jesd204_up_ilas_mem.v verilogSource axi_jesd204_rx.v verilogSource CHECKSUM_d579961a xilinx_anylanguagesynthesis_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset ../../common/up_axi.v verilogSource jesd204_up_rx.v verilogSource jesd204_up_rx_lane.v verilogSource jesd204_up_ilas_mem.v verilogSource axi_jesd204_rx.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/axi_jesd204_rx_v1_0.tcl tclSource CHECKSUM_397049c5 XGUI_VERSION_2 xilinx_xpgui_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset ADI JESD204C Receive AXI Interface ID Id 0 NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 LINK_MODE Link Layer mode 1 ENABLE_LINK_STATS Enable Link Stats 0 DATA_PATH_WIDTH Data Path Width 4 Component_Name axi_jesd204_rx_v1_0 virtex7 /Analog_Devices ADI JESD204C Receive AXI Interface level_2 package_project Analog Devices https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_rx 1 2024-06-06T03:08:35Z 2024.1