analog.com user util_pad 1.0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_pad xilinx_anylanguagesynthesis_view_fileset viewChecksum 1b1c31dd xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_pad xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 1b1c31dd xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 4f92a007 data_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_out out 31 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation NUM_OF_SAMPLES Num Of Samples 2 IN_BITS_PER_SAMPLE In Bits Per Sample 16 OUT_BITS_PER_SAMPLE Out Bits Per Sample 16 PADDING_TO_MSB_LSB_N Padding To Msb Lsb N 0 SIGN_EXTEND Sign Extend 1 xilinx_anylanguagesynthesis_view_fileset util_pad.v verilogSource CHECKSUM_1b1c31dd xilinx_anylanguagebehavioralsimulation_view_fileset util_pad.v verilogSource xilinx_xpgui_view_fileset xgui/util_pad_v1_0.tcl tclSource CHECKSUM_4f92a007 XGUI_VERSION_2 util_pad_v1_0 NUM_OF_SAMPLES Num Of Samples 2 IN_BITS_PER_SAMPLE In Bits Per Sample 16 OUT_BITS_PER_SAMPLE Out Bits Per Sample 16 PADDING_TO_MSB_LSB_N Padding To Msb Lsb N 0 SIGN_EXTEND Sign Extend 1 Component_Name util_pad_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices util_pad_v1_0 level_2 package_project Analog Devices http://www.analog.com 1 2024-06-06T03:13:49Z 2024.1