analog.com user util_var_fifo 1.0 clk CLK clk ASSOCIATED_RESET rst rst RST rst xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_var_fifo xilinx_anylanguagesynthesis_view_fileset viewChecksum c02044a9 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_var_fifo xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum c02044a9 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 9fdedb52 clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rst in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation depth in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_in_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_out_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation wea_w out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation en_w out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation addr_w out 12 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation din_w out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation en_r out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation addr_r out 12 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dout_r in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation DATA_WIDTH Data Width 32 ADDRESS_WIDTH Address Width 13 xilinx_anylanguagesynthesis_view_fileset util_var_fifo.v verilogSource CHECKSUM_c02044a9 xilinx_anylanguagebehavioralsimulation_view_fileset util_var_fifo.v verilogSource xilinx_xpgui_view_fileset xgui/util_var_fifo_v1_0.tcl tclSource CHECKSUM_9fdedb52 XGUI_VERSION_2 util_var_fifo_v1_0 DATA_WIDTH Data Width 32 ADDRESS_WIDTH Address Width 13 Component_Name util_var_fifo_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices util_var_fifo_v1_0 level_2 package_project Analog Devices https://wiki.analog.com/resources/fpga/docs/util_var_fifo 1 2024-06-06T03:14:31Z 2024.1