analog.com user util_adxcvr 1.0 up_clk CLK up_clk ASSOCIATED_RESET up_rstn cpll_ref_clk_0 CLK cpll_ref_clk_0 ASSOCIATED_RESET up_rx_rst_0:up_tx_rst_0 rx_out_clk_0 CLK rx_out_clk_0 tx_out_clk_0 CLK tx_out_clk_0 rx_clk_0 CLK rx_clk_0 tx_clk_0 CLK tx_clk_0 qpll_ref_clk_0 CLK qpll_ref_clk_0 cpll_ref_clk_1 CLK cpll_ref_clk_1 ASSOCIATED_RESET up_rx_rst_1:up_tx_rst_1 rx_out_clk_1 CLK rx_out_clk_1 tx_out_clk_1 CLK tx_out_clk_1 rx_clk_1 CLK rx_clk_1 tx_clk_1 CLK tx_clk_1 cpll_ref_clk_2 CLK cpll_ref_clk_2 ASSOCIATED_RESET up_rx_rst_2:up_tx_rst_2 rx_out_clk_2 CLK rx_out_clk_2 tx_out_clk_2 CLK tx_out_clk_2 rx_clk_2 CLK rx_clk_2 tx_clk_2 CLK tx_clk_2 cpll_ref_clk_3 CLK cpll_ref_clk_3 ASSOCIATED_RESET up_rx_rst_3:up_tx_rst_3 rx_out_clk_3 CLK rx_out_clk_3 tx_out_clk_3 CLK tx_out_clk_3 rx_clk_3 CLK rx_clk_3 tx_clk_3 CLK tx_clk_3 cpll_ref_clk_4 CLK cpll_ref_clk_4 ASSOCIATED_RESET up_rx_rst_4:up_tx_rst_4 rx_out_clk_4 CLK rx_out_clk_4 tx_out_clk_4 CLK tx_out_clk_4 rx_clk_4 CLK rx_clk_4 tx_clk_4 CLK tx_clk_4 qpll_ref_clk_4 CLK qpll_ref_clk_4 cpll_ref_clk_5 CLK cpll_ref_clk_5 ASSOCIATED_RESET up_rx_rst_5:up_tx_rst_5 rx_out_clk_5 CLK rx_out_clk_5 tx_out_clk_5 CLK tx_out_clk_5 rx_clk_5 CLK rx_clk_5 tx_clk_5 CLK tx_clk_5 cpll_ref_clk_6 CLK cpll_ref_clk_6 ASSOCIATED_RESET up_rx_rst_6:up_tx_rst_6 rx_out_clk_6 CLK rx_out_clk_6 tx_out_clk_6 CLK tx_out_clk_6 rx_clk_6 CLK rx_clk_6 tx_clk_6 CLK tx_clk_6 cpll_ref_clk_7 CLK cpll_ref_clk_7 ASSOCIATED_RESET up_rx_rst_7:up_tx_rst_7 rx_out_clk_7 CLK rx_out_clk_7 tx_out_clk_7 CLK tx_out_clk_7 rx_clk_7 CLK rx_clk_7 tx_clk_7 CLK tx_clk_7 cpll_ref_clk_8 CLK cpll_ref_clk_8 ASSOCIATED_RESET up_rx_rst_8:up_tx_rst_8 rx_out_clk_8 CLK rx_out_clk_8 tx_out_clk_8 CLK tx_out_clk_8 rx_clk_8 CLK rx_clk_8 tx_clk_8 CLK tx_clk_8 qpll_ref_clk_8 CLK qpll_ref_clk_8 cpll_ref_clk_9 CLK cpll_ref_clk_9 ASSOCIATED_RESET up_rx_rst_9:up_tx_rst_9 rx_out_clk_9 CLK rx_out_clk_9 tx_out_clk_9 CLK tx_out_clk_9 rx_clk_9 CLK rx_clk_9 tx_clk_9 CLK tx_clk_9 cpll_ref_clk_10 CLK cpll_ref_clk_10 ASSOCIATED_RESET up_rx_rst_10:up_tx_rst_10 rx_out_clk_10 CLK rx_out_clk_10 tx_out_clk_10 CLK tx_out_clk_10 rx_clk_10 CLK rx_clk_10 tx_clk_10 CLK tx_clk_10 cpll_ref_clk_11 CLK cpll_ref_clk_11 ASSOCIATED_RESET up_rx_rst_11:up_tx_rst_11 rx_out_clk_11 CLK rx_out_clk_11 tx_out_clk_11 CLK tx_out_clk_11 rx_clk_11 CLK rx_clk_11 tx_clk_11 CLK tx_clk_11 cpll_ref_clk_12 CLK cpll_ref_clk_12 ASSOCIATED_RESET up_rx_rst_12:up_tx_rst_12 rx_out_clk_12 CLK rx_out_clk_12 tx_out_clk_12 CLK tx_out_clk_12 rx_clk_12 CLK rx_clk_12 tx_clk_12 CLK tx_clk_12 qpll_ref_clk_12 CLK qpll_ref_clk_12 cpll_ref_clk_13 CLK cpll_ref_clk_13 ASSOCIATED_RESET up_rx_rst_13:up_tx_rst_13 rx_out_clk_13 CLK rx_out_clk_13 tx_out_clk_13 CLK tx_out_clk_13 rx_clk_13 CLK rx_clk_13 tx_clk_13 CLK tx_clk_13 cpll_ref_clk_14 CLK cpll_ref_clk_14 ASSOCIATED_RESET up_rx_rst_14:up_tx_rst_14 rx_out_clk_14 CLK rx_out_clk_14 tx_out_clk_14 CLK tx_out_clk_14 rx_clk_14 CLK rx_clk_14 tx_clk_14 CLK tx_clk_14 cpll_ref_clk_15 CLK cpll_ref_clk_15 ASSOCIATED_RESET up_rx_rst_15:up_tx_rst_15 rx_out_clk_15 CLK rx_out_clk_15 tx_out_clk_15 CLK tx_out_clk_15 rx_clk_15 CLK rx_clk_15 tx_clk_15 CLK tx_clk_15 cpll_ref_clk_16 CLK cpll_ref_clk_16 ASSOCIATED_RESET up_rx_rst_16:up_tx_rst_16 rx_out_clk_16 CLK rx_out_clk_16 tx_out_clk_16 CLK tx_out_clk_16 rx_clk_16 CLK rx_clk_16 tx_clk_16 CLK tx_clk_16 qpll_ref_clk_16 CLK qpll_ref_clk_16 cpll_ref_clk_17 CLK cpll_ref_clk_17 ASSOCIATED_RESET up_rx_rst_17:up_tx_rst_17 rx_out_clk_17 CLK rx_out_clk_17 tx_out_clk_17 CLK tx_out_clk_17 rx_clk_17 CLK rx_clk_17 tx_clk_17 CLK tx_clk_17 cpll_ref_clk_18 CLK cpll_ref_clk_18 ASSOCIATED_RESET up_rx_rst_18:up_tx_rst_18 rx_out_clk_18 CLK rx_out_clk_18 tx_out_clk_18 CLK tx_out_clk_18 rx_clk_18 CLK rx_clk_18 tx_clk_18 CLK tx_clk_18 cpll_ref_clk_19 CLK cpll_ref_clk_19 ASSOCIATED_RESET up_rx_rst_19:up_tx_rst_19 rx_out_clk_19 CLK rx_out_clk_19 tx_out_clk_19 CLK tx_out_clk_19 rx_clk_19 CLK rx_clk_19 tx_clk_19 CLK tx_clk_19 cpll_ref_clk_20 CLK cpll_ref_clk_20 ASSOCIATED_RESET up_rx_rst_20:up_tx_rst_20 rx_out_clk_20 CLK rx_out_clk_20 tx_out_clk_20 CLK tx_out_clk_20 rx_clk_20 CLK rx_clk_20 tx_clk_20 CLK tx_clk_20 qpll_ref_clk_20 CLK qpll_ref_clk_20 cpll_ref_clk_21 CLK cpll_ref_clk_21 ASSOCIATED_RESET up_rx_rst_21:up_tx_rst_21 rx_out_clk_21 CLK rx_out_clk_21 tx_out_clk_21 CLK tx_out_clk_21 rx_clk_21 CLK rx_clk_21 tx_clk_21 CLK tx_clk_21 cpll_ref_clk_22 CLK cpll_ref_clk_22 ASSOCIATED_RESET up_rx_rst_22:up_tx_rst_22 rx_out_clk_22 CLK rx_out_clk_22 tx_out_clk_22 CLK tx_out_clk_22 rx_clk_22 CLK rx_clk_22 tx_clk_22 CLK tx_clk_22 cpll_ref_clk_23 CLK cpll_ref_clk_23 ASSOCIATED_RESET up_rx_rst_23:up_tx_rst_23 rx_out_clk_23 CLK rx_out_clk_23 tx_out_clk_23 CLK tx_out_clk_23 rx_clk_23 CLK rx_clk_23 tx_clk_23 CLK tx_clk_23 cpll_ref_clk_24 CLK cpll_ref_clk_24 ASSOCIATED_RESET up_rx_rst_24:up_tx_rst_24 rx_out_clk_24 CLK rx_out_clk_24 tx_out_clk_24 CLK tx_out_clk_24 rx_clk_24 CLK rx_clk_24 tx_clk_24 CLK tx_clk_24 qpll_ref_clk_24 CLK qpll_ref_clk_24 cpll_ref_clk_25 CLK cpll_ref_clk_25 ASSOCIATED_RESET up_rx_rst_25:up_tx_rst_25 rx_out_clk_25 CLK rx_out_clk_25 tx_out_clk_25 CLK tx_out_clk_25 rx_clk_25 CLK rx_clk_25 tx_clk_25 CLK tx_clk_25 cpll_ref_clk_26 CLK cpll_ref_clk_26 ASSOCIATED_RESET up_rx_rst_26:up_tx_rst_26 rx_out_clk_26 CLK rx_out_clk_26 tx_out_clk_26 CLK tx_out_clk_26 rx_clk_26 CLK rx_clk_26 tx_clk_26 CLK tx_clk_26 cpll_ref_clk_27 CLK cpll_ref_clk_27 ASSOCIATED_RESET up_rx_rst_27:up_tx_rst_27 rx_out_clk_27 CLK rx_out_clk_27 tx_out_clk_27 CLK tx_out_clk_27 rx_clk_27 CLK rx_clk_27 tx_clk_27 CLK tx_clk_27 cpll_ref_clk_28 CLK cpll_ref_clk_28 ASSOCIATED_RESET up_rx_rst_28:up_tx_rst_28 rx_out_clk_28 CLK rx_out_clk_28 tx_out_clk_28 CLK tx_out_clk_28 rx_clk_28 CLK rx_clk_28 tx_clk_28 CLK tx_clk_28 qpll_ref_clk_28 CLK qpll_ref_clk_28 cpll_ref_clk_29 CLK cpll_ref_clk_29 ASSOCIATED_RESET up_rx_rst_29:up_tx_rst_29 rx_out_clk_29 CLK rx_out_clk_29 tx_out_clk_29 CLK tx_out_clk_29 rx_clk_29 CLK rx_clk_29 tx_clk_29 CLK tx_clk_29 cpll_ref_clk_30 CLK cpll_ref_clk_30 ASSOCIATED_RESET up_rx_rst_30:up_tx_rst_30 rx_out_clk_30 CLK rx_out_clk_30 tx_out_clk_30 CLK tx_out_clk_30 rx_clk_30 CLK rx_clk_30 tx_clk_30 CLK tx_clk_30 cpll_ref_clk_31 CLK cpll_ref_clk_31 ASSOCIATED_RESET up_rx_rst_31:up_tx_rst_31 rx_out_clk_31 CLK rx_out_clk_31 tx_out_clk_31 CLK tx_out_clk_31 rx_clk_31 CLK rx_clk_31 tx_clk_31 CLK tx_clk_31 rx_clk_2x_0 CLK rx_clk_2x_0 tx_clk_2x_0 CLK tx_clk_2x_0 rx_out_clk_div2_0 CLK rx_out_clk_div2_0 tx_out_clk_div2_0 CLK tx_out_clk_div2_0 rx_clk_2x_1 CLK rx_clk_2x_1 tx_clk_2x_1 CLK tx_clk_2x_1 rx_out_clk_div2_1 CLK rx_out_clk_div2_1 tx_out_clk_div2_1 CLK tx_out_clk_div2_1 rx_clk_2x_2 CLK rx_clk_2x_2 tx_clk_2x_2 CLK tx_clk_2x_2 rx_out_clk_div2_2 CLK rx_out_clk_div2_2 tx_out_clk_div2_2 CLK tx_out_clk_div2_2 rx_clk_2x_3 CLK rx_clk_2x_3 tx_clk_2x_3 CLK tx_clk_2x_3 rx_out_clk_div2_3 CLK rx_out_clk_div2_3 tx_out_clk_div2_3 CLK tx_out_clk_div2_3 rx_clk_2x_4 CLK rx_clk_2x_4 tx_clk_2x_4 CLK tx_clk_2x_4 rx_out_clk_div2_4 CLK rx_out_clk_div2_4 tx_out_clk_div2_4 CLK tx_out_clk_div2_4 rx_clk_2x_5 CLK rx_clk_2x_5 tx_clk_2x_5 CLK tx_clk_2x_5 rx_out_clk_div2_5 CLK rx_out_clk_div2_5 tx_out_clk_div2_5 CLK tx_out_clk_div2_5 rx_clk_2x_6 CLK rx_clk_2x_6 tx_clk_2x_6 CLK tx_clk_2x_6 rx_out_clk_div2_6 CLK rx_out_clk_div2_6 tx_out_clk_div2_6 CLK tx_out_clk_div2_6 rx_clk_2x_7 CLK rx_clk_2x_7 tx_clk_2x_7 CLK tx_clk_2x_7 rx_out_clk_div2_7 CLK rx_out_clk_div2_7 tx_out_clk_div2_7 CLK tx_out_clk_div2_7 rx_clk_2x_8 CLK rx_clk_2x_8 tx_clk_2x_8 CLK tx_clk_2x_8 rx_out_clk_div2_8 CLK rx_out_clk_div2_8 tx_out_clk_div2_8 CLK tx_out_clk_div2_8 rx_clk_2x_9 CLK rx_clk_2x_9 tx_clk_2x_9 CLK tx_clk_2x_9 rx_out_clk_div2_9 CLK rx_out_clk_div2_9 tx_out_clk_div2_9 CLK tx_out_clk_div2_9 rx_clk_2x_10 CLK rx_clk_2x_10 tx_clk_2x_10 CLK tx_clk_2x_10 rx_out_clk_div2_10 CLK rx_out_clk_div2_10 tx_out_clk_div2_10 CLK tx_out_clk_div2_10 rx_clk_2x_11 CLK rx_clk_2x_11 tx_clk_2x_11 CLK tx_clk_2x_11 rx_out_clk_div2_11 CLK rx_out_clk_div2_11 tx_out_clk_div2_11 CLK tx_out_clk_div2_11 rx_clk_2x_12 CLK rx_clk_2x_12 tx_clk_2x_12 CLK tx_clk_2x_12 rx_out_clk_div2_12 CLK rx_out_clk_div2_12 tx_out_clk_div2_12 CLK tx_out_clk_div2_12 rx_clk_2x_13 CLK rx_clk_2x_13 tx_clk_2x_13 CLK tx_clk_2x_13 rx_out_clk_div2_13 CLK rx_out_clk_div2_13 tx_out_clk_div2_13 CLK tx_out_clk_div2_13 rx_clk_2x_14 CLK rx_clk_2x_14 tx_clk_2x_14 CLK tx_clk_2x_14 rx_out_clk_div2_14 CLK rx_out_clk_div2_14 tx_out_clk_div2_14 CLK tx_out_clk_div2_14 rx_clk_2x_15 CLK rx_clk_2x_15 tx_clk_2x_15 CLK tx_clk_2x_15 rx_out_clk_div2_15 CLK rx_out_clk_div2_15 tx_out_clk_div2_15 CLK tx_out_clk_div2_15 rx_clk_2x_16 CLK rx_clk_2x_16 tx_clk_2x_16 CLK tx_clk_2x_16 rx_out_clk_div2_16 CLK rx_out_clk_div2_16 tx_out_clk_div2_16 CLK tx_out_clk_div2_16 rx_clk_2x_17 CLK rx_clk_2x_17 tx_clk_2x_17 CLK tx_clk_2x_17 rx_out_clk_div2_17 CLK rx_out_clk_div2_17 tx_out_clk_div2_17 CLK tx_out_clk_div2_17 rx_clk_2x_18 CLK rx_clk_2x_18 tx_clk_2x_18 CLK tx_clk_2x_18 rx_out_clk_div2_18 CLK rx_out_clk_div2_18 tx_out_clk_div2_18 CLK tx_out_clk_div2_18 rx_clk_2x_19 CLK rx_clk_2x_19 tx_clk_2x_19 CLK tx_clk_2x_19 rx_out_clk_div2_19 CLK rx_out_clk_div2_19 tx_out_clk_div2_19 CLK tx_out_clk_div2_19 rx_clk_2x_20 CLK rx_clk_2x_20 tx_clk_2x_20 CLK tx_clk_2x_20 rx_out_clk_div2_20 CLK rx_out_clk_div2_20 tx_out_clk_div2_20 CLK tx_out_clk_div2_20 rx_clk_2x_21 CLK rx_clk_2x_21 tx_clk_2x_21 CLK tx_clk_2x_21 rx_out_clk_div2_21 CLK rx_out_clk_div2_21 tx_out_clk_div2_21 CLK tx_out_clk_div2_21 rx_clk_2x_22 CLK rx_clk_2x_22 tx_clk_2x_22 CLK tx_clk_2x_22 rx_out_clk_div2_22 CLK rx_out_clk_div2_22 tx_out_clk_div2_22 CLK tx_out_clk_div2_22 rx_clk_2x_23 CLK rx_clk_2x_23 tx_clk_2x_23 CLK tx_clk_2x_23 rx_out_clk_div2_23 CLK rx_out_clk_div2_23 tx_out_clk_div2_23 CLK tx_out_clk_div2_23 rx_clk_2x_24 CLK rx_clk_2x_24 tx_clk_2x_24 CLK tx_clk_2x_24 rx_out_clk_div2_24 CLK rx_out_clk_div2_24 tx_out_clk_div2_24 CLK tx_out_clk_div2_24 rx_clk_2x_25 CLK rx_clk_2x_25 tx_clk_2x_25 CLK tx_clk_2x_25 rx_out_clk_div2_25 CLK rx_out_clk_div2_25 tx_out_clk_div2_25 CLK tx_out_clk_div2_25 rx_clk_2x_26 CLK rx_clk_2x_26 tx_clk_2x_26 CLK tx_clk_2x_26 rx_out_clk_div2_26 CLK rx_out_clk_div2_26 tx_out_clk_div2_26 CLK tx_out_clk_div2_26 rx_clk_2x_27 CLK rx_clk_2x_27 tx_clk_2x_27 CLK tx_clk_2x_27 rx_out_clk_div2_27 CLK rx_out_clk_div2_27 tx_out_clk_div2_27 CLK tx_out_clk_div2_27 rx_clk_2x_28 CLK rx_clk_2x_28 tx_clk_2x_28 CLK tx_clk_2x_28 rx_out_clk_div2_28 CLK rx_out_clk_div2_28 tx_out_clk_div2_28 CLK tx_out_clk_div2_28 rx_clk_2x_29 CLK rx_clk_2x_29 tx_clk_2x_29 CLK tx_clk_2x_29 rx_out_clk_div2_29 CLK rx_out_clk_div2_29 tx_out_clk_div2_29 CLK tx_out_clk_div2_29 rx_clk_2x_30 CLK rx_clk_2x_30 tx_clk_2x_30 CLK tx_clk_2x_30 rx_out_clk_div2_30 CLK rx_out_clk_div2_30 tx_out_clk_div2_30 CLK tx_out_clk_div2_30 rx_clk_2x_31 CLK rx_clk_2x_31 tx_clk_2x_31 CLK tx_clk_2x_31 rx_out_clk_div2_31 CLK rx_out_clk_div2_31 tx_out_clk_div2_31 CLK tx_out_clk_div2_31 up_rstn RST up_rstn POLARITY ACTIVE_LOW up_rx_rst_0 RST up_rx_rst_0 up_tx_rst_0 RST up_tx_rst_0 up_cpll_rst_0 RST up_cpll_rst_0 up_qpll_rst_0 RST up_qpll_rst_0 up_rx_rst_1 RST up_rx_rst_1 up_tx_rst_1 RST up_tx_rst_1 up_cpll_rst_1 RST up_cpll_rst_1 up_rx_rst_2 RST up_rx_rst_2 up_tx_rst_2 RST up_tx_rst_2 up_cpll_rst_2 RST up_cpll_rst_2 up_rx_rst_3 RST up_rx_rst_3 up_tx_rst_3 RST up_tx_rst_3 up_cpll_rst_3 RST up_cpll_rst_3 up_rx_rst_4 RST up_rx_rst_4 up_tx_rst_4 RST up_tx_rst_4 up_cpll_rst_4 RST up_cpll_rst_4 up_qpll_rst_4 RST up_qpll_rst_4 up_rx_rst_5 RST up_rx_rst_5 up_tx_rst_5 RST up_tx_rst_5 up_cpll_rst_5 RST up_cpll_rst_5 up_rx_rst_6 RST up_rx_rst_6 up_tx_rst_6 RST up_tx_rst_6 up_cpll_rst_6 RST up_cpll_rst_6 up_rx_rst_7 RST up_rx_rst_7 up_tx_rst_7 RST up_tx_rst_7 up_cpll_rst_7 RST up_cpll_rst_7 up_rx_rst_8 RST up_rx_rst_8 up_tx_rst_8 RST up_tx_rst_8 up_cpll_rst_8 RST up_cpll_rst_8 up_qpll_rst_8 RST up_qpll_rst_8 up_rx_rst_9 RST up_rx_rst_9 up_tx_rst_9 RST up_tx_rst_9 up_cpll_rst_9 RST up_cpll_rst_9 up_rx_rst_10 RST up_rx_rst_10 up_tx_rst_10 RST up_tx_rst_10 up_cpll_rst_10 RST up_cpll_rst_10 up_rx_rst_11 RST up_rx_rst_11 up_tx_rst_11 RST up_tx_rst_11 up_cpll_rst_11 RST up_cpll_rst_11 up_rx_rst_12 RST up_rx_rst_12 up_tx_rst_12 RST up_tx_rst_12 up_cpll_rst_12 RST up_cpll_rst_12 up_qpll_rst_12 RST up_qpll_rst_12 up_rx_rst_13 RST up_rx_rst_13 up_tx_rst_13 RST up_tx_rst_13 up_cpll_rst_13 RST up_cpll_rst_13 up_rx_rst_14 RST up_rx_rst_14 up_tx_rst_14 RST up_tx_rst_14 up_cpll_rst_14 RST up_cpll_rst_14 up_rx_rst_15 RST up_rx_rst_15 up_tx_rst_15 RST up_tx_rst_15 up_cpll_rst_15 RST up_cpll_rst_15 up_rx_rst_16 RST up_rx_rst_16 up_tx_rst_16 RST up_tx_rst_16 up_cpll_rst_16 RST up_cpll_rst_16 up_qpll_rst_16 RST up_qpll_rst_16 up_rx_rst_17 RST up_rx_rst_17 up_tx_rst_17 RST up_tx_rst_17 up_cpll_rst_17 RST up_cpll_rst_17 up_rx_rst_18 RST up_rx_rst_18 up_tx_rst_18 RST up_tx_rst_18 up_cpll_rst_18 RST up_cpll_rst_18 up_rx_rst_19 RST up_rx_rst_19 up_tx_rst_19 RST up_tx_rst_19 up_cpll_rst_19 RST up_cpll_rst_19 up_rx_rst_20 RST up_rx_rst_20 up_tx_rst_20 RST up_tx_rst_20 up_cpll_rst_20 RST up_cpll_rst_20 up_qpll_rst_20 RST up_qpll_rst_20 up_rx_rst_21 RST up_rx_rst_21 up_tx_rst_21 RST up_tx_rst_21 up_cpll_rst_21 RST up_cpll_rst_21 up_rx_rst_22 RST up_rx_rst_22 up_tx_rst_22 RST up_tx_rst_22 up_cpll_rst_22 RST up_cpll_rst_22 up_rx_rst_23 RST up_rx_rst_23 up_tx_rst_23 RST up_tx_rst_23 up_cpll_rst_23 RST up_cpll_rst_23 up_rx_rst_24 RST up_rx_rst_24 up_tx_rst_24 RST up_tx_rst_24 up_cpll_rst_24 RST up_cpll_rst_24 up_qpll_rst_24 RST up_qpll_rst_24 up_rx_rst_25 RST up_rx_rst_25 up_tx_rst_25 RST up_tx_rst_25 up_cpll_rst_25 RST up_cpll_rst_25 up_rx_rst_26 RST up_rx_rst_26 up_tx_rst_26 RST up_tx_rst_26 up_cpll_rst_26 RST up_cpll_rst_26 up_rx_rst_27 RST up_rx_rst_27 up_tx_rst_27 RST up_tx_rst_27 up_cpll_rst_27 RST up_cpll_rst_27 up_rx_rst_28 RST up_rx_rst_28 up_tx_rst_28 RST up_tx_rst_28 up_cpll_rst_28 RST up_cpll_rst_28 up_qpll_rst_28 RST up_qpll_rst_28 up_rx_rst_29 RST up_rx_rst_29 up_tx_rst_29 RST up_tx_rst_29 up_cpll_rst_29 RST up_cpll_rst_29 up_rx_rst_30 RST up_rx_rst_30 up_tx_rst_30 RST up_tx_rst_30 up_cpll_rst_30 RST up_cpll_rst_30 up_rx_rst_31 RST up_rx_rst_31 up_tx_rst_31 RST up_tx_rst_31 up_cpll_rst_31 RST up_cpll_rst_31 up_cm_0 enb up_cm_enb_0 addr up_cm_addr_0 wr up_cm_wr_0 wdata up_cm_wdata_0 rdata up_cm_rdata_0 ready up_cm_ready_0 true up_es_0 enb up_es_enb_0 addr up_es_addr_0 wr up_es_wr_0 wdata up_es_wdata_0 rdata up_es_rdata_0 reset up_es_reset_0 ready up_es_ready_0 true up_rx_0 pll_locked up_rx_pll_locked_0 rst up_rx_rst_0 user_ready up_rx_user_ready_0 rst_done up_rx_rst_done_0 prbssel up_rx_prbssel_0 prbscntreset up_rx_prbscntreset_0 prbserr up_rx_prbserr_0 prbslocked up_rx_prbslocked_0 bufstatus up_rx_bufstatus_0 bufstatus_rst up_rx_bufstatus_rst_0 lpm_dfe_n up_rx_lpm_dfe_n_0 rate up_rx_rate_0 sys_clk_sel up_rx_sys_clk_sel_0 out_clk_sel up_rx_out_clk_sel_0 enb up_rx_enb_0 addr up_rx_addr_0 wr up_rx_wr_0 wdata up_rx_wdata_0 rdata up_rx_rdata_0 ready up_rx_ready_0 true up_tx_0 pll_locked up_tx_pll_locked_0 rst up_tx_rst_0 user_ready up_tx_user_ready_0 rst_done up_tx_rst_done_0 prbsforceerr up_tx_prbsforceerr_0 prbssel up_tx_prbssel_0 bufstatus up_tx_bufstatus_0 lpm_dfe_n up_tx_lpm_dfe_n_0 rate up_tx_rate_0 sys_clk_sel up_tx_sys_clk_sel_0 out_clk_sel up_tx_out_clk_sel_0 tx_diffctrl up_tx_diffctrl_0 tx_postcursor up_tx_postcursor_0 tx_precursor up_tx_precursor_0 enb up_tx_enb_0 addr up_tx_addr_0 wr up_tx_wr_0 wdata up_tx_wdata_0 rdata up_tx_rdata_0 ready up_tx_ready_0 true rx_0 rxcharisk rx_charisk_0 rxnotintable rx_notintable_0 rxdisperr rx_disperr_0 rxdata rx_data_0 rxheader rx_header_0 rxblock_sync rx_block_sync_0 true tx_0 txcharisk tx_charisk_0 txdata tx_data_0 txheader tx_header_0 true up_es_1 enb up_es_enb_1 addr up_es_addr_1 wr up_es_wr_1 wdata up_es_wdata_1 rdata up_es_rdata_1 reset up_es_reset_1 ready up_es_ready_1 true up_rx_1 pll_locked up_rx_pll_locked_1 rst up_rx_rst_1 user_ready up_rx_user_ready_1 rst_done up_rx_rst_done_1 prbssel up_rx_prbssel_1 prbscntreset up_rx_prbscntreset_1 prbserr up_rx_prbserr_1 prbslocked up_rx_prbslocked_1 bufstatus up_rx_bufstatus_1 bufstatus_rst up_rx_bufstatus_rst_1 lpm_dfe_n up_rx_lpm_dfe_n_1 rate up_rx_rate_1 sys_clk_sel up_rx_sys_clk_sel_1 out_clk_sel up_rx_out_clk_sel_1 enb up_rx_enb_1 addr up_rx_addr_1 wr up_rx_wr_1 wdata up_rx_wdata_1 rdata up_rx_rdata_1 ready up_rx_ready_1 true up_tx_1 pll_locked up_tx_pll_locked_1 rst up_tx_rst_1 user_ready up_tx_user_ready_1 rst_done up_tx_rst_done_1 prbsforceerr up_tx_prbsforceerr_1 prbssel up_tx_prbssel_1 bufstatus up_tx_bufstatus_1 lpm_dfe_n up_tx_lpm_dfe_n_1 rate up_tx_rate_1 sys_clk_sel up_tx_sys_clk_sel_1 out_clk_sel up_tx_out_clk_sel_1 tx_diffctrl up_tx_diffctrl_1 tx_postcursor up_tx_postcursor_1 tx_precursor up_tx_precursor_1 enb up_tx_enb_1 addr up_tx_addr_1 wr up_tx_wr_1 wdata up_tx_wdata_1 rdata up_tx_rdata_1 ready up_tx_ready_1 true rx_1 rxcharisk rx_charisk_1 rxnotintable rx_notintable_1 rxdisperr rx_disperr_1 rxdata rx_data_1 rxheader rx_header_1 rxblock_sync rx_block_sync_1 true tx_1 txcharisk tx_charisk_1 txdata tx_data_1 txheader tx_header_1 true up_es_2 enb up_es_enb_2 addr up_es_addr_2 wr up_es_wr_2 wdata up_es_wdata_2 rdata up_es_rdata_2 reset up_es_reset_2 ready up_es_ready_2 true up_rx_2 pll_locked up_rx_pll_locked_2 rst up_rx_rst_2 user_ready up_rx_user_ready_2 rst_done up_rx_rst_done_2 prbssel up_rx_prbssel_2 prbscntreset up_rx_prbscntreset_2 prbserr up_rx_prbserr_2 prbslocked up_rx_prbslocked_2 bufstatus up_rx_bufstatus_2 bufstatus_rst up_rx_bufstatus_rst_2 lpm_dfe_n up_rx_lpm_dfe_n_2 rate up_rx_rate_2 sys_clk_sel up_rx_sys_clk_sel_2 out_clk_sel up_rx_out_clk_sel_2 enb up_rx_enb_2 addr up_rx_addr_2 wr up_rx_wr_2 wdata up_rx_wdata_2 rdata up_rx_rdata_2 ready up_rx_ready_2 true up_tx_2 pll_locked up_tx_pll_locked_2 rst up_tx_rst_2 user_ready up_tx_user_ready_2 rst_done up_tx_rst_done_2 prbsforceerr up_tx_prbsforceerr_2 prbssel up_tx_prbssel_2 bufstatus up_tx_bufstatus_2 lpm_dfe_n up_tx_lpm_dfe_n_2 rate up_tx_rate_2 sys_clk_sel up_tx_sys_clk_sel_2 out_clk_sel up_tx_out_clk_sel_2 tx_diffctrl up_tx_diffctrl_2 tx_postcursor up_tx_postcursor_2 tx_precursor up_tx_precursor_2 enb up_tx_enb_2 addr up_tx_addr_2 wr up_tx_wr_2 wdata up_tx_wdata_2 rdata up_tx_rdata_2 ready up_tx_ready_2 true rx_2 rxcharisk rx_charisk_2 rxnotintable rx_notintable_2 rxdisperr rx_disperr_2 rxdata rx_data_2 rxheader rx_header_2 rxblock_sync rx_block_sync_2 true tx_2 txcharisk tx_charisk_2 txdata tx_data_2 txheader tx_header_2 true up_es_3 enb up_es_enb_3 addr up_es_addr_3 wr up_es_wr_3 wdata up_es_wdata_3 rdata up_es_rdata_3 reset up_es_reset_3 ready up_es_ready_3 true up_rx_3 pll_locked up_rx_pll_locked_3 rst up_rx_rst_3 user_ready up_rx_user_ready_3 rst_done up_rx_rst_done_3 prbssel up_rx_prbssel_3 prbscntreset up_rx_prbscntreset_3 prbserr up_rx_prbserr_3 prbslocked up_rx_prbslocked_3 bufstatus up_rx_bufstatus_3 bufstatus_rst up_rx_bufstatus_rst_3 lpm_dfe_n up_rx_lpm_dfe_n_3 rate up_rx_rate_3 sys_clk_sel up_rx_sys_clk_sel_3 out_clk_sel up_rx_out_clk_sel_3 enb up_rx_enb_3 addr up_rx_addr_3 wr up_rx_wr_3 wdata up_rx_wdata_3 rdata up_rx_rdata_3 ready up_rx_ready_3 true up_tx_3 pll_locked up_tx_pll_locked_3 rst up_tx_rst_3 user_ready up_tx_user_ready_3 rst_done up_tx_rst_done_3 prbsforceerr up_tx_prbsforceerr_3 prbssel up_tx_prbssel_3 bufstatus up_tx_bufstatus_3 lpm_dfe_n up_tx_lpm_dfe_n_3 rate up_tx_rate_3 sys_clk_sel up_tx_sys_clk_sel_3 out_clk_sel up_tx_out_clk_sel_3 tx_diffctrl up_tx_diffctrl_3 tx_postcursor up_tx_postcursor_3 tx_precursor up_tx_precursor_3 enb up_tx_enb_3 addr up_tx_addr_3 wr up_tx_wr_3 wdata up_tx_wdata_3 rdata up_tx_rdata_3 ready up_tx_ready_3 true rx_3 rxcharisk rx_charisk_3 rxnotintable rx_notintable_3 rxdisperr rx_disperr_3 rxdata rx_data_3 rxheader rx_header_3 rxblock_sync rx_block_sync_3 true tx_3 txcharisk tx_charisk_3 txdata tx_data_3 txheader tx_header_3 true up_cm_4 enb up_cm_enb_4 addr up_cm_addr_4 wr up_cm_wr_4 wdata up_cm_wdata_4 rdata up_cm_rdata_4 ready up_cm_ready_4 true up_es_4 enb up_es_enb_4 addr up_es_addr_4 wr up_es_wr_4 wdata up_es_wdata_4 rdata up_es_rdata_4 reset up_es_reset_4 ready up_es_ready_4 true up_rx_4 pll_locked up_rx_pll_locked_4 rst up_rx_rst_4 user_ready up_rx_user_ready_4 rst_done up_rx_rst_done_4 prbssel up_rx_prbssel_4 prbscntreset up_rx_prbscntreset_4 prbserr up_rx_prbserr_4 prbslocked up_rx_prbslocked_4 bufstatus up_rx_bufstatus_4 bufstatus_rst up_rx_bufstatus_rst_4 lpm_dfe_n up_rx_lpm_dfe_n_4 rate up_rx_rate_4 sys_clk_sel up_rx_sys_clk_sel_4 out_clk_sel up_rx_out_clk_sel_4 enb up_rx_enb_4 addr up_rx_addr_4 wr up_rx_wr_4 wdata up_rx_wdata_4 rdata up_rx_rdata_4 ready up_rx_ready_4 true up_tx_4 pll_locked up_tx_pll_locked_4 rst up_tx_rst_4 user_ready up_tx_user_ready_4 rst_done up_tx_rst_done_4 prbsforceerr up_tx_prbsforceerr_4 prbssel up_tx_prbssel_4 bufstatus up_tx_bufstatus_4 lpm_dfe_n up_tx_lpm_dfe_n_4 rate up_tx_rate_4 sys_clk_sel up_tx_sys_clk_sel_4 out_clk_sel up_tx_out_clk_sel_4 tx_diffctrl up_tx_diffctrl_4 tx_postcursor up_tx_postcursor_4 tx_precursor up_tx_precursor_4 enb up_tx_enb_4 addr up_tx_addr_4 wr up_tx_wr_4 wdata up_tx_wdata_4 rdata up_tx_rdata_4 ready up_tx_ready_4 true rx_4 rxcharisk rx_charisk_4 rxnotintable rx_notintable_4 rxdisperr rx_disperr_4 rxdata rx_data_4 rxheader rx_header_4 rxblock_sync rx_block_sync_4 true tx_4 txcharisk tx_charisk_4 txdata tx_data_4 txheader tx_header_4 true up_es_5 enb up_es_enb_5 addr up_es_addr_5 wr up_es_wr_5 wdata up_es_wdata_5 rdata up_es_rdata_5 reset up_es_reset_5 ready up_es_ready_5 true up_rx_5 pll_locked up_rx_pll_locked_5 rst up_rx_rst_5 user_ready up_rx_user_ready_5 rst_done up_rx_rst_done_5 prbssel up_rx_prbssel_5 prbscntreset up_rx_prbscntreset_5 prbserr up_rx_prbserr_5 prbslocked up_rx_prbslocked_5 bufstatus up_rx_bufstatus_5 bufstatus_rst up_rx_bufstatus_rst_5 lpm_dfe_n up_rx_lpm_dfe_n_5 rate up_rx_rate_5 sys_clk_sel up_rx_sys_clk_sel_5 out_clk_sel up_rx_out_clk_sel_5 enb up_rx_enb_5 addr up_rx_addr_5 wr up_rx_wr_5 wdata up_rx_wdata_5 rdata up_rx_rdata_5 ready up_rx_ready_5 true up_tx_5 pll_locked up_tx_pll_locked_5 rst up_tx_rst_5 user_ready up_tx_user_ready_5 rst_done up_tx_rst_done_5 prbsforceerr up_tx_prbsforceerr_5 prbssel up_tx_prbssel_5 bufstatus up_tx_bufstatus_5 lpm_dfe_n up_tx_lpm_dfe_n_5 rate up_tx_rate_5 sys_clk_sel up_tx_sys_clk_sel_5 out_clk_sel up_tx_out_clk_sel_5 tx_diffctrl up_tx_diffctrl_5 tx_postcursor up_tx_postcursor_5 tx_precursor up_tx_precursor_5 enb up_tx_enb_5 addr up_tx_addr_5 wr up_tx_wr_5 wdata up_tx_wdata_5 rdata up_tx_rdata_5 ready up_tx_ready_5 true rx_5 rxcharisk rx_charisk_5 rxnotintable rx_notintable_5 rxdisperr rx_disperr_5 rxdata rx_data_5 rxheader rx_header_5 rxblock_sync rx_block_sync_5 true tx_5 txcharisk tx_charisk_5 txdata tx_data_5 txheader tx_header_5 true up_es_6 enb up_es_enb_6 addr up_es_addr_6 wr up_es_wr_6 wdata up_es_wdata_6 rdata up_es_rdata_6 reset up_es_reset_6 ready up_es_ready_6 true up_rx_6 pll_locked up_rx_pll_locked_6 rst up_rx_rst_6 user_ready up_rx_user_ready_6 rst_done up_rx_rst_done_6 prbssel up_rx_prbssel_6 prbscntreset up_rx_prbscntreset_6 prbserr up_rx_prbserr_6 prbslocked up_rx_prbslocked_6 bufstatus up_rx_bufstatus_6 bufstatus_rst up_rx_bufstatus_rst_6 lpm_dfe_n up_rx_lpm_dfe_n_6 rate up_rx_rate_6 sys_clk_sel up_rx_sys_clk_sel_6 out_clk_sel up_rx_out_clk_sel_6 enb up_rx_enb_6 addr up_rx_addr_6 wr up_rx_wr_6 wdata up_rx_wdata_6 rdata up_rx_rdata_6 ready up_rx_ready_6 true up_tx_6 pll_locked up_tx_pll_locked_6 rst up_tx_rst_6 user_ready up_tx_user_ready_6 rst_done up_tx_rst_done_6 prbsforceerr up_tx_prbsforceerr_6 prbssel up_tx_prbssel_6 bufstatus up_tx_bufstatus_6 lpm_dfe_n up_tx_lpm_dfe_n_6 rate up_tx_rate_6 sys_clk_sel up_tx_sys_clk_sel_6 out_clk_sel up_tx_out_clk_sel_6 tx_diffctrl up_tx_diffctrl_6 tx_postcursor up_tx_postcursor_6 tx_precursor up_tx_precursor_6 enb up_tx_enb_6 addr up_tx_addr_6 wr up_tx_wr_6 wdata up_tx_wdata_6 rdata up_tx_rdata_6 ready up_tx_ready_6 true rx_6 rxcharisk rx_charisk_6 rxnotintable rx_notintable_6 rxdisperr rx_disperr_6 rxdata rx_data_6 rxheader rx_header_6 rxblock_sync rx_block_sync_6 true tx_6 txcharisk tx_charisk_6 txdata tx_data_6 txheader tx_header_6 true up_es_7 enb up_es_enb_7 addr up_es_addr_7 wr up_es_wr_7 wdata up_es_wdata_7 rdata up_es_rdata_7 reset up_es_reset_7 ready up_es_ready_7 true up_rx_7 pll_locked up_rx_pll_locked_7 rst up_rx_rst_7 user_ready up_rx_user_ready_7 rst_done up_rx_rst_done_7 prbssel up_rx_prbssel_7 prbscntreset up_rx_prbscntreset_7 prbserr up_rx_prbserr_7 prbslocked up_rx_prbslocked_7 bufstatus up_rx_bufstatus_7 bufstatus_rst up_rx_bufstatus_rst_7 lpm_dfe_n up_rx_lpm_dfe_n_7 rate up_rx_rate_7 sys_clk_sel up_rx_sys_clk_sel_7 out_clk_sel up_rx_out_clk_sel_7 enb up_rx_enb_7 addr up_rx_addr_7 wr up_rx_wr_7 wdata up_rx_wdata_7 rdata up_rx_rdata_7 ready up_rx_ready_7 true up_tx_7 pll_locked up_tx_pll_locked_7 rst up_tx_rst_7 user_ready up_tx_user_ready_7 rst_done up_tx_rst_done_7 prbsforceerr up_tx_prbsforceerr_7 prbssel up_tx_prbssel_7 bufstatus up_tx_bufstatus_7 lpm_dfe_n up_tx_lpm_dfe_n_7 rate up_tx_rate_7 sys_clk_sel up_tx_sys_clk_sel_7 out_clk_sel up_tx_out_clk_sel_7 tx_diffctrl up_tx_diffctrl_7 tx_postcursor up_tx_postcursor_7 tx_precursor up_tx_precursor_7 enb up_tx_enb_7 addr up_tx_addr_7 wr up_tx_wr_7 wdata up_tx_wdata_7 rdata up_tx_rdata_7 ready up_tx_ready_7 true rx_7 rxcharisk rx_charisk_7 rxnotintable rx_notintable_7 rxdisperr rx_disperr_7 rxdata rx_data_7 rxheader rx_header_7 rxblock_sync rx_block_sync_7 true tx_7 txcharisk tx_charisk_7 txdata tx_data_7 txheader tx_header_7 true up_cm_8 enb up_cm_enb_8 addr up_cm_addr_8 wr up_cm_wr_8 wdata up_cm_wdata_8 rdata up_cm_rdata_8 ready up_cm_ready_8 false up_es_8 enb up_es_enb_8 addr up_es_addr_8 wr up_es_wr_8 wdata up_es_wdata_8 rdata up_es_rdata_8 reset up_es_reset_8 ready up_es_ready_8 false up_rx_8 pll_locked up_rx_pll_locked_8 rst up_rx_rst_8 user_ready up_rx_user_ready_8 rst_done up_rx_rst_done_8 prbssel up_rx_prbssel_8 prbscntreset up_rx_prbscntreset_8 prbserr up_rx_prbserr_8 prbslocked up_rx_prbslocked_8 bufstatus up_rx_bufstatus_8 bufstatus_rst up_rx_bufstatus_rst_8 lpm_dfe_n up_rx_lpm_dfe_n_8 rate up_rx_rate_8 sys_clk_sel up_rx_sys_clk_sel_8 out_clk_sel up_rx_out_clk_sel_8 enb up_rx_enb_8 addr up_rx_addr_8 wr up_rx_wr_8 wdata up_rx_wdata_8 rdata up_rx_rdata_8 ready up_rx_ready_8 false up_tx_8 pll_locked up_tx_pll_locked_8 rst up_tx_rst_8 user_ready up_tx_user_ready_8 rst_done up_tx_rst_done_8 prbsforceerr up_tx_prbsforceerr_8 prbssel up_tx_prbssel_8 bufstatus up_tx_bufstatus_8 lpm_dfe_n up_tx_lpm_dfe_n_8 rate up_tx_rate_8 sys_clk_sel up_tx_sys_clk_sel_8 out_clk_sel up_tx_out_clk_sel_8 tx_diffctrl up_tx_diffctrl_8 tx_postcursor up_tx_postcursor_8 tx_precursor up_tx_precursor_8 enb up_tx_enb_8 addr up_tx_addr_8 wr up_tx_wr_8 wdata up_tx_wdata_8 rdata up_tx_rdata_8 ready up_tx_ready_8 false rx_8 rxcharisk rx_charisk_8 rxnotintable rx_notintable_8 rxdisperr rx_disperr_8 rxdata rx_data_8 rxheader rx_header_8 rxblock_sync rx_block_sync_8 false tx_8 txcharisk tx_charisk_8 txdata tx_data_8 txheader tx_header_8 false up_es_9 enb up_es_enb_9 addr up_es_addr_9 wr up_es_wr_9 wdata up_es_wdata_9 rdata up_es_rdata_9 reset up_es_reset_9 ready up_es_ready_9 false up_rx_9 pll_locked up_rx_pll_locked_9 rst up_rx_rst_9 user_ready up_rx_user_ready_9 rst_done up_rx_rst_done_9 prbssel up_rx_prbssel_9 prbscntreset up_rx_prbscntreset_9 prbserr up_rx_prbserr_9 prbslocked up_rx_prbslocked_9 bufstatus up_rx_bufstatus_9 bufstatus_rst up_rx_bufstatus_rst_9 lpm_dfe_n up_rx_lpm_dfe_n_9 rate up_rx_rate_9 sys_clk_sel up_rx_sys_clk_sel_9 out_clk_sel up_rx_out_clk_sel_9 enb up_rx_enb_9 addr up_rx_addr_9 wr up_rx_wr_9 wdata up_rx_wdata_9 rdata up_rx_rdata_9 ready up_rx_ready_9 false up_tx_9 pll_locked up_tx_pll_locked_9 rst up_tx_rst_9 user_ready up_tx_user_ready_9 rst_done up_tx_rst_done_9 prbsforceerr up_tx_prbsforceerr_9 prbssel up_tx_prbssel_9 bufstatus up_tx_bufstatus_9 lpm_dfe_n up_tx_lpm_dfe_n_9 rate up_tx_rate_9 sys_clk_sel up_tx_sys_clk_sel_9 out_clk_sel up_tx_out_clk_sel_9 tx_diffctrl up_tx_diffctrl_9 tx_postcursor up_tx_postcursor_9 tx_precursor up_tx_precursor_9 enb up_tx_enb_9 addr up_tx_addr_9 wr up_tx_wr_9 wdata up_tx_wdata_9 rdata up_tx_rdata_9 ready up_tx_ready_9 false rx_9 rxcharisk rx_charisk_9 rxnotintable rx_notintable_9 rxdisperr rx_disperr_9 rxdata rx_data_9 rxheader rx_header_9 rxblock_sync rx_block_sync_9 false tx_9 txcharisk tx_charisk_9 txdata tx_data_9 txheader tx_header_9 false up_es_10 enb up_es_enb_10 addr up_es_addr_10 wr up_es_wr_10 wdata up_es_wdata_10 rdata up_es_rdata_10 reset up_es_reset_10 ready up_es_ready_10 false up_rx_10 pll_locked up_rx_pll_locked_10 rst up_rx_rst_10 user_ready up_rx_user_ready_10 rst_done up_rx_rst_done_10 prbssel up_rx_prbssel_10 prbscntreset up_rx_prbscntreset_10 prbserr up_rx_prbserr_10 prbslocked up_rx_prbslocked_10 bufstatus up_rx_bufstatus_10 bufstatus_rst up_rx_bufstatus_rst_10 lpm_dfe_n up_rx_lpm_dfe_n_10 rate up_rx_rate_10 sys_clk_sel up_rx_sys_clk_sel_10 out_clk_sel up_rx_out_clk_sel_10 enb up_rx_enb_10 addr up_rx_addr_10 wr up_rx_wr_10 wdata up_rx_wdata_10 rdata up_rx_rdata_10 ready up_rx_ready_10 false up_tx_10 pll_locked up_tx_pll_locked_10 rst up_tx_rst_10 user_ready up_tx_user_ready_10 rst_done up_tx_rst_done_10 prbsforceerr up_tx_prbsforceerr_10 prbssel up_tx_prbssel_10 bufstatus up_tx_bufstatus_10 lpm_dfe_n up_tx_lpm_dfe_n_10 rate up_tx_rate_10 sys_clk_sel up_tx_sys_clk_sel_10 out_clk_sel up_tx_out_clk_sel_10 tx_diffctrl up_tx_diffctrl_10 tx_postcursor up_tx_postcursor_10 tx_precursor up_tx_precursor_10 enb up_tx_enb_10 addr up_tx_addr_10 wr up_tx_wr_10 wdata up_tx_wdata_10 rdata up_tx_rdata_10 ready up_tx_ready_10 false rx_10 rxcharisk rx_charisk_10 rxnotintable rx_notintable_10 rxdisperr rx_disperr_10 rxdata rx_data_10 rxheader rx_header_10 rxblock_sync rx_block_sync_10 false tx_10 txcharisk tx_charisk_10 txdata tx_data_10 txheader tx_header_10 false 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sys_clk_sel up_rx_sys_clk_sel_14 out_clk_sel up_rx_out_clk_sel_14 enb up_rx_enb_14 addr up_rx_addr_14 wr up_rx_wr_14 wdata up_rx_wdata_14 rdata up_rx_rdata_14 ready up_rx_ready_14 false up_tx_14 pll_locked up_tx_pll_locked_14 rst up_tx_rst_14 user_ready up_tx_user_ready_14 rst_done up_tx_rst_done_14 prbsforceerr up_tx_prbsforceerr_14 prbssel up_tx_prbssel_14 bufstatus up_tx_bufstatus_14 lpm_dfe_n up_tx_lpm_dfe_n_14 rate up_tx_rate_14 sys_clk_sel up_tx_sys_clk_sel_14 out_clk_sel up_tx_out_clk_sel_14 tx_diffctrl up_tx_diffctrl_14 tx_postcursor up_tx_postcursor_14 tx_precursor up_tx_precursor_14 enb up_tx_enb_14 addr up_tx_addr_14 wr up_tx_wr_14 wdata up_tx_wdata_14 rdata up_tx_rdata_14 ready up_tx_ready_14 false rx_14 rxcharisk rx_charisk_14 rxnotintable rx_notintable_14 rxdisperr rx_disperr_14 rxdata rx_data_14 rxheader rx_header_14 rxblock_sync rx_block_sync_14 false tx_14 txcharisk tx_charisk_14 txdata tx_data_14 txheader tx_header_14 false up_es_15 enb up_es_enb_15 addr up_es_addr_15 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up_es_ready_23 false up_rx_23 pll_locked up_rx_pll_locked_23 rst up_rx_rst_23 user_ready up_rx_user_ready_23 rst_done up_rx_rst_done_23 prbssel up_rx_prbssel_23 prbscntreset up_rx_prbscntreset_23 prbserr up_rx_prbserr_23 prbslocked up_rx_prbslocked_23 bufstatus up_rx_bufstatus_23 bufstatus_rst up_rx_bufstatus_rst_23 lpm_dfe_n up_rx_lpm_dfe_n_23 rate up_rx_rate_23 sys_clk_sel up_rx_sys_clk_sel_23 out_clk_sel up_rx_out_clk_sel_23 enb up_rx_enb_23 addr up_rx_addr_23 wr up_rx_wr_23 wdata up_rx_wdata_23 rdata up_rx_rdata_23 ready up_rx_ready_23 false up_tx_23 pll_locked up_tx_pll_locked_23 rst up_tx_rst_23 user_ready up_tx_user_ready_23 rst_done up_tx_rst_done_23 prbsforceerr up_tx_prbsforceerr_23 prbssel up_tx_prbssel_23 bufstatus up_tx_bufstatus_23 lpm_dfe_n up_tx_lpm_dfe_n_23 rate up_tx_rate_23 sys_clk_sel up_tx_sys_clk_sel_23 out_clk_sel up_tx_out_clk_sel_23 tx_diffctrl up_tx_diffctrl_23 tx_postcursor up_tx_postcursor_23 tx_precursor up_tx_precursor_23 enb up_tx_enb_23 addr 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out_clk_sel up_rx_out_clk_sel_24 enb up_rx_enb_24 addr up_rx_addr_24 wr up_rx_wr_24 wdata up_rx_wdata_24 rdata up_rx_rdata_24 ready up_rx_ready_24 false up_tx_24 pll_locked up_tx_pll_locked_24 rst up_tx_rst_24 user_ready up_tx_user_ready_24 rst_done up_tx_rst_done_24 prbsforceerr up_tx_prbsforceerr_24 prbssel up_tx_prbssel_24 bufstatus up_tx_bufstatus_24 lpm_dfe_n up_tx_lpm_dfe_n_24 rate up_tx_rate_24 sys_clk_sel up_tx_sys_clk_sel_24 out_clk_sel up_tx_out_clk_sel_24 tx_diffctrl up_tx_diffctrl_24 tx_postcursor up_tx_postcursor_24 tx_precursor up_tx_precursor_24 enb up_tx_enb_24 addr up_tx_addr_24 wr up_tx_wr_24 wdata up_tx_wdata_24 rdata up_tx_rdata_24 ready up_tx_ready_24 false rx_24 rxcharisk rx_charisk_24 rxnotintable rx_notintable_24 rxdisperr rx_disperr_24 rxdata rx_data_24 rxheader rx_header_24 rxblock_sync rx_block_sync_24 false tx_24 txcharisk tx_charisk_24 txdata tx_data_24 txheader tx_header_24 false up_es_25 enb up_es_enb_25 addr up_es_addr_25 wr up_es_wr_25 wdata up_es_wdata_25 rdata up_es_rdata_25 reset up_es_reset_25 ready up_es_ready_25 false up_rx_25 pll_locked up_rx_pll_locked_25 rst up_rx_rst_25 user_ready up_rx_user_ready_25 rst_done up_rx_rst_done_25 prbssel up_rx_prbssel_25 prbscntreset up_rx_prbscntreset_25 prbserr up_rx_prbserr_25 prbslocked up_rx_prbslocked_25 bufstatus up_rx_bufstatus_25 bufstatus_rst up_rx_bufstatus_rst_25 lpm_dfe_n up_rx_lpm_dfe_n_25 rate up_rx_rate_25 sys_clk_sel up_rx_sys_clk_sel_25 out_clk_sel up_rx_out_clk_sel_25 enb up_rx_enb_25 addr up_rx_addr_25 wr up_rx_wr_25 wdata up_rx_wdata_25 rdata up_rx_rdata_25 ready up_rx_ready_25 false up_tx_25 pll_locked up_tx_pll_locked_25 rst up_tx_rst_25 user_ready up_tx_user_ready_25 rst_done up_tx_rst_done_25 prbsforceerr up_tx_prbsforceerr_25 prbssel up_tx_prbssel_25 bufstatus up_tx_bufstatus_25 lpm_dfe_n up_tx_lpm_dfe_n_25 rate up_tx_rate_25 sys_clk_sel up_tx_sys_clk_sel_25 out_clk_sel up_tx_out_clk_sel_25 tx_diffctrl up_tx_diffctrl_25 tx_postcursor up_tx_postcursor_25 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wdata up_rx_wdata_26 rdata up_rx_rdata_26 ready up_rx_ready_26 false up_tx_26 pll_locked up_tx_pll_locked_26 rst up_tx_rst_26 user_ready up_tx_user_ready_26 rst_done up_tx_rst_done_26 prbsforceerr up_tx_prbsforceerr_26 prbssel up_tx_prbssel_26 bufstatus up_tx_bufstatus_26 lpm_dfe_n up_tx_lpm_dfe_n_26 rate up_tx_rate_26 sys_clk_sel up_tx_sys_clk_sel_26 out_clk_sel up_tx_out_clk_sel_26 tx_diffctrl up_tx_diffctrl_26 tx_postcursor up_tx_postcursor_26 tx_precursor up_tx_precursor_26 enb up_tx_enb_26 addr up_tx_addr_26 wr up_tx_wr_26 wdata up_tx_wdata_26 rdata up_tx_rdata_26 ready up_tx_ready_26 false rx_26 rxcharisk rx_charisk_26 rxnotintable rx_notintable_26 rxdisperr rx_disperr_26 rxdata rx_data_26 rxheader rx_header_26 rxblock_sync rx_block_sync_26 false tx_26 txcharisk tx_charisk_26 txdata tx_data_26 txheader tx_header_26 false up_es_27 enb up_es_enb_27 addr up_es_addr_27 wr up_es_wr_27 wdata up_es_wdata_27 rdata up_es_rdata_27 reset up_es_reset_27 ready up_es_ready_27 false up_rx_27 pll_locked up_rx_pll_locked_27 rst up_rx_rst_27 user_ready up_rx_user_ready_27 rst_done up_rx_rst_done_27 prbssel up_rx_prbssel_27 prbscntreset up_rx_prbscntreset_27 prbserr up_rx_prbserr_27 prbslocked up_rx_prbslocked_27 bufstatus up_rx_bufstatus_27 bufstatus_rst up_rx_bufstatus_rst_27 lpm_dfe_n up_rx_lpm_dfe_n_27 rate up_rx_rate_27 sys_clk_sel up_rx_sys_clk_sel_27 out_clk_sel up_rx_out_clk_sel_27 enb up_rx_enb_27 addr up_rx_addr_27 wr up_rx_wr_27 wdata up_rx_wdata_27 rdata up_rx_rdata_27 ready up_rx_ready_27 false up_tx_27 pll_locked up_tx_pll_locked_27 rst up_tx_rst_27 user_ready up_tx_user_ready_27 rst_done up_tx_rst_done_27 prbsforceerr up_tx_prbsforceerr_27 prbssel up_tx_prbssel_27 bufstatus up_tx_bufstatus_27 lpm_dfe_n up_tx_lpm_dfe_n_27 rate up_tx_rate_27 sys_clk_sel up_tx_sys_clk_sel_27 out_clk_sel up_tx_out_clk_sel_27 tx_diffctrl up_tx_diffctrl_27 tx_postcursor up_tx_postcursor_27 tx_precursor up_tx_precursor_27 enb up_tx_enb_27 addr up_tx_addr_27 wr up_tx_wr_27 wdata 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up_es_reset_29 ready up_es_ready_29 false up_rx_29 pll_locked up_rx_pll_locked_29 rst up_rx_rst_29 user_ready up_rx_user_ready_29 rst_done up_rx_rst_done_29 prbssel up_rx_prbssel_29 prbscntreset up_rx_prbscntreset_29 prbserr up_rx_prbserr_29 prbslocked up_rx_prbslocked_29 bufstatus up_rx_bufstatus_29 bufstatus_rst up_rx_bufstatus_rst_29 lpm_dfe_n up_rx_lpm_dfe_n_29 rate up_rx_rate_29 sys_clk_sel up_rx_sys_clk_sel_29 out_clk_sel up_rx_out_clk_sel_29 enb up_rx_enb_29 addr up_rx_addr_29 wr up_rx_wr_29 wdata up_rx_wdata_29 rdata up_rx_rdata_29 ready up_rx_ready_29 false up_tx_29 pll_locked up_tx_pll_locked_29 rst up_tx_rst_29 user_ready up_tx_user_ready_29 rst_done up_tx_rst_done_29 prbsforceerr up_tx_prbsforceerr_29 prbssel up_tx_prbssel_29 bufstatus up_tx_bufstatus_29 lpm_dfe_n up_tx_lpm_dfe_n_29 rate up_tx_rate_29 sys_clk_sel up_tx_sys_clk_sel_29 out_clk_sel up_tx_out_clk_sel_29 tx_diffctrl up_tx_diffctrl_29 tx_postcursor up_tx_postcursor_29 tx_precursor up_tx_precursor_29 enb up_tx_enb_29 addr up_tx_addr_29 wr up_tx_wr_29 wdata up_tx_wdata_29 rdata up_tx_rdata_29 ready up_tx_ready_29 false rx_29 rxcharisk rx_charisk_29 rxnotintable rx_notintable_29 rxdisperr rx_disperr_29 rxdata rx_data_29 rxheader rx_header_29 rxblock_sync rx_block_sync_29 false tx_29 txcharisk tx_charisk_29 txdata tx_data_29 txheader tx_header_29 false up_es_30 enb up_es_enb_30 addr up_es_addr_30 wr up_es_wr_30 wdata up_es_wdata_30 rdata up_es_rdata_30 reset up_es_reset_30 ready up_es_ready_30 false up_rx_30 pll_locked up_rx_pll_locked_30 rst up_rx_rst_30 user_ready up_rx_user_ready_30 rst_done up_rx_rst_done_30 prbssel up_rx_prbssel_30 prbscntreset up_rx_prbscntreset_30 prbserr up_rx_prbserr_30 prbslocked up_rx_prbslocked_30 bufstatus up_rx_bufstatus_30 bufstatus_rst up_rx_bufstatus_rst_30 lpm_dfe_n up_rx_lpm_dfe_n_30 rate up_rx_rate_30 sys_clk_sel up_rx_sys_clk_sel_30 out_clk_sel up_rx_out_clk_sel_30 enb up_rx_enb_30 addr up_rx_addr_30 wr up_rx_wr_30 wdata up_rx_wdata_30 rdata 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xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_diffctrl_31 in 4 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_postcursor_31 in 4 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_precursor_31 in 4 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_enb_31 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_addr_31 in 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_wr_31 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_wdata_31 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_rdata_31 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_tx_ready_31 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation XCVR_TYPE Xcvr Type 0 RX_LANE_RATE Rx Lane Rate 12.5 TX_LANE_RATE Tx Lane Rate 12.5 LINK_MODE Link Mode 1 DATA_PATH_WIDTH Data Path Width 4 QPLL_REFCLK_DIV Qpll Refclk Div 1 QPLL_FBDIV_RATIO Qpll Fbdiv Ratio 1 POR_CFG Por Cfg 0x0006 PPF0_CFG Ppf0 Cfg 0x0600 PPF1_CFG Ppf1 Cfg 0x0600 QPLL_CFG Qpll Cfg "000011010000000000110000001" QPLL_FBDIV Qpll Fbdiv "0000110000" QPLL_CFG0 Qpll Cfg0 0x331C QPLL_CFG1 Qpll Cfg1 0xD038 QPLL_CFG1_G3 Qpll Cfg1 G3 0xD038 QPLL_CFG2 Qpll Cfg2 0x0FC0 QPLL_CFG2_G3 Qpll Cfg2 G3 0x0FC0 QPLL_CFG3 Qpll Cfg3 0x0120 QPLL_CFG4 Qpll Cfg4 0x0003 QPLL_CP_G3 Qpll Cp G3 "0000011111" QPLL_LPF Qpll Lpf "0100110111" QPLL_CP Qpll Cp "0001111111" CPLL_FBDIV Cpll Fbdiv 2 CPLL_FBDIV_4_5 Cpll Fbdiv 4 5 5 CPLL_CFG0 Cpll Cfg0 0x01FA CPLL_CFG1 Cpll Cfg1 0x0023 CPLL_CFG2 Cpll Cfg2 0x0002 CPLL_CFG3 Cpll Cfg3 0x0000 CH_HSPMUX Ch Hspmux 0x2424 PREIQ_FREQ_BST Preiq Freq Bst 0 RXPI_CFG0 Rxpi Cfg0 0x0002 RXPI_CFG1 Rxpi Cfg1 0x0015 RTX_BUF_CML_CTRL Rtx Buf Cml Ctrl "011" TX_NUM_OF_LANES Tx Num Of Lanes 8 TX_OUT_DIV Tx Out Div 1 TX_CLK25_DIV Tx Clk25 Div 20 TX_LANE_INVERT Tx Lane Invert 0 TX_PI_BIASSET Tx Pi Biasset 1 TXPI_CFG Txpi Cfg 0x0054 A_TXDIFFCTRL A Txdiffctrl "10110" RX_NUM_OF_LANES Rx Num Of Lanes 8 RX_OUT_DIV Rx Out Div 1 RX_CLK25_DIV Rx Clk25 Div 20 RX_DFE_LPM_CFG Rx Dfe Lpm Cfg 0x0104 RX_PMA_CFG Rx Pma Cfg 0x001E7080 RX_CDR_CFG Rx Cdr Cfg 0x0B000023FF10400020 RXCDR_CFG0 Rxcdr Cfg0 0x0002 RXCDR_CFG2 Rxcdr Cfg2 0x0269 RXCDR_CFG2_GEN2 Rxcdr Cfg2 Gen2 "1001100101" RXCDR_CFG2_GEN4 Rxcdr Cfg2 Gen4 0x00B4 RXCDR_CFG3 Rxcdr Cfg3 0x0012 RXCDR_CFG3_GEN2 Rxcdr Cfg3 Gen2 "011010" RXCDR_CFG3_GEN3 Rxcdr Cfg3 Gen3 0x0012 RXCDR_CFG3_GEN4 Rxcdr Cfg3 Gen4 0x0024 RXDFE_KH_CFG2 Rxdfe Kh Cfg2 0x0200 RXDFE_KH_CFG3 Rxdfe Kh Cfg3 0x4101 RX_WIDEMODE_CDR Rx Widemode Cdr "00" RX_XMODE_SEL Rx Xmode Sel "1" TXDRV_FREQBAND Txdrv Freqband 0 TXFE_CFG0 Txfe Cfg0 0x03C2 TXFE_CFG1 Txfe Cfg1 0x6C00 TXFE_CFG2 Txfe Cfg2 0x6C00 TXFE_CFG3 Txfe Cfg3 0x6C00 TXPI_CFG0 Txpi Cfg0 0x0300 TXPI_CFG1 Txpi Cfg1 0x1000 TXSWBST_EN Txswbst En 0 RX_LANE_INVERT Rx Lane Invert 0 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_pairs_07421b06 0 1 2 3 4 5 6 7 8 9 10 choice_pairs_1942b210 2 1 xilinx_anylanguagesynthesis_view_fileset util_adxcvr_constr.xdc xdc ../../jesd204/jesd204_common/sync_header_align.v verilogSource util_adxcvr_xch.v verilogSource util_adxcvr_xcm.v verilogSource ../../scripts/adi_xilinx_device_info_enc.tcl tclSource bd/bd.tcl tclSource util_adxcvr.v verilogSource CHECKSUM_ae47eb4b xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset ../../jesd204/jesd204_common/sync_header_align.v verilogSource util_adxcvr_xch.v verilogSource util_adxcvr_xcm.v verilogSource ../../scripts/adi_xilinx_device_info_enc.tcl tclSource bd/bd.tcl tclSource util_adxcvr.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/util_adxcvr_v1_0.tcl tclSource CHECKSUM_fedc5936 XGUI_VERSION_2 xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_utilityxitfiles_view_fileset gui/util_adxcvr_v1_0.gtcl GTCL util_adxcvr_v1_0 XCVR_TYPE Xcvr Type 0 RX_LANE_RATE Rx Lane Rate (Gbps) 12.5 TX_LANE_RATE Tx Lane Rate (Gbps) 12.5 LINK_MODE Link Layer mode 1 DATA_PATH_WIDTH Data Path Width 4 true QPLL_REFCLK_DIV Qpll Refclk Div 1 QPLL_FBDIV_RATIO Qpll Fbdiv Ratio 1 POR_CFG Por Cfg 0x0006 PPF0_CFG Ppf0 Cfg 0x0600 PPF1_CFG Ppf1 Cfg 0x0600 QPLL_CFG Qpll Cfg "000011010000000000110000001" QPLL_FBDIV Qpll Fbdiv "0000110000" QPLL_CFG0 Qpll Cfg0 0x331C QPLL_CFG1 Qpll Cfg1 0xD038 QPLL_CFG1_G3 Qpll Cfg1 G3 0xD038 QPLL_CFG2 Qpll Cfg2 0x0FC0 QPLL_CFG2_G3 Qpll Cfg2 G3 0x0FC0 QPLL_CFG3 Qpll Cfg3 0x0120 QPLL_CFG4 Qpll Cfg4 0x0003 QPLL_CP_G3 Qpll Cp G3 "0000011111" QPLL_LPF Qpll Lpf "0100110111" QPLL_CP Qpll Cp "0001111111" CPLL_FBDIV Cpll Fbdiv 2 CPLL_FBDIV_4_5 Cpll Fbdiv 4 5 5 CPLL_CFG0 Cpll Cfg0 0x01FA CPLL_CFG1 Cpll Cfg1 0x0023 CPLL_CFG2 Cpll Cfg2 0x0002 CPLL_CFG3 Cpll Cfg3 0x0000 CH_HSPMUX Ch Hspmux 0x2424 PREIQ_FREQ_BST Preiq Freq Bst 0 RXPI_CFG0 Rxpi Cfg0 0x0002 RXPI_CFG1 Rxpi Cfg1 0x0015 RTX_BUF_CML_CTRL Rtx Buf Cml Ctrl "011" TX_NUM_OF_LANES Tx Num Of Lanes 8 TX_OUT_DIV Tx Out Div 1 TX_CLK25_DIV Tx Clk25 Div 20 TX_LANE_INVERT Tx Lane Invert 0 TX_PI_BIASSET Tx Pi Biasset 1 TXPI_CFG Txpi Cfg 0x0054 A_TXDIFFCTRL A Txdiffctrl "10110" RX_NUM_OF_LANES Rx Num Of Lanes 8 RX_OUT_DIV Rx Out Div 1 RX_CLK25_DIV Rx Clk25 Div 20 RX_DFE_LPM_CFG Rx Dfe Lpm Cfg 0x0104 RX_PMA_CFG Rx Pma Cfg 0x001E7080 RX_CDR_CFG Rx Cdr Cfg 0x0B000023FF10400020 RXCDR_CFG0 Rxcdr Cfg0 0x0002 RXCDR_CFG2 Rxcdr Cfg2 0x0269 RXCDR_CFG2_GEN2 Rxcdr Cfg2 Gen2 "1001100101" RXCDR_CFG2_GEN4 Rxcdr Cfg2 Gen4 0x00B4 RXCDR_CFG3 Rxcdr Cfg3 0x0012 RXCDR_CFG3_GEN2 Rxcdr Cfg3 Gen2 "011010" RXCDR_CFG3_GEN3 Rxcdr Cfg3 Gen3 0x0012 RXCDR_CFG3_GEN4 Rxcdr Cfg3 Gen4 0x0024 RXDFE_KH_CFG2 Rxdfe Kh Cfg2 0x0200 RXDFE_KH_CFG3 Rxdfe Kh Cfg3 0x4101 RX_WIDEMODE_CDR Rx Widemode Cdr "00" RX_XMODE_SEL Rx Xmode Sel "1" TXDRV_FREQBAND Txdrv Freqband 0 TXFE_CFG0 Txfe Cfg0 0x03C2 TXFE_CFG1 Txfe Cfg1 0x6C00 TXFE_CFG2 Txfe Cfg2 0x6C00 TXFE_CFG3 Txfe Cfg3 0x6C00 TXPI_CFG0 Txpi Cfg0 0x0300 TXPI_CFG1 Txpi Cfg1 0x1000 TXSWBST_EN Txswbst En 0 RX_LANE_INVERT Rx Lane Invert 0 Component_Name util_adxcvr_v1_0 virtex7 /Analog_Devices util_adxcvr_v1_0 level_2 package_project Analog Devices https://wiki.analog.com/resources/fpga/docs/util_xcvr 1 2024-06-06T03:15:47Z 2024.1