analog.com user jesd204_rx 1.0 rx_phy0 rxdata phy_data 31 0 rxcharisk phy_charisk 3 0 rxdisperr phy_disperr 3 0 rxnotintable phy_notintable 3 0 rxheader phy_header 1 0 rxblock_sync phy_block_sync 0 0 true rx_phy1 rxdata phy_data 63 32 rxcharisk phy_charisk 7 4 rxdisperr phy_disperr 7 4 rxnotintable phy_notintable 7 4 rxheader phy_header 3 2 rxblock_sync phy_block_sync 1 1 false rx_phy2 rxdata phy_data 95 64 rxcharisk phy_charisk 11 8 rxdisperr phy_disperr 11 8 rxnotintable phy_notintable 11 8 rxheader phy_header 5 4 rxblock_sync phy_block_sync 2 2 false rx_phy3 rxdata phy_data 127 96 rxcharisk phy_charisk 15 12 rxdisperr phy_disperr 15 12 rxnotintable phy_notintable 15 12 rxheader phy_header 7 6 rxblock_sync phy_block_sync 3 3 false rx_phy4 rxdata phy_data 159 128 rxcharisk phy_charisk 19 16 rxdisperr phy_disperr 19 16 rxnotintable phy_notintable 19 16 rxheader phy_header 9 8 rxblock_sync phy_block_sync 4 4 false rx_phy5 rxdata phy_data 191 160 rxcharisk phy_charisk 23 20 rxdisperr phy_disperr 23 20 rxnotintable phy_notintable 23 20 rxheader phy_header 11 10 rxblock_sync phy_block_sync 5 5 false rx_phy6 rxdata phy_data 223 192 rxcharisk phy_charisk 27 24 rxdisperr phy_disperr 27 24 rxnotintable phy_notintable 27 24 rxheader phy_header 13 12 rxblock_sync phy_block_sync 6 6 false rx_phy7 rxdata phy_data 255 224 rxcharisk phy_charisk 31 28 rxdisperr phy_disperr 31 28 rxnotintable phy_notintable 31 28 rxheader phy_header 15 14 rxblock_sync phy_block_sync 7 7 false rx_phy8 rxdata phy_data 287 256 rxcharisk phy_charisk 35 32 rxdisperr phy_disperr 35 32 rxnotintable phy_notintable 35 32 rxheader phy_header 17 16 rxblock_sync phy_block_sync 8 8 false rx_phy9 rxdata phy_data 319 288 rxcharisk phy_charisk 39 36 rxdisperr phy_disperr 39 36 rxnotintable phy_notintable 39 36 rxheader phy_header 19 18 rxblock_sync phy_block_sync 9 9 false rx_phy10 rxdata phy_data 351 320 rxcharisk phy_charisk 43 40 rxdisperr phy_disperr 43 40 rxnotintable phy_notintable 43 40 rxheader phy_header 21 20 rxblock_sync phy_block_sync 10 10 false rx_phy11 rxdata phy_data 383 352 rxcharisk phy_charisk 47 44 rxdisperr phy_disperr 47 44 rxnotintable phy_notintable 47 44 rxheader phy_header 23 22 rxblock_sync phy_block_sync 11 11 false rx_phy12 rxdata phy_data 415 384 rxcharisk phy_charisk 51 48 rxdisperr phy_disperr 51 48 rxnotintable phy_notintable 51 48 rxheader phy_header 25 24 rxblock_sync phy_block_sync 12 12 false rx_phy13 rxdata phy_data 447 416 rxcharisk phy_charisk 55 52 rxdisperr phy_disperr 55 52 rxnotintable phy_notintable 55 52 rxheader phy_header 27 26 rxblock_sync phy_block_sync 13 13 false rx_phy14 rxdata phy_data 479 448 rxcharisk phy_charisk 59 56 rxdisperr phy_disperr 59 56 rxnotintable phy_notintable 59 56 rxheader phy_header 29 28 rxblock_sync phy_block_sync 14 14 false rx_phy15 rxdata phy_data 511 480 rxcharisk phy_charisk 63 60 rxdisperr phy_disperr 63 60 rxnotintable phy_notintable 63 60 rxheader phy_header 31 30 rxblock_sync phy_block_sync 15 15 false rx_phy16 rxdata phy_data 543 512 rxcharisk phy_charisk 67 64 rxdisperr phy_disperr 67 64 rxnotintable phy_notintable 67 64 rxheader phy_header 33 32 rxblock_sync phy_block_sync 16 16 false rx_phy17 rxdata phy_data 575 544 rxcharisk phy_charisk 71 68 rxdisperr phy_disperr 71 68 rxnotintable phy_notintable 71 68 rxheader phy_header 35 34 rxblock_sync phy_block_sync 17 17 false rx_phy18 rxdata phy_data 607 576 rxcharisk phy_charisk 75 72 rxdisperr phy_disperr 75 72 rxnotintable phy_notintable 75 72 rxheader phy_header 37 36 rxblock_sync phy_block_sync 18 18 false rx_phy19 rxdata phy_data 639 608 rxcharisk phy_charisk 79 76 rxdisperr phy_disperr 79 76 rxnotintable phy_notintable 79 76 rxheader phy_header 39 38 rxblock_sync phy_block_sync 19 19 false rx_phy20 rxdata phy_data 671 640 rxcharisk phy_charisk 83 80 rxdisperr phy_disperr 83 80 rxnotintable phy_notintable 83 80 rxheader phy_header 41 40 rxblock_sync phy_block_sync 20 20 false rx_phy21 rxdata phy_data 703 672 rxcharisk phy_charisk 87 84 rxdisperr phy_disperr 87 84 rxnotintable phy_notintable 87 84 rxheader phy_header 43 42 rxblock_sync phy_block_sync 21 21 false rx_phy22 rxdata phy_data 735 704 rxcharisk phy_charisk 91 88 rxdisperr phy_disperr 91 88 rxnotintable phy_notintable 91 88 rxheader phy_header 45 44 rxblock_sync phy_block_sync 22 22 false rx_phy23 rxdata phy_data 767 736 rxcharisk phy_charisk 95 92 rxdisperr phy_disperr 95 92 rxnotintable phy_notintable 95 92 rxheader phy_header 47 46 rxblock_sync phy_block_sync 23 23 false rx_phy24 rxdata phy_data 799 768 rxcharisk phy_charisk 99 96 rxdisperr phy_disperr 99 96 rxnotintable phy_notintable 99 96 rxheader phy_header 49 48 rxblock_sync phy_block_sync 24 24 false rx_phy25 rxdata phy_data 831 800 rxcharisk phy_charisk 103 100 rxdisperr phy_disperr 103 100 rxnotintable phy_notintable 103 100 rxheader phy_header 51 50 rxblock_sync phy_block_sync 25 25 false rx_phy26 rxdata phy_data 863 832 rxcharisk phy_charisk 107 104 rxdisperr phy_disperr 107 104 rxnotintable phy_notintable 107 104 rxheader phy_header 53 52 rxblock_sync phy_block_sync 26 26 false rx_phy27 rxdata phy_data 895 864 rxcharisk phy_charisk 111 108 rxdisperr phy_disperr 111 108 rxnotintable phy_notintable 111 108 rxheader phy_header 55 54 rxblock_sync phy_block_sync 27 27 false rx_phy28 rxdata phy_data 927 896 rxcharisk phy_charisk 115 112 rxdisperr phy_disperr 115 112 rxnotintable phy_notintable 115 112 rxheader phy_header 57 56 rxblock_sync phy_block_sync 28 28 false rx_phy29 rxdata phy_data 959 928 rxcharisk phy_charisk 119 116 rxdisperr phy_disperr 119 116 rxnotintable phy_notintable 119 116 rxheader phy_header 59 58 rxblock_sync phy_block_sync 29 29 false rx_phy30 rxdata phy_data 991 960 rxcharisk phy_charisk 123 120 rxdisperr phy_disperr 123 120 rxnotintable phy_notintable 123 120 rxheader phy_header 61 60 rxblock_sync phy_block_sync 30 30 false rx_phy31 rxdata phy_data 1023 992 rxcharisk phy_charisk 127 124 rxdisperr phy_disperr 127 124 rxnotintable phy_notintable 127 124 rxheader phy_header 63 62 rxblock_sync phy_block_sync 31 31 false rx_cfg lanes_disable cfg_lanes_disable links_disable cfg_links_disable octets_per_multiframe cfg_octets_per_multiframe octets_per_frame cfg_octets_per_frame disable_scrambler cfg_disable_scrambler disable_char_replacement cfg_disable_char_replacement frame_align_err_threshold cfg_frame_align_err_threshold device_octets_per_multiframe device_cfg_octets_per_multiframe device_octets_per_frame device_cfg_octets_per_frame device_beats_per_multiframe device_cfg_beats_per_multiframe device_lmfc_offset device_cfg_lmfc_offset device_sysref_oneshot device_cfg_sysref_oneshot device_sysref_disable device_cfg_sysref_disable device_buffer_delay device_cfg_buffer_delay device_buffer_early_release device_cfg_buffer_early_release err_statistics_reset ctrl_err_statistics_reset err_statistics_mask ctrl_err_statistics_mask rx_status ctrl_state status_ctrl_state lane_cgs_state status_lane_cgs_state lane_emb_state status_lane_emb_state err_statistics_cnt status_err_statistics_cnt lane_ifs_ready status_lane_ifs_ready lane_latency status_lane_latency lane_frame_align_err_cnt status_lane_frame_align_err_cnt synth_params0 status_synth_params0 synth_params1 status_synth_params1 synth_params2 status_synth_params2 rx_ilas_config valid ilas_config_valid addr ilas_config_addr data ilas_config_data true rx_event sysref_alignment_error device_event_sysref_alignment_error sysref_edge device_event_sysref_edge frame_alignment_error event_frame_alignment_error unexpected_lane_state_error event_unexpected_lane_state_error rx_cfg_rx_ilas_config_rx_event_rx_status_signal_clock rx_cfg_rx_ilas_config_rx_event_rx_status_signal_clock CLK clk ASSOCIATED_BUSIF rx_cfg:rx_ilas_config:rx_event:rx_status ASSOCIATED_RESET reset rx_cfg_rx_ilas_config_rx_event_rx_status_signal_reset rx_cfg_rx_ilas_config_rx_event_rx_status_signal_reset RST reset POLARITY ACTIVE_HIGH rx_data_signal_clock rx_data_signal_clock CLK device_clk ASSOCIATED_BUSIF rx_data ASSOCIATED_RESET device_reset rx_data_signal_reset rx_data_signal_reset RST device_reset POLARITY ACTIVE_HIGH xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog jesd204_rx xilinx_anylanguagesynthesis_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum 92d764be xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog jesd204_rx xilinx_anylanguagebehavioralsimulation_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 92d764be xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum 01adfe72 xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_blockdiagram_view_fileset xilinx_utilityxitfiles Utility XIT/TTCL :vivado.xilinx.com:xit.util xilinx_utilityxitfiles_view_fileset clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation phy_data in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 phy_header in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 phy_charisk in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 phy_notintable in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 phy_disperr in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 phy_block_sync in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sysref in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation lmfc_edge out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation lmfc_clk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_event_sysref_alignment_error out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_event_sysref_edge out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation event_frame_alignment_error out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation event_unexpected_lane_state_error out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true phy_en_char_align out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true rx_data out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_eof out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_sof out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_eomf out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_somf out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_lanes_disable in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_links_disable in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_octets_per_multiframe in 9 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_octets_per_frame in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_disable_scrambler in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_disable_char_replacement in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_frame_align_err_threshold in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_octets_per_multiframe in 9 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_octets_per_frame in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_beats_per_multiframe in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_lmfc_offset in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_sysref_oneshot in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_sysref_disable in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_buffer_early_release in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation device_cfg_buffer_delay in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ctrl_err_statistics_reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ctrl_err_statistics_mask in 6 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_err_statistics_cnt out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ilas_config_valid out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ilas_config_addr out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ilas_config_data out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_ctrl_state out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_lane_cgs_state out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_lane_ifs_ready out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_lane_latency out 13 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_lane_emb_state out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_lane_frame_align_err_cnt out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_synth_params0 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_synth_params1 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_synth_params2 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 NUM_INPUT_PIPELINE Num Input Pipeline 1 NUM_OUTPUT_PIPELINE Num Output Pipeline 1 LINK_MODE Link Mode 1 DATA_PATH_WIDTH Data Path Width 4 ENABLE_FRAME_ALIGN_CHECK Enable Frame Align Check 1 ENABLE_FRAME_ALIGN_ERR_RESET Enable Frame Align Err Reset 0 ENABLE_CHAR_REPLACE Enable Char Replace 0 ASYNC_CLK Async Clk 1 TPL_DATA_PATH_WIDTH Tpl Data Path Width 4 choice_pairs_1942b210 2 1 xilinx_anylanguagesynthesis_view_fileset jesd204_rx_ooc.ttcl ttcl jesd204_rx_constr.ttcl ttcl jesd204_rx_lane.v verilogSource jesd204_rx_lane_64b.v verilogSource jesd204_rx_header.v verilogSource jesd204_rx_cgs.v verilogSource jesd204_rx_ctrl.v verilogSource jesd204_rx_ctrl_64b.v verilogSource elastic_buffer.v verilogSource error_monitor.v verilogSource jesd204_ilas_monitor.v verilogSource align_mux.v verilogSource jesd204_lane_latency_monitor.v verilogSource jesd204_rx_frame_align.v verilogSource jesd204_rx.v verilogSource ../../common/ad_pack.v verilogSource bd/bd.tcl tclSource ../../common/ad_upack.v verilogSource CHECKSUM_1efbc24f xilinx_anylanguagesynthesis_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset jesd204_rx_lane.v verilogSource jesd204_rx_lane_64b.v verilogSource jesd204_rx_header.v verilogSource jesd204_rx_cgs.v verilogSource jesd204_rx_ctrl.v verilogSource jesd204_rx_ctrl_64b.v verilogSource elastic_buffer.v verilogSource error_monitor.v verilogSource jesd204_ilas_monitor.v verilogSource align_mux.v verilogSource jesd204_lane_latency_monitor.v verilogSource jesd204_rx_frame_align.v verilogSource jesd204_rx.v verilogSource ../../common/ad_pack.v verilogSource bd/bd.tcl tclSource ../../common/ad_upack.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/jesd204_rx_v1_0.tcl tclSource CHECKSUM_8cf9565f XGUI_VERSION_2 xilinx_xpgui_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource xilinx_blockdiagram_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_utilityxitfiles_view_fileset gui/jesd204_rx_v1_0.gtcl GTCL ADI JESD204 Receive NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 NUM_INPUT_PIPELINE Num Input Pipeline 1 NUM_OUTPUT_PIPELINE Num Output Pipeline 1 LINK_MODE Link Layer mode 1 DATA_PATH_WIDTH Data Path Width 4 true ENABLE_FRAME_ALIGN_CHECK Enable Frame Align Check 1 ENABLE_FRAME_ALIGN_ERR_RESET Enable Frame Align Err Reset 0 ENABLE_CHAR_REPLACE Enable Char Replace 0 ASYNC_CLK Link and Device Clock Asynchronous 1 TPL_DATA_PATH_WIDTH Tpl Data Path Width 4 Component_Name jesd204_rx_v1_0 SYSREF_IOB Place SYSREF in IOB true virtex7 /Analog_Devices ADI JESD204 Receive level_2 package_project Analog Devices http://www.analog.com 1 2024-06-06T03:09:13Z 2024.1