analog.com
user
axi_ad9250
1.0
s_axi
AWADDR
s_axi_awaddr
AWPROT
s_axi_awprot
AWVALID
s_axi_awvalid
AWREADY
s_axi_awready
WDATA
s_axi_wdata
WSTRB
s_axi_wstrb
WVALID
s_axi_wvalid
WREADY
s_axi_wready
BRESP
s_axi_bresp
BVALID
s_axi_bvalid
BREADY
s_axi_bready
ARADDR
s_axi_araddr
ARPROT
s_axi_arprot
ARVALID
s_axi_arvalid
ARREADY
s_axi_arready
RDATA
s_axi_rdata
RRESP
s_axi_rresp
RVALID
s_axi_rvalid
RREADY
s_axi_rready
s_axi_aclk
CLK
s_axi_aclk
ASSOCIATED_BUSIF
s_axi
ASSOCIATED_RESET
s_axi_aresetn
s_axi_aresetn
RST
s_axi_aresetn
POLARITY
ACTIVE_LOW
rx_clk
CLK
rx_clk
adc_clk
CLK
adc_clk
s_axi
axi_lite
0
4096
0
xilinx_anylanguagesynthesis
Synthesis
:vivado.xilinx.com:synthesis
Verilog
axi_ad9250
xilinx_anylanguagesynthesis_analog_com_user_ad_ip_jesd204_tpl_adc_1_0__ref_view_fileset
xilinx_anylanguagesynthesis_view_fileset
viewChecksum
8673dcf2
xilinx_anylanguagebehavioralsimulation
Simulation
:vivado.xilinx.com:simulation
Verilog
axi_ad9250
xilinx_anylanguagebehavioralsimulation_analog_com_user_ad_ip_jesd204_tpl_adc_1_0__ref_view_fileset
xilinx_anylanguagebehavioralsimulation_view_fileset
viewChecksum
8673dcf2
xilinx_xpgui
UI Layout
:vivado.xilinx.com:xgui.ui
xilinx_xpgui_analog_com_user_ad_ip_jesd204_tpl_adc_1_0__ref_view_fileset
xilinx_xpgui_view_fileset
viewChecksum
783e7a8b
xilinx_blockdiagram
Block Diagram
:vivado.xilinx.com:block.diagram
xilinx_blockdiagram_analog_com_user_ad_ip_jesd204_tpl_adc_1_0__ref_view_fileset
xilinx_blockdiagram_view_fileset
rx_clk
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
rx_sof
in
3
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
rx_valid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
rx_data
in
63
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
rx_ready
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
adc_clk
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
adc_valid_a
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
adc_enable_a
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
adc_data_a
out
31
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
adc_valid_b
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
adc_enable_b
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
adc_data_b
out
31
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
adc_dovf
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_aclk
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_aresetn
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_awvalid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_awaddr
in
11
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_awprot
in
2
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_awready
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_wvalid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_wdata
in
31
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_wstrb
in
3
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
1
s_axi_wready
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_bvalid
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_bresp
out
1
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_bready
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_arvalid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_araddr
in
11
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_arprot
in
2
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_arready
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_rvalid
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_rdata
out
31
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_rresp
out
1
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_rready
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
ID
Id
0
FPGA_TECHNOLOGY
Fpga Technology
0
FPGA_FAMILY
Fpga Family
0
SPEED_GRADE
Speed Grade
0
DEV_PACKAGE
Dev Package
0
choice_list_74b5137e
ACTIVE_HIGH
ACTIVE_LOW
choice_pairs_00ecfe9a
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
choice_pairs_19f99f31
0
10
11
12
13
14
20
21
22
23
24
25
30
choice_pairs_28f798a2
0
1
2
3
4
choice_pairs_fc01a186
0
1
2
3
4
5
6
xilinx_anylanguagesynthesis_view_fileset
axi_ad9250.v
verilogSource
CHECKSUM_8673dcf2
xilinx_anylanguagesynthesis_analog_com_user_ad_ip_jesd204_tpl_adc_1_0__ref_view_fileset
xilinx_anylanguagebehavioralsimulation_view_fileset
axi_ad9250.v
verilogSource
xilinx_anylanguagebehavioralsimulation_analog_com_user_ad_ip_jesd204_tpl_adc_1_0__ref_view_fileset
xilinx_xpgui_view_fileset
xgui/axi_ad9250_v1_0.tcl
tclSource
CHECKSUM_14b777a3
XGUI_VERSION_2
xilinx_xpgui_analog_com_user_ad_ip_jesd204_tpl_adc_1_0__ref_view_fileset
xilinx_blockdiagram_view_fileset
bd/bd.tcl
tclSource
xilinx_blockdiagram_analog_com_user_ad_ip_jesd204_tpl_adc_1_0__ref_view_fileset
axi_ad9250_v1_0
ID
Id
0
FPGA_TECHNOLOGY
Fpga Technology
0
FPGA_FAMILY
Fpga Family
0
SPEED_GRADE
Speed Grade
0
DEV_PACKAGE
Dev Package
0
Component_Name
axi_ad9250_v1_0
virtex7
qvirtex7
versal
kintex7
kintex7l
qkintex7
qkintex7l
akintex7
artix7
artix7l
aartix7
qartix7
zynq
qzynq
azynq
spartan7
aspartan7
virtexu
zynquplus
virtexuplus
virtexuplusHBM
virtexuplus58g
kintexuplus
artixuplus
kintexu
/Analog_Devices
axi_ad9250_v1_0
level_2
package_project
Analog Devices
http://www.analog.com
1
2024-01-14T03:40:16Z
2023.2.1