analog.com user spi_engine_interconnect 1.0 m_ctrl CMD_READY m_cmd_ready CMD_VALID m_cmd_valid CMD_DATA m_cmd_data SDO_READY m_sdo_ready SDO_VALID m_sdo_valid SDO_DATA m_sdo_data SDI_READY m_sdi_ready SDI_VALID m_sdi_valid SDI_DATA m_sdi_data SYNC_READY m_sync_ready SYNC_VALID m_sync_valid SYNC_DATA m_sync m_ctrl_signal_clock m_ctrl_signal_clock CLK clk ASSOCIATED_BUSIF m_ctrl ASSOCIATED_RESET resetn m_ctrl_signal_reset m_ctrl_signal_reset RST resetn POLARITY ACTIVE_LOW s0_ctrl CMD_READY s0_cmd_ready CMD_VALID s0_cmd_valid CMD_DATA s0_cmd_data SDO_READY s0_sdo_ready SDO_VALID s0_sdo_valid SDO_DATA s0_sdo_data SDI_READY s0_sdi_ready SDI_VALID s0_sdi_valid SDI_DATA s0_sdi_data SYNC_READY s0_sync_ready SYNC_VALID s0_sync_valid SYNC_DATA s0_sync s0_ctrl_signal_clock s0_ctrl_signal_clock CLK clk ASSOCIATED_BUSIF s0_ctrl ASSOCIATED_RESET resetn s0_ctrl_signal_reset s0_ctrl_signal_reset RST resetn POLARITY ACTIVE_LOW s1_ctrl CMD_READY s1_cmd_ready CMD_VALID s1_cmd_valid CMD_DATA s1_cmd_data SDO_READY s1_sdo_ready SDO_VALID s1_sdo_valid SDO_DATA s1_sdo_data SDI_READY s1_sdi_ready SDI_VALID s1_sdi_valid SDI_DATA s1_sdi_data SYNC_READY s1_sync_ready SYNC_VALID s1_sync_valid SYNC_DATA s1_sync s1_ctrl_signal_clock s1_ctrl_signal_clock CLK clk ASSOCIATED_BUSIF s1_ctrl ASSOCIATED_RESET resetn s1_ctrl_signal_reset s1_ctrl_signal_reset RST resetn POLARITY ACTIVE_LOW xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog spi_engine_interconnect xilinx_anylanguagesynthesis_view_fileset viewChecksum d4ae3839 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog spi_engine_interconnect xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum d4ae3839 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum e4fdc10e clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation resetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_cmd_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_cmd_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_cmd_data out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_sdo_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_sdo_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_sdo_data out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_sdi_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_sdi_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_sdi_data in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_sync_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_sync_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_sync in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s0_cmd_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s0_cmd_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s0_cmd_data in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s0_sdo_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s0_sdo_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s0_sdo_data in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s0_sdi_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s0_sdi_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s0_sdi_data out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s0_sync_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s0_sync_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s0_sync out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s1_cmd_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s1_cmd_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s1_cmd_data in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s1_sdo_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s1_sdo_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s1_sdo_data in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s1_sdi_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s1_sdi_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s1_sdi_data out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s1_sync_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s1_sync_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s1_sync out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation DATA_WIDTH Data Width 8 NUM_OF_SDI Num Of Sdi 1 xilinx_anylanguagesynthesis_view_fileset spi_engine_interconnect.v verilogSource CHECKSUM_d4ae3839 xilinx_anylanguagebehavioralsimulation_view_fileset spi_engine_interconnect.v verilogSource xilinx_xpgui_view_fileset xgui/spi_engine_interconnect_v1_0.tcl tclSource CHECKSUM_d9e58594 XGUI_VERSION_2 spi_engine_interconnect_v1_0 DATA_WIDTH Parallel data width 8 NUM_OF_SDI Number of MISO lines 1 Component_Name spi_engine_interconnect_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices spi_engine_interconnect_v1_0 level_2 package_project Analog Devices https://wiki.analog.com/resources/fpga/peripherals/spi_engine/interconnect 1 2024-01-14T03:52:56Z 2023.2.1