analog.com user axi_adcfifo 1.0 axi AWID axi_awid AWADDR axi_awaddr AWLEN axi_awlen AWSIZE axi_awsize AWBURST axi_awburst AWLOCK axi_awlock AWCACHE axi_awcache AWPROT axi_awprot AWQOS axi_awqos AWUSER axi_awuser AWVALID axi_awvalid AWREADY axi_awready WDATA axi_wdata WSTRB axi_wstrb WLAST axi_wlast WUSER axi_wuser WVALID axi_wvalid WREADY axi_wready BID axi_bid BRESP axi_bresp BUSER axi_buser BVALID axi_bvalid BREADY axi_bready ARID axi_arid ARADDR axi_araddr ARLEN axi_arlen ARSIZE axi_arsize ARBURST axi_arburst ARLOCK axi_arlock ARCACHE axi_arcache ARPROT axi_arprot ARQOS axi_arqos ARUSER axi_aruser ARVALID axi_arvalid ARREADY axi_arready RID axi_rid RDATA axi_rdata RRESP axi_rresp RLAST axi_rlast RUSER axi_ruser RVALID axi_rvalid RREADY axi_rready axi_clk CLK axi_clk ASSOCIATED_BUSIF axi ASSOCIATED_RESET axi_resetn axi_resetn RST axi_resetn POLARITY ACTIVE_LOW dma_clk CLK dma_clk adc_clk CLK adc_clk ASSOCIATED_RESET adc_rst adc_rst RST adc_rst axi 4294967296 512 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_adcfifo xilinx_anylanguagesynthesis_view_fileset viewChecksum 9d3409ef xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_adcfifo xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 26ee1cce xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 9aae2ee9 adc_rst in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_wr in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_wdata in 127 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_wovf out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_wr out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_wdata out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_wready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_xfer_req in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_xfer_status out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_resetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_awvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_awid out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_awburst out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_awlock out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_awcache out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_awprot out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_awqos out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_awuser out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_awlen out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_awsize out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_awaddr out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_awready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 axi_wvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_wdata out 511 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_wstrb out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_wlast out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_wuser out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_wready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 axi_bvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 axi_bid in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 axi_bresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 axi_buser in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 axi_bready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_arvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_arid out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_arburst out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_arlock out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_arcache out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_arprot out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_arqos out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_aruser out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_arlen out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_arsize out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_araddr out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_arready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 axi_rvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 axi_rid in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 axi_ruser in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 axi_rresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 axi_rlast in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 axi_rdata in 511 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 axi_rready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ADC_DATA_WIDTH Adc Data Width 128 DMA_DATA_WIDTH Dma Data Width 64 AXI_DATA_WIDTH Axi Data Width 512 DMA_READY_ENABLE Dma Ready Enable 1 AXI_SIZE Axi Size 2 AXI_LENGTH Axi Length 16 AXI_ADDRESS Axi Address 0x00000000 AXI_ADDRESS_LIMIT Axi Address Limit 0xFFFFFFFF choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset axi_adcfifo_constr.xdc xdc ../../common/ad_axis_inf_rx.v verilogSource ../../common/ad_mem.v verilogSource ../../common/ad_mem_asym.v verilogSource axi_adcfifo_adc.v verilogSource axi_adcfifo_dma.v verilogSource axi_adcfifo_rd.v verilogSource axi_adcfifo_wr.v verilogSource ../../common/up_xfer_status.v verilogSource axi_adcfifo.v verilogSource CHECKSUM_1b6ed270 xilinx_anylanguagebehavioralsimulation_view_fileset ../../common/ad_axis_inf_rx.v verilogSource ../../common/ad_mem.v verilogSource ../../common/ad_mem_asym.v verilogSource axi_adcfifo_adc.v verilogSource axi_adcfifo_dma.v verilogSource axi_adcfifo_rd.v verilogSource axi_adcfifo_wr.v verilogSource ../../common/up_xfer_status.v verilogSource axi_adcfifo.v verilogSource xilinx_xpgui_view_fileset xgui/axi_adcfifo_v1_0.tcl tclSource CHECKSUM_9aae2ee9 XGUI_VERSION_2 axi_adcfifo_v1_0 ADC_DATA_WIDTH Adc Data Width 128 DMA_DATA_WIDTH Dma Data Width 64 AXI_DATA_WIDTH Axi Data Width 512 DMA_READY_ENABLE Dma Ready Enable 1 AXI_SIZE Axi Size 2 AXI_LENGTH Axi Length 16 AXI_ADDRESS Axi Address 0x00000000 AXI_ADDRESS_LIMIT Axi Address Limit 0xFFFFFFFF Component_Name axi_adcfifo_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices axi_adcfifo_v1_0 level_2 package_project Analog Devices http://www.analog.com 1 2024-06-06T03:14:53Z 2024.1