analog.com user axi_ad5766 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW spi_engine_ctrl CMD_READY cmd_ready CMD_VALID cmd_valid CMD_DATA cmd_data SDO_READY sdo_data_ready SDO_VALID sdo_data_valid SDO_DATA sdo_data SDI_READY sdi_data_ready SDI_VALID sdi_data_valid SDI_DATA sdi_data SYNC_READY sync_ready SYNC_VALID sync_valid SYNC_DATA sync_data spi_engine_offload_ctrl CMD_WR_EN ctrl_cmd_wr_en CMD_WR_DATA ctrl_cmd_wr_data ENABLE ctrl_enable ENABLED ctrl_enabled MEM_RESET ctrl_mem_reset spi_engine_offload_ctrl_signal_clock spi_engine_offload_ctrl_signal_clock CLK ctrl_clk ASSOCIATED_BUSIF spi_engine_offload_ctrl spi_engine_ctrl_signal_clock spi_engine_ctrl_signal_clock CLK spi_clk ASSOCIATED_BUSIF spi_engine_ctrl ASSOCIATED_RESET spi_resetn spi_engine_ctrl_signal_reset spi_engine_ctrl_signal_reset RST spi_resetn POLARITY ACTIVE_LOW dma_fifo_tx_signal_clock dma_fifo_tx_signal_clock CLK dma_clk ASSOCIATED_BUSIF dma_fifo_tx s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_ad5766 xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum effc7a98 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_ad5766 xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum effc7a98 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum cd4b316c xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_blockdiagram_view_fileset s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_clk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_valid out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_enable in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_data in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dma_xfer_req in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_underflow in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation spi_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation spi_resetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cmd_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cmd_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cmd_data out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdo_data_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sdo_data_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdo_data out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdi_data_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdi_data_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sdi_data in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sync_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync_data in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ctrl_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ctrl_cmd_wr_en in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ctrl_cmd_wr_data in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ctrl_enable in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ctrl_enabled out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ctrl_mem_reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 ASYNC_SPI_CLK Async Spi Clk 0 CMD_MEM_ADDRESS_WIDTH Cmd Mem Address Width 4 SDO_MEM_ADDRESS_WIDTH Sdo Mem Address Width 4 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_pairs_00ecfe9a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 choice_pairs_19f99f31 0 10 11 12 13 14 20 21 22 23 24 25 30 choice_pairs_28f798a2 0 1 2 3 4 choice_pairs_fc01a186 0 1 2 3 4 5 6 xilinx_anylanguagesynthesis_view_fileset ../common/ad_rst.v verilogSource up_ad5766_sequencer.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_dac_common.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource ../common/util_pulse_gen.v verilogSource axi_ad5766.v verilogSource CHECKSUM_285d8cd9 xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_rst.v verilogSource up_ad5766_sequencer.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_dac_common.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource ../common/util_pulse_gen.v verilogSource axi_ad5766.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/axi_ad5766_v1_0.tcl tclSource CHECKSUM_092e488f XGUI_VERSION_2 xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset axi_ad5766_v1_0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 ASYNC_SPI_CLK Async Spi Clk 0 CMD_MEM_ADDRESS_WIDTH Cmd Mem Address Width 4 SDO_MEM_ADDRESS_WIDTH Sdo Mem Address Width 4 Component_Name axi_ad5766_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices axi_ad5766_v1_0 level_2 package_project Analog Devices http://www.analog.com 1 2024-01-14T03:38:31Z 2023.2.1