analog.com user util_do_ram 1.0 s_axis TREADY s_axis_ready TVALID s_axis_valid TDATA s_axis_data TSTRB s_axis_strb TKEEP s_axis_keep TUSER s_axis_user TLAST s_axis_last m_axis TREADY m_axis_ready TVALID m_axis_valid TDATA m_axis_data TSTRB m_axis_strb TKEEP m_axis_keep TUSER m_axis_user TLAST m_axis_last wr_ctrl request_enable wr_request_enable request_valid wr_request_valid request_ready wr_request_ready request_length wr_request_length response_measured_length wr_response_measured_length response_eot wr_response_eot rd_ctrl request_enable rd_request_enable request_valid rd_request_valid request_ready rd_request_ready request_length rd_request_length response_eot rd_response_eot s_axis_wr_ctrl_signal_clock s_axis_wr_ctrl_signal_clock CLK s_axis_aclk ASSOCIATED_BUSIF s_axis:wr_ctrl ASSOCIATED_RESET s_axis_aresetn s_axis_wr_ctrl_signal_reset s_axis_wr_ctrl_signal_reset RST s_axis_aresetn POLARITY ACTIVE_LOW m_axis_rd_ctrl_signal_clock m_axis_rd_ctrl_signal_clock CLK m_axis_aclk ASSOCIATED_BUSIF m_axis:rd_ctrl ASSOCIATED_RESET m_axis_aresetn m_axis_rd_ctrl_signal_reset m_axis_rd_ctrl_signal_reset RST m_axis_aresetn POLARITY ACTIVE_LOW xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_do_ram xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum f913396f xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_do_ram xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum f913396f xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_util_axis_fifo_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum 770a1483 wr_request_enable in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation wr_request_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation wr_request_ready out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0x0 wr_request_length in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation wr_response_measured_length out 15 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0x00000000 wr_response_eot out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0x0 rd_request_enable in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rd_request_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rd_request_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rd_request_length in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rd_response_eot out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_ready out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0x0 s_axis_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_data in 511 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axis_strb in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_keep in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_user in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_last in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_data out 127 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_strb out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_keep out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_user out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_last out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation SRC_DATA_WIDTH Src Data Width 512 DST_DATA_WIDTH Dst Data Width 128 LENGTH_WIDTH Length Width 16 xilinx_anylanguagesynthesis_view_fileset util_do_ram_ooc.ttcl ttcl util_do_ram_constr.xdc xdc processing_order late ../common/ad_mem_asym.v verilogSource util_do_ram.v verilogSource CHECKSUM_94f67d2d xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_mem_asym.v verilogSource util_do_ram.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/util_do_ram_v1_0.tcl tclSource CHECKSUM_770a1483 XGUI_VERSION_2 xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_util_axis_fifo_1_0__ref_view_fileset Serves as storage for the Data Offload core, using Block RAM or URAM SRC_DATA_WIDTH Src Data Width 512 DST_DATA_WIDTH Dst Data Width 128 LENGTH_WIDTH Length Width 16 Component_Name util_do_ram_v1_0 virtex7 /Analog_Devices ADI Data Offload RAM Storage level_2 package_project Analog Devices http://www.analog.com 1 2024-01-14T03:54:37Z 2023.2.1