analog.com user axi_pwm_gen 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW ext_clk CLK ext_clk s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis SystemVerilog axi_pwm_gen xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum e9e1139f xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation SystemVerilog axi_pwm_gen xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum f808a9db xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum c4bc8231 xilinx_utilityxitfiles Utility XIT/TTCL :vivado.xilinx.com:xit.util xilinx_utilityxitfiles_view_fileset s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ext_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true ext_sync in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false pwm_0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true pwm_1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false pwm_2 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false pwm_3 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false pwm_4 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false pwm_5 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false pwm_6 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false pwm_7 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false pwm_8 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false pwm_9 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false pwm_10 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false pwm_11 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false pwm_12 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false pwm_13 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false pwm_14 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false pwm_15 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ID Id 0 ASYNC_CLK_EN Async Clk En true N_PWMS N Pwms 1 PWM_EXT_SYNC Pwm Ext Sync 0 EXT_ASYNC_SYNC Ext Async Sync 0 false SOFTWARE_BRINGUP Software Bringup 1 EXT_SYNC_PHASE_ALIGN Ext Sync Phase Align 0 false FORCE_ALIGN Force Align 0 START_AT_SYNC Start At Sync 1 PULSE_0_WIDTH Pulse 0 Width 7 PULSE_1_WIDTH Pulse 1 Width 7 PULSE_2_WIDTH Pulse 2 Width 7 false PULSE_3_WIDTH Pulse 3 Width 7 false PULSE_4_WIDTH Pulse 4 Width 7 false PULSE_5_WIDTH Pulse 5 Width 7 false PULSE_6_WIDTH Pulse 6 Width 7 false PULSE_7_WIDTH Pulse 7 Width 7 false PULSE_8_WIDTH Pulse 8 Width 7 false PULSE_9_WIDTH Pulse 9 Width 7 false PULSE_10_WIDTH Pulse 10 Width 7 false PULSE_11_WIDTH Pulse 11 Width 7 false PULSE_12_WIDTH Pulse 12 Width 7 false PULSE_13_WIDTH Pulse 13 Width 7 false PULSE_14_WIDTH Pulse 14 Width 7 false PULSE_15_WIDTH Pulse 15 Width 7 false PULSE_0_PERIOD Pulse 0 Period 10 PULSE_1_PERIOD Pulse 1 Period 10 PULSE_2_PERIOD Pulse 2 Period 10 false PULSE_3_PERIOD Pulse 3 Period 10 false PULSE_4_PERIOD Pulse 4 Period 10 false PULSE_5_PERIOD Pulse 5 Period 10 false PULSE_6_PERIOD Pulse 6 Period 10 false PULSE_7_PERIOD Pulse 7 Period 10 false PULSE_8_PERIOD Pulse 8 Period 10 false PULSE_9_PERIOD Pulse 9 Period 10 false PULSE_10_PERIOD Pulse 10 Period 10 false PULSE_11_PERIOD Pulse 11 Period 10 false PULSE_12_PERIOD Pulse 12 Period 10 false PULSE_13_PERIOD Pulse 13 Period 10 false PULSE_14_PERIOD Pulse 14 Period 10 false PULSE_15_PERIOD Pulse 15 Period 10 false PULSE_0_OFFSET Pulse 0 Offset 0 PULSE_1_OFFSET Pulse 1 Offset 0 PULSE_2_OFFSET Pulse 2 Offset 0 false PULSE_3_OFFSET Pulse 3 Offset 0 false PULSE_4_OFFSET Pulse 4 Offset 0 false PULSE_5_OFFSET Pulse 5 Offset 0 false PULSE_6_OFFSET Pulse 6 Offset 0 false PULSE_7_OFFSET Pulse 7 Offset 0 false PULSE_8_OFFSET Pulse 8 Offset 0 false PULSE_9_OFFSET Pulse 9 Offset 0 false PULSE_10_OFFSET Pulse 10 Offset 0 false PULSE_11_OFFSET Pulse 11 Offset 0 false PULSE_12_OFFSET Pulse 12 Offset 0 false PULSE_13_OFFSET Pulse 13 Offset 0 false PULSE_14_OFFSET Pulse 14 Offset 0 false PULSE_15_OFFSET Pulse 15 Offset 0 false choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset axi_pwm_gen_constr.ttcl ttcl ../xilinx/common/ad_rst_constr.xdc xdc ../common/ad_rst.v verilogSource axi_pwm_gen_1.v verilogSource ../common/up_axi.v verilogSource axi_pwm_gen_regmap.sv systemVerilogSource axi_pwm_gen.sv systemVerilogSource CHECKSUM_ab87ef54 xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_rst.v verilogSource axi_pwm_gen_1.v verilogSource ../common/up_axi.v verilogSource axi_pwm_gen_regmap.sv systemVerilogSource axi_pwm_gen.sv systemVerilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/axi_pwm_gen_v1_0.tcl tclSource CHECKSUM_d4b1a0c8 XGUI_VERSION_2 xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_utilityxitfiles_view_fileset gui/axi_pwm_gen_v1_0.gtcl GTCL ADI AXI PWM Generator ID Id 0 ASYNC_CLK_EN ASYNC_CLK_EN true N_PWMS Number of pwms 1 PWM_EXT_SYNC External sync 0 EXT_ASYNC_SYNC External sync signal is asynchronous 0 false SOFTWARE_BRINGUP Require software bringup 1 EXT_SYNC_PHASE_ALIGN External sync enable phase align 0 false FORCE_ALIGN Force align 0 START_AT_SYNC Start at sync 1 PULSE_0_WIDTH PULSE 0 width 7 true PULSE_1_WIDTH PULSE 1 width 7 true PULSE_2_WIDTH PULSE 2 width 7 false PULSE_3_WIDTH PULSE 3 width 7 false PULSE_4_WIDTH PULSE 4 width 7 false PULSE_5_WIDTH PULSE 5 width 7 false PULSE_6_WIDTH PULSE 6 width 7 false PULSE_7_WIDTH PULSE 7 width 7 false PULSE_8_WIDTH PULSE 8 width 7 false PULSE_9_WIDTH PULSE 9 width 7 false PULSE_10_WIDTH PULSE 10 width 7 false PULSE_11_WIDTH PULSE 11 width 7 false PULSE_12_WIDTH PULSE 12 width 7 false PULSE_13_WIDTH PULSE 13 width 7 false PULSE_14_WIDTH PULSE 14 width 7 false PULSE_15_WIDTH PULSE 15 width 7 false PULSE_0_PERIOD PULSE 0 period 10 true PULSE_1_PERIOD PULSE 1 period 10 true PULSE_2_PERIOD PULSE 2 period 10 false PULSE_3_PERIOD PULSE 3 period 10 false PULSE_4_PERIOD PULSE 4 period 10 false PULSE_5_PERIOD PULSE 5 period 10 false PULSE_6_PERIOD PULSE 6 period 10 false PULSE_7_PERIOD PULSE 7 period 10 false PULSE_8_PERIOD PULSE 8 period 10 false PULSE_9_PERIOD PULSE 9 period 10 false PULSE_10_PERIOD PULSE 10 period 10 false PULSE_11_PERIOD PULSE 11 period 10 false PULSE_12_PERIOD PULSE 12 period 10 false PULSE_13_PERIOD PULSE 13 period 10 false PULSE_14_PERIOD PULSE 14 period 10 false PULSE_15_PERIOD PULSE 15 period 10 false PULSE_0_OFFSET PULSE 0 offset 0 true PULSE_1_OFFSET PULSE 1 offset 0 true PULSE_2_OFFSET PULSE 2 offset 0 false PULSE_3_OFFSET PULSE 3 offset 0 false PULSE_4_OFFSET PULSE 4 offset 0 false PULSE_5_OFFSET PULSE 5 offset 0 false PULSE_6_OFFSET PULSE 6 offset 0 false PULSE_7_OFFSET PULSE 7 offset 0 false PULSE_8_OFFSET PULSE 8 offset 0 false PULSE_9_OFFSET PULSE 9 offset 0 false PULSE_10_OFFSET PULSE 10 offset 0 false PULSE_11_OFFSET PULSE 11 offset 0 false PULSE_12_OFFSET PULSE 12 offset 0 false PULSE_13_OFFSET PULSE 13 offset 0 false PULSE_14_OFFSET PULSE 14 offset 0 false PULSE_15_OFFSET PULSE 15 offset 0 false Component_Name axi_pwm_gen_v1_0 virtex7 /Analog_Devices ADI AXI PWM Generator level_2 package_project Analog Devices https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen 1 2024-06-06T03:05:23Z 2024.1