analog.com user axi_adrv9001 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW delay_clk CLK delay_clk adc_1_clk CLK adc_1_clk ASSOCIATED_RESET adc_1_rst adc_2_clk CLK adc_2_clk ASSOCIATED_RESET adc_2_rst dac_1_clk CLK dac_1_clk ASSOCIATED_RESET dac_1_rst dac_2_clk CLK dac_2_clk ASSOCIATED_RESET dac_2_rst adc_1_rst RST adc_1_rst POLARITY adc_2_rst RST adc_2_rst POLARITY dac_1_rst RST dac_1_rst POLARITY dac_2_rst RST dac_2_rst POLARITY s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_adrv9001 xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum cb9e5853 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_adrv9001 xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum f220243d xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum 7d3a131e xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_blockdiagram_view_fileset ref_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation mssi_sync in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 tx_output_enable in std_logic xilinx_anylanguagesynthesis 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xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx2_dclk_in_n_NC in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true rx2_dclk_in_p_dclk_in in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true rx2_idata_in_n_idata0 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true rx2_idata_in_p_idata1 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true rx2_qdata_in_n_qdata2 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true rx2_qdata_in_p_qdata3 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true rx2_strobe_in_n_NC in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true rx2_strobe_in_p_strobe_in in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true tx1_dclk_out_n_NC out std_logic xilinx_anylanguagesynthesis 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xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true tx2_dclk_out_p_dclk_out out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true tx2_dclk_in_n_NC in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true tx2_dclk_in_p_dclk_in in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true tx2_idata_out_n_idata0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true tx2_idata_out_p_idata1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true tx2_qdata_out_n_qdata2 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true tx2_qdata_out_p_qdata3 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true tx2_strobe_out_n_NC out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true tx2_strobe_out_p_strobe_out out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true rx1_enable out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx2_enable out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true tx1_enable out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tx2_enable out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true delay_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_1_clk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_1_rst out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_1_valid_i0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_1_enable_i0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_1_data_i0 out 15 0 std_logic_vector xilinx_anylanguagesynthesis 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xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ID Id 0 CMOS_LVDS_N Cmos Lvds N 0 TDD_DISABLE Tdd Disable 0 DDS_DISABLE Dds Disable 0 INDEPENDENT_1R1T_SUPPORT Independent 1r1t Support 1 COMMON_2R2T_SUPPORT Common 2r2t Support 1 DISABLE_RX2_SSI Disable Rx2 Ssi 0 DISABLE_TX2_SSI Disable Tx2 Ssi 0 RX_USE_BUFG Rx Use Bufg 0 TX_USE_BUFG Tx Use Bufg 0 IODELAY_CTRL Iodelay Ctrl 1 IODELAY_ENABLE Iodelay Enable 1 IO_DELAY_GROUP Io Delay Group dev_if_delay_group FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 EXT_SYNC Ext Sync 0 USE_RX_CLK_FOR_TX Use Rx Clk For Tx 0 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_pairs_19f99f31 0 10 11 12 13 14 20 21 22 23 24 25 30 choice_pairs_28f798a2 0 1 2 3 4 choice_pairs_a6e6e044 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 choice_pairs_a897e79d 0 1 2 3 4 5 6 7 xilinx_anylanguagesynthesis_view_fileset ../xilinx/common/up_xfer_cntrl_constr.xdc xdc ../xilinx/common/ad_rst_constr.xdc xdc ../xilinx/common/up_xfer_status_constr.xdc xdc ../xilinx/common/up_clock_mon_constr.xdc xdc axi_adrv9001_constr.xdc xdc ../common/ad_addsub.v verilogSource ../common/ad_datafmt.v verilogSource ../common/ad_dds.v verilogSource ../common/ad_dds_1.v verilogSource ../common/ad_dds_2.v verilogSource ../common/ad_dds_cordic_pipe.v verilogSource ../common/ad_dds_sine.v verilogSource ../common/ad_dds_sine_cordic.v verilogSource ../xilinx/common/ad_mul.v verilogSource ../common/ad_pngen.v verilogSource ../common/ad_pnmon.v verilogSource ../common/ad_rst.v verilogSource ../xilinx/common/ad_serdes_in.v verilogSource ../xilinx/common/ad_serdes_out.v verilogSource ../common/ad_tdd_control.v verilogSource adrv9001_aligner4.v verilogSource adrv9001_aligner8.v verilogSource adrv9001_pack.v verilogSource adrv9001_rx.v verilogSource adrv9001_rx_link.v verilogSource adrv9001_tx.v verilogSource adrv9001_tx_link.v verilogSource axi_adrv9001_core.v verilogSource axi_adrv9001_if.v verilogSource axi_adrv9001_rx.v verilogSource axi_adrv9001_rx_channel.v verilogSource axi_adrv9001_tdd.v verilogSource axi_adrv9001_tx.v verilogSource axi_adrv9001_tx_channel.v verilogSource ../common/up_adc_channel.v verilogSource ../common/up_adc_common.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_dac_channel.v verilogSource ../common/up_dac_common.v verilogSource ../common/up_delay_cntrl.v verilogSource ../common/up_tdd_cntrl.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_adrv9001.v verilogSource CHECKSUM_bbc86102 xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_addsub.v verilogSource ../common/ad_datafmt.v verilogSource ../common/ad_dds.v verilogSource ../common/ad_dds_1.v verilogSource ../common/ad_dds_2.v verilogSource ../common/ad_dds_cordic_pipe.v verilogSource ../common/ad_dds_sine.v verilogSource ../common/ad_dds_sine_cordic.v verilogSource ../xilinx/common/ad_mul.v verilogSource ../common/ad_pngen.v verilogSource ../common/ad_pnmon.v verilogSource ../common/ad_rst.v verilogSource ../xilinx/common/ad_serdes_in.v verilogSource ../xilinx/common/ad_serdes_out.v verilogSource ../common/ad_tdd_control.v verilogSource adrv9001_aligner4.v verilogSource adrv9001_aligner8.v verilogSource adrv9001_pack.v verilogSource adrv9001_rx.v verilogSource adrv9001_rx_link.v verilogSource adrv9001_tx.v verilogSource adrv9001_tx_link.v verilogSource axi_adrv9001_core.v verilogSource axi_adrv9001_if.v verilogSource axi_adrv9001_rx.v verilogSource axi_adrv9001_rx_channel.v verilogSource axi_adrv9001_tdd.v verilogSource axi_adrv9001_tx.v verilogSource axi_adrv9001_tx_channel.v verilogSource ../common/up_adc_channel.v verilogSource ../common/up_adc_common.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_dac_channel.v verilogSource ../common/up_dac_common.v verilogSource ../common/up_delay_cntrl.v verilogSource ../common/up_tdd_cntrl.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_adrv9001.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/axi_adrv9001_v1_0.tcl tclSource CHECKSUM_372ea539 XGUI_VERSION_2 xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset axi_adrv9001_v1_0 ID Id 0 CMOS_LVDS_N Cmos Lvds N 0 TDD_DISABLE Tdd Disable 0 DDS_DISABLE Dds Disable 0 INDEPENDENT_1R1T_SUPPORT Independent 1r1t Support 1 COMMON_2R2T_SUPPORT Common 2r2t Support 1 DISABLE_RX2_SSI Disable Rx2 Ssi 0 DISABLE_TX2_SSI Disable Tx2 Ssi 0 RX_USE_BUFG Rx Use Bufg 0 TX_USE_BUFG Tx Use Bufg 0 IODELAY_CTRL Iodelay Ctrl 1 IODELAY_ENABLE Iodelay Enable 1 IO_DELAY_GROUP Io Delay Group dev_if_delay_group FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 EXT_SYNC External sync 0 USE_RX_CLK_FOR_TX Use Rx Clk For Tx 0 Component_Name axi_adrv9001_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices axi_adrv9001_v1_0 level_2 package_project XPM_CDC Analog Devices http://www.analog.com 1 2024-06-06T03:01:04Z 2024.1