analog.com user util_hbm 1.0 s_axis TREADY s_axis_ready TVALID s_axis_valid TDATA s_axis_data TSTRB s_axis_strb TKEEP s_axis_keep TUSER s_axis_user TLAST s_axis_last m_axis TREADY m_axis_ready TVALID m_axis_valid TDATA m_axis_data TSTRB m_axis_strb TKEEP m_axis_keep TUSER m_axis_user TLAST m_axis_last MAXI_0 ARADDR m_axi_araddr 31 0 ARBURST m_axi_arburst 1 0 ARLEN m_axi_arlen 7 0 ARREADY m_axi_arready 0 0 ARSIZE m_axi_arsize 2 0 ARVALID m_axi_arvalid 0 0 AWADDR m_axi_awaddr 31 0 AWBURST m_axi_awburst 1 0 AWLEN m_axi_awlen 7 0 AWREADY m_axi_awready 0 0 AWSIZE m_axi_awsize 2 0 AWVALID m_axi_awvalid 0 0 BREADY m_axi_bready 0 0 BRESP m_axi_bresp 1 0 BVALID m_axi_bvalid 0 0 RDATA m_axi_rdata 255 0 RLAST m_axi_rlast 0 0 RREADY m_axi_rready 0 0 RRESP m_axi_rresp 1 0 RVALID m_axi_rvalid 0 0 WDATA m_axi_wdata 255 0 WLAST m_axi_wlast 0 0 WREADY m_axi_wready 0 0 WSTRB m_axi_wstrb 31 0 WVALID m_axi_wvalid 0 0 SUPPORTS_NARROW_BURST 0 true MAXI_1 ARADDR m_axi_araddr 63 32 ARBURST m_axi_arburst 3 2 ARLEN m_axi_arlen 15 8 ARREADY m_axi_arready 1 1 ARSIZE m_axi_arsize 5 3 ARVALID m_axi_arvalid 1 1 AWADDR m_axi_awaddr 63 32 AWBURST m_axi_awburst 3 2 AWLEN m_axi_awlen 15 8 AWREADY m_axi_awready 1 1 AWSIZE m_axi_awsize 5 3 AWVALID m_axi_awvalid 1 1 BREADY m_axi_bready 1 1 BRESP m_axi_bresp 3 2 BVALID m_axi_bvalid 1 1 RDATA m_axi_rdata 511 256 RLAST m_axi_rlast 1 1 RREADY m_axi_rready 1 1 RRESP m_axi_rresp 3 2 RVALID m_axi_rvalid 1 1 WDATA m_axi_wdata 511 256 WLAST m_axi_wlast 1 1 WREADY m_axi_wready 1 1 WSTRB m_axi_wstrb 63 32 WVALID m_axi_wvalid 1 1 SUPPORTS_NARROW_BURST 0 true MAXI_2 ARADDR m_axi_araddr 95 64 ARBURST m_axi_arburst 5 4 ARLEN m_axi_arlen 23 16 ARREADY m_axi_arready 2 2 ARSIZE m_axi_arsize 8 6 ARVALID m_axi_arvalid 2 2 AWADDR m_axi_awaddr 95 64 AWBURST m_axi_awburst 5 4 AWLEN m_axi_awlen 23 16 AWREADY m_axi_awready 2 2 AWSIZE m_axi_awsize 8 6 AWVALID m_axi_awvalid 2 2 BREADY m_axi_bready 2 2 BRESP m_axi_bresp 5 4 BVALID m_axi_bvalid 2 2 RDATA m_axi_rdata 767 512 RLAST m_axi_rlast 2 2 RREADY m_axi_rready 2 2 RRESP m_axi_rresp 5 4 RVALID m_axi_rvalid 2 2 WDATA m_axi_wdata 767 512 WLAST m_axi_wlast 2 2 WREADY m_axi_wready 2 2 WSTRB m_axi_wstrb 95 64 WVALID m_axi_wvalid 2 2 SUPPORTS_NARROW_BURST 0 false MAXI_3 ARADDR m_axi_araddr 127 96 ARBURST m_axi_arburst 7 6 ARLEN m_axi_arlen 31 24 ARREADY m_axi_arready 3 3 ARSIZE m_axi_arsize 11 9 ARVALID m_axi_arvalid 3 3 AWADDR m_axi_awaddr 127 96 AWBURST m_axi_awburst 7 6 AWLEN m_axi_awlen 31 24 AWREADY m_axi_awready 3 3 AWSIZE m_axi_awsize 11 9 AWVALID m_axi_awvalid 3 3 BREADY m_axi_bready 3 3 BRESP m_axi_bresp 7 6 BVALID m_axi_bvalid 3 3 RDATA m_axi_rdata 1023 768 RLAST m_axi_rlast 3 3 RREADY m_axi_rready 3 3 RRESP m_axi_rresp 7 6 RVALID m_axi_rvalid 3 3 WDATA m_axi_wdata 1023 768 WLAST m_axi_wlast 3 3 WREADY m_axi_wready 3 3 WSTRB m_axi_wstrb 127 96 WVALID m_axi_wvalid 3 3 SUPPORTS_NARROW_BURST 0 false MAXI_4 ARADDR m_axi_araddr 159 128 ARBURST m_axi_arburst 9 8 ARLEN m_axi_arlen 39 32 ARREADY m_axi_arready 4 4 ARSIZE m_axi_arsize 14 12 ARVALID m_axi_arvalid 4 4 AWADDR m_axi_awaddr 159 128 AWBURST m_axi_awburst 9 8 AWLEN m_axi_awlen 39 32 AWREADY m_axi_awready 4 4 AWSIZE m_axi_awsize 14 12 AWVALID m_axi_awvalid 4 4 BREADY m_axi_bready 4 4 BRESP m_axi_bresp 9 8 BVALID m_axi_bvalid 4 4 RDATA m_axi_rdata 1279 1024 RLAST m_axi_rlast 4 4 RREADY m_axi_rready 4 4 RRESP m_axi_rresp 9 8 RVALID m_axi_rvalid 4 4 WDATA m_axi_wdata 1279 1024 WLAST m_axi_wlast 4 4 WREADY m_axi_wready 4 4 WSTRB m_axi_wstrb 159 128 WVALID m_axi_wvalid 4 4 SUPPORTS_NARROW_BURST 0 false MAXI_5 ARADDR m_axi_araddr 191 160 ARBURST m_axi_arburst 11 10 ARLEN m_axi_arlen 47 40 ARREADY m_axi_arready 5 5 ARSIZE m_axi_arsize 17 15 ARVALID m_axi_arvalid 5 5 AWADDR m_axi_awaddr 191 160 AWBURST m_axi_awburst 11 10 AWLEN m_axi_awlen 47 40 AWREADY m_axi_awready 5 5 AWSIZE m_axi_awsize 17 15 AWVALID m_axi_awvalid 5 5 BREADY m_axi_bready 5 5 BRESP m_axi_bresp 11 10 BVALID m_axi_bvalid 5 5 RDATA m_axi_rdata 1535 1280 RLAST m_axi_rlast 5 5 RREADY m_axi_rready 5 5 RRESP m_axi_rresp 11 10 RVALID m_axi_rvalid 5 5 WDATA m_axi_wdata 1535 1280 WLAST m_axi_wlast 5 5 WREADY m_axi_wready 5 5 WSTRB m_axi_wstrb 191 160 WVALID m_axi_wvalid 5 5 SUPPORTS_NARROW_BURST 0 false MAXI_6 ARADDR m_axi_araddr 223 192 ARBURST m_axi_arburst 13 12 ARLEN m_axi_arlen 55 48 ARREADY m_axi_arready 6 6 ARSIZE m_axi_arsize 20 18 ARVALID m_axi_arvalid 6 6 AWADDR m_axi_awaddr 223 192 AWBURST m_axi_awburst 13 12 AWLEN m_axi_awlen 55 48 AWREADY m_axi_awready 6 6 AWSIZE m_axi_awsize 20 18 AWVALID m_axi_awvalid 6 6 BREADY m_axi_bready 6 6 BRESP m_axi_bresp 13 12 BVALID m_axi_bvalid 6 6 RDATA m_axi_rdata 1791 1536 RLAST m_axi_rlast 6 6 RREADY m_axi_rready 6 6 RRESP m_axi_rresp 13 12 RVALID m_axi_rvalid 6 6 WDATA m_axi_wdata 1791 1536 WLAST m_axi_wlast 6 6 WREADY m_axi_wready 6 6 WSTRB m_axi_wstrb 223 192 WVALID m_axi_wvalid 6 6 SUPPORTS_NARROW_BURST 0 false MAXI_7 ARADDR m_axi_araddr 255 224 ARBURST m_axi_arburst 15 14 ARLEN m_axi_arlen 63 56 ARREADY m_axi_arready 7 7 ARSIZE m_axi_arsize 23 21 ARVALID m_axi_arvalid 7 7 AWADDR m_axi_awaddr 255 224 AWBURST m_axi_awburst 15 14 AWLEN m_axi_awlen 63 56 AWREADY m_axi_awready 7 7 AWSIZE m_axi_awsize 23 21 AWVALID m_axi_awvalid 7 7 BREADY m_axi_bready 7 7 BRESP m_axi_bresp 15 14 BVALID m_axi_bvalid 7 7 RDATA m_axi_rdata 2047 1792 RLAST m_axi_rlast 7 7 RREADY m_axi_rready 7 7 RRESP m_axi_rresp 15 14 RVALID m_axi_rvalid 7 7 WDATA m_axi_wdata 2047 1792 WLAST m_axi_wlast 7 7 WREADY m_axi_wready 7 7 WSTRB m_axi_wstrb 255 224 WVALID m_axi_wvalid 7 7 SUPPORTS_NARROW_BURST 0 false MAXI_8 ARADDR m_axi_araddr 287 256 ARBURST m_axi_arburst 17 16 ARLEN m_axi_arlen 71 64 ARREADY m_axi_arready 8 8 ARSIZE m_axi_arsize 26 24 ARVALID m_axi_arvalid 8 8 AWADDR m_axi_awaddr 287 256 AWBURST m_axi_awburst 17 16 AWLEN m_axi_awlen 71 64 AWREADY m_axi_awready 8 8 AWSIZE m_axi_awsize 26 24 AWVALID m_axi_awvalid 8 8 BREADY m_axi_bready 8 8 BRESP m_axi_bresp 17 16 BVALID m_axi_bvalid 8 8 RDATA m_axi_rdata 2303 2048 RLAST m_axi_rlast 8 8 RREADY m_axi_rready 8 8 RRESP m_axi_rresp 17 16 RVALID m_axi_rvalid 8 8 WDATA m_axi_wdata 2303 2048 WLAST m_axi_wlast 8 8 WREADY m_axi_wready 8 8 WSTRB m_axi_wstrb 287 256 WVALID m_axi_wvalid 8 8 SUPPORTS_NARROW_BURST 0 false MAXI_9 ARADDR m_axi_araddr 319 288 ARBURST m_axi_arburst 19 18 ARLEN m_axi_arlen 79 72 ARREADY m_axi_arready 9 9 ARSIZE m_axi_arsize 29 27 ARVALID m_axi_arvalid 9 9 AWADDR m_axi_awaddr 319 288 AWBURST m_axi_awburst 19 18 AWLEN m_axi_awlen 79 72 AWREADY m_axi_awready 9 9 AWSIZE m_axi_awsize 29 27 AWVALID m_axi_awvalid 9 9 BREADY m_axi_bready 9 9 BRESP m_axi_bresp 19 18 BVALID m_axi_bvalid 9 9 RDATA m_axi_rdata 2559 2304 RLAST m_axi_rlast 9 9 RREADY m_axi_rready 9 9 RRESP m_axi_rresp 19 18 RVALID m_axi_rvalid 9 9 WDATA m_axi_wdata 2559 2304 WLAST m_axi_wlast 9 9 WREADY m_axi_wready 9 9 WSTRB m_axi_wstrb 319 288 WVALID m_axi_wvalid 9 9 SUPPORTS_NARROW_BURST 0 false MAXI_10 ARADDR m_axi_araddr 351 320 ARBURST m_axi_arburst 21 20 ARLEN m_axi_arlen 87 80 ARREADY m_axi_arready 10 10 ARSIZE m_axi_arsize 32 30 ARVALID m_axi_arvalid 10 10 AWADDR m_axi_awaddr 351 320 AWBURST m_axi_awburst 21 20 AWLEN m_axi_awlen 87 80 AWREADY m_axi_awready 10 10 AWSIZE m_axi_awsize 32 30 AWVALID m_axi_awvalid 10 10 BREADY m_axi_bready 10 10 BRESP m_axi_bresp 21 20 BVALID m_axi_bvalid 10 10 RDATA m_axi_rdata 2815 2560 RLAST m_axi_rlast 10 10 RREADY m_axi_rready 10 10 RRESP m_axi_rresp 21 20 RVALID m_axi_rvalid 10 10 WDATA m_axi_wdata 2815 2560 WLAST m_axi_wlast 10 10 WREADY m_axi_wready 10 10 WSTRB m_axi_wstrb 351 320 WVALID m_axi_wvalid 10 10 SUPPORTS_NARROW_BURST 0 false MAXI_11 ARADDR m_axi_araddr 383 352 ARBURST m_axi_arburst 23 22 ARLEN m_axi_arlen 95 88 ARREADY m_axi_arready 11 11 ARSIZE m_axi_arsize 35 33 ARVALID m_axi_arvalid 11 11 AWADDR m_axi_awaddr 383 352 AWBURST m_axi_awburst 23 22 AWLEN m_axi_awlen 95 88 AWREADY m_axi_awready 11 11 AWSIZE m_axi_awsize 35 33 AWVALID m_axi_awvalid 11 11 BREADY m_axi_bready 11 11 BRESP m_axi_bresp 23 22 BVALID m_axi_bvalid 11 11 RDATA m_axi_rdata 3071 2816 RLAST m_axi_rlast 11 11 RREADY m_axi_rready 11 11 RRESP m_axi_rresp 23 22 RVALID m_axi_rvalid 11 11 WDATA m_axi_wdata 3071 2816 WLAST m_axi_wlast 11 11 WREADY m_axi_wready 11 11 WSTRB m_axi_wstrb 383 352 WVALID m_axi_wvalid 11 11 SUPPORTS_NARROW_BURST 0 false MAXI_12 ARADDR m_axi_araddr 415 384 ARBURST m_axi_arburst 25 24 ARLEN m_axi_arlen 103 96 ARREADY m_axi_arready 12 12 ARSIZE m_axi_arsize 38 36 ARVALID m_axi_arvalid 12 12 AWADDR m_axi_awaddr 415 384 AWBURST m_axi_awburst 25 24 AWLEN m_axi_awlen 103 96 AWREADY m_axi_awready 12 12 AWSIZE m_axi_awsize 38 36 AWVALID m_axi_awvalid 12 12 BREADY m_axi_bready 12 12 BRESP m_axi_bresp 25 24 BVALID m_axi_bvalid 12 12 RDATA m_axi_rdata 3327 3072 RLAST m_axi_rlast 12 12 RREADY m_axi_rready 12 12 RRESP m_axi_rresp 25 24 RVALID m_axi_rvalid 12 12 WDATA m_axi_wdata 3327 3072 WLAST m_axi_wlast 12 12 WREADY m_axi_wready 12 12 WSTRB m_axi_wstrb 415 384 WVALID m_axi_wvalid 12 12 SUPPORTS_NARROW_BURST 0 false MAXI_13 ARADDR m_axi_araddr 447 416 ARBURST m_axi_arburst 27 26 ARLEN m_axi_arlen 111 104 ARREADY m_axi_arready 13 13 ARSIZE m_axi_arsize 41 39 ARVALID m_axi_arvalid 13 13 AWADDR m_axi_awaddr 447 416 AWBURST m_axi_awburst 27 26 AWLEN m_axi_awlen 111 104 AWREADY m_axi_awready 13 13 AWSIZE m_axi_awsize 41 39 AWVALID m_axi_awvalid 13 13 BREADY m_axi_bready 13 13 BRESP m_axi_bresp 27 26 BVALID m_axi_bvalid 13 13 RDATA m_axi_rdata 3583 3328 RLAST m_axi_rlast 13 13 RREADY m_axi_rready 13 13 RRESP m_axi_rresp 27 26 RVALID m_axi_rvalid 13 13 WDATA m_axi_wdata 3583 3328 WLAST m_axi_wlast 13 13 WREADY m_axi_wready 13 13 WSTRB m_axi_wstrb 447 416 WVALID m_axi_wvalid 13 13 SUPPORTS_NARROW_BURST 0 false MAXI_14 ARADDR m_axi_araddr 479 448 ARBURST m_axi_arburst 29 28 ARLEN m_axi_arlen 119 112 ARREADY m_axi_arready 14 14 ARSIZE m_axi_arsize 44 42 ARVALID m_axi_arvalid 14 14 AWADDR m_axi_awaddr 479 448 AWBURST m_axi_awburst 29 28 AWLEN m_axi_awlen 119 112 AWREADY m_axi_awready 14 14 AWSIZE m_axi_awsize 44 42 AWVALID m_axi_awvalid 14 14 BREADY m_axi_bready 14 14 BRESP m_axi_bresp 29 28 BVALID m_axi_bvalid 14 14 RDATA m_axi_rdata 3839 3584 RLAST m_axi_rlast 14 14 RREADY m_axi_rready 14 14 RRESP m_axi_rresp 29 28 RVALID m_axi_rvalid 14 14 WDATA m_axi_wdata 3839 3584 WLAST m_axi_wlast 14 14 WREADY m_axi_wready 14 14 WSTRB m_axi_wstrb 479 448 WVALID m_axi_wvalid 14 14 SUPPORTS_NARROW_BURST 0 false MAXI_15 ARADDR m_axi_araddr 511 480 ARBURST m_axi_arburst 31 30 ARLEN m_axi_arlen 127 120 ARREADY m_axi_arready 15 15 ARSIZE m_axi_arsize 47 45 ARVALID m_axi_arvalid 15 15 AWADDR m_axi_awaddr 511 480 AWBURST m_axi_awburst 31 30 AWLEN m_axi_awlen 127 120 AWREADY m_axi_awready 15 15 AWSIZE m_axi_awsize 47 45 AWVALID m_axi_awvalid 15 15 BREADY m_axi_bready 15 15 BRESP m_axi_bresp 31 30 BVALID m_axi_bvalid 15 15 RDATA m_axi_rdata 4095 3840 RLAST m_axi_rlast 15 15 RREADY m_axi_rready 15 15 RRESP m_axi_rresp 31 30 RVALID m_axi_rvalid 15 15 WDATA m_axi_wdata 4095 3840 WLAST m_axi_wlast 15 15 WREADY m_axi_wready 15 15 WSTRB m_axi_wstrb 511 480 WVALID m_axi_wvalid 15 15 SUPPORTS_NARROW_BURST 0 false _MAXI_0_MAXI_1_MAXI_2_MAXI_3_MAXI_4_MAXI_5_MAXI_6_MAXI_7_MAXI_8_MAXI_9_MAXI_10_MAXI_11_MAXI_12_MAXI_13_MAXI_14_MAXI_15_signal_clock _MAXI_0_MAXI_1_MAXI_2_MAXI_3_MAXI_4_MAXI_5_MAXI_6_MAXI_7_MAXI_8_MAXI_9_MAXI_10_MAXI_11_MAXI_12_MAXI_13_MAXI_14_MAXI_15_signal_clock CLK m_axi_aclk ASSOCIATED_BUSIF :MAXI_0:MAXI_1:MAXI_2:MAXI_3:MAXI_4:MAXI_5:MAXI_6:MAXI_7:MAXI_8:MAXI_9:MAXI_10:MAXI_11:MAXI_12:MAXI_13:MAXI_14:MAXI_15 ASSOCIATED_RESET m_axi_aresetn _MAXI_0_MAXI_1_MAXI_2_MAXI_3_MAXI_4_MAXI_5_MAXI_6_MAXI_7_MAXI_8_MAXI_9_MAXI_10_MAXI_11_MAXI_12_MAXI_13_MAXI_14_MAXI_15_signal_reset _MAXI_0_MAXI_1_MAXI_2_MAXI_3_MAXI_4_MAXI_5_MAXI_6_MAXI_7_MAXI_8_MAXI_9_MAXI_10_MAXI_11_MAXI_12_MAXI_13_MAXI_14_MAXI_15_signal_reset RST m_axi_aresetn POLARITY ACTIVE_LOW wr_ctrl request_enable wr_request_enable request_valid wr_request_valid request_ready wr_request_ready request_length wr_request_length response_measured_length wr_response_measured_length response_eot wr_response_eot status_overflow wr_overflow rd_ctrl request_enable rd_request_enable request_valid rd_request_valid request_ready rd_request_ready request_length rd_request_length response_eot rd_response_eot status_underflow rd_underflow s_axis_wr_ctrl_signal_clock s_axis_wr_ctrl_signal_clock CLK s_axis_aclk ASSOCIATED_BUSIF s_axis:wr_ctrl ASSOCIATED_RESET s_axis_aresetn s_axis_wr_ctrl_signal_reset s_axis_wr_ctrl_signal_reset RST s_axis_aresetn POLARITY ACTIVE_LOW m_axis_rd_ctrl_signal_clock m_axis_rd_ctrl_signal_clock CLK m_axis_aclk ASSOCIATED_BUSIF m_axis:rd_ctrl ASSOCIATED_RESET m_axis_aresetn m_axis_rd_ctrl_signal_reset m_axis_rd_ctrl_signal_reset RST m_axis_aresetn POLARITY ACTIVE_LOW MAXI_0 4G 1 MAXI_1 4G 1 MAXI_2 4G 1 MAXI_3 4G 1 MAXI_4 4G 1 MAXI_5 4G 1 MAXI_6 4G 1 MAXI_7 4G 1 MAXI_8 4G 1 MAXI_9 4G 1 MAXI_10 4G 1 MAXI_11 4G 1 MAXI_12 4G 1 MAXI_13 4G 1 MAXI_14 4G 1 MAXI_15 4G 1 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_hbm xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_axi_dmac_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum e53075f6 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_hbm xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_axi_dmac_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 9b7d6e4d xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_axi_dmac_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum b924abcc xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_blockdiagram_analog_com_user_axi_dmac_1_0__ref_view_fileset xilinx_blockdiagram_view_fileset xilinx_utilityxitfiles Utility XIT/TTCL :vivado.xilinx.com:xit.util xilinx_utilityxitfiles_view_fileset wr_request_enable in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation wr_request_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation wr_request_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation wr_request_length in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation wr_response_measured_length out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation wr_response_eot out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0x0 wr_overflow out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rd_request_enable in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rd_request_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rd_request_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rd_request_length in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rd_response_eot out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0x0 rd_underflow out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_data in 511 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axis_strb in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_keep in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_user in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_last in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_data out 511 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_strb out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_keep out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_user out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_last out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awaddr out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awlen out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awsize out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awburst out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awvalid out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awready in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_wdata out 511 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_wstrb out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_wready in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_wvalid out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_wlast out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_bvalid in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_bresp in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_bready out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_arready in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_arvalid out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_araddr out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_arlen out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_arsize out 5 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_arburst out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_rdata in 511 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_rready out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_rvalid in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_rresp in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_rlast in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation TX_RX_N Tx Rx N 1 SRC_DATA_WIDTH Src Data Width 512 DST_DATA_WIDTH Dst Data Width 512 LENGTH_WIDTH Length Width 32 AXI_PROTOCOL Axi Protocol 0 AXI_DATA_WIDTH Axi Data Width 256 AXI_ADDR_WIDTH Axi Addr Width 32 MEM_TYPE Mem Type 2 HBM_SEGMENTS_PER_MASTER Hbm Segments Per Master HBM_SEGMENT_INDEX Hbm Segment Index 0 DDR_BASE_ADDDRESS Ddr Base Adddress 0 false NUM_M Num M 2 SRC_FIFO_SIZE Src Fifo Size 8 DST_FIFO_SIZE Dst Fifo Size 8 choice_list_2fc640b2 16 32 64 128 256 512 1024 2048 4096 choice_list_90ee0cc7 32 64 128 256 512 1024 choice_list_9a3ef62d 2 4 8 16 32 choice_list_f4d5364e 1 2 4 8 16 choice_pairs_453b9fa5 1 0 choice_pairs_4b4b5176 2 1 choice_pairs_8bd59fa5 1 0 choice_pairs_cebf9777 28 29 30 31 32 33 34 xilinx_anylanguagesynthesis_view_fileset util_hbm_ooc.ttcl ttcl util_hbm_constr.xdc xdc processing_order late bd/bd.tcl tclSource util_hbm.v verilogSource CHECKSUM_a4a1e134 xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_axi_dmac_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset bd/bd.tcl tclSource util_hbm.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_axi_dmac_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/util_hbm_v1_0.tcl tclSource CHECKSUM_c86c89ca XGUI_VERSION_2 xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_axi_dmac_1_0__ref_view_fileset xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_blockdiagram_analog_com_user_axi_dmac_1_0__ref_view_fileset xilinx_utilityxitfiles_view_fileset gui/util_hbm_v1_0.gtcl GTCL Bridge between a AXI Stream master/slave interface and an AXI Memory Mapped interface TX_RX_N Datapath type 1 SRC_DATA_WIDTH Source AXIS Bus Width 512 DST_DATA_WIDTH Destination AXIS Bus Width 512 LENGTH_WIDTH Storage size 24 AXI_PROTOCOL AXI Protocol 0 AXI_DATA_WIDTH AXI Data Bus Width 256 AXI_ADDR_WIDTH Axi Addr Width 32 MEM_TYPE External Storage Type 2 HBM_SEGMENTS_PER_MASTER HBM sections per master false HBM_SEGMENT_INDEX First HBM section index 0 true DDR_BASE_ADDDRESS DDR base address 0 false NUM_M Number of AXI Masters 2 SRC_FIFO_SIZE Write Buffer Size 8 DST_FIFO_SIZE Read Buffer Size 8 Component_Name util_hbm_v1_0 virtex7 /Analog_Devices ADI AXIS to HBM/DDR AXI bridge level_2 package_project Analog Devices http://www.analog.com 1 2024-01-14T03:55:19Z 2023.2.1