analog.com user util_mii_to_rmii 1.0 GMII COL mii_col CRS mii_crs RXD mii_rxd RX_CLK mii_rx_clk RX_DV mii_rx_dv RX_ER mii_rx_er TXD mac_txd TX_CLK mii_tx_clk TX_EN mac_tx_en TX_ER mac_tx_er false MII COL mii_col CRS mii_crs RXD mii_rxd RX_CLK mii_rx_clk RX_DV mii_rx_dv RX_ER mii_rx_er TXD mac_txd TX_CLK mii_tx_clk TX_EN mac_tx_en TX_ER mac_tx_er true RMII CRS_DV phy_crs_dv RXD phy_rxd RX_ER phy_rx_er TXD rmii_txd TX_EN rmii_tx_en reset_n RST reset_n ref_clk CLK ref_clk xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_mii_to_rmii xilinx_anylanguagesynthesis_view_fileset viewChecksum 7f96d891 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_mii_to_rmii xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 7f96d891 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum c554a0dc mac_tx_en in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 mac_txd in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation mac_tx_er in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation mii_tx_clk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation mii_rx_clk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation mii_col out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation mii_crs out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation mii_rx_dv out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation mii_rx_er out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation mii_rxd out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rmii_txd out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rmii_tx_en out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation phy_rxd in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation phy_crs_dv in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation phy_rx_er in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ref_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reset_n in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation INTF_CFG Intf Cfg 0 RATE_10_100 Rate 10 100 0 choice_pairs_7362e83f 0 1 choice_pairs_bf1c9d7a 0 1 xilinx_anylanguagesynthesis_view_fileset mac_phy_link.v verilogSource phy_mac_link.v verilogSource util_mii_to_rmii.v verilogSource CHECKSUM_4eec8a2d xilinx_anylanguagebehavioralsimulation_view_fileset mac_phy_link.v verilogSource phy_mac_link.v verilogSource util_mii_to_rmii.v verilogSource xilinx_xpgui_view_fileset xgui/util_mii_to_rmii_v1_0.tcl tclSource CHECKSUM_7db2218e XGUI_VERSION_2 MII to RMII Converter IP INTF_CFG Interface Selection 0 RATE_10_100 Rate Selection 0 Component_Name util_mii_to_rmii_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices util_mii_to_rmii level_2 package_project Analog Devices http://www.analog.com 1 2024-01-14T03:55:44Z 2023.2.1