analog.com user util_sigma_delta_spi 1.0 m_spi SCLK m_sclk SDI m_sdi SDO m_sdo SDO_T m_sdo_t CS m_cs s_spi SCLK s_sclk SDI s_sdi SDO s_sdo SDO_T s_sdo_t CS s_cs m_spi_s_spi_signal_clock m_spi_s_spi_signal_clock CLK clk ASSOCIATED_BUSIF m_spi:s_spi ASSOCIATED_RESET resetn m_spi_s_spi_signal_reset m_spi_s_spi_signal_reset RST resetn POLARITY ACTIVE_LOW xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_sigma_delta_spi xilinx_anylanguagesynthesis_view_fileset viewChecksum 1b2e346e xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_sigma_delta_spi xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 1b2e346e xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum dfe70b83 clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation resetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation spi_active in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_sclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_sdo in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_sdo_t in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_sdi out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_cs in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_sclk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_sdo out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_sdo_t out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_sdi in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_cs out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_ready out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation NUM_OF_CS Num Of Cs 1 CS_PIN Cs Pin 0 IDLE_TIMEOUT Idle Timeout 63 xilinx_anylanguagesynthesis_view_fileset util_sigma_delta_spi.v verilogSource CHECKSUM_1b2e346e xilinx_anylanguagebehavioralsimulation_view_fileset util_sigma_delta_spi.v verilogSource xilinx_xpgui_view_fileset xgui/util_sigma_delta_spi_v1_0.tcl tclSource CHECKSUM_dfe70b83 XGUI_VERSION_2 util_sigma_delta_spi_v1_0 NUM_OF_CS Num Of Cs 1 CS_PIN Cs Pin 0 IDLE_TIMEOUT Idle Timeout 63 Component_Name util_sigma_delta_spi_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices util_sigma_delta_spi_v1_0 level_2 package_project Analog Devices http://www.analog.com 1 2024-01-14T03:56:37Z 2023.2.1