analog.com user spi_engine_execution 1.0 ctrl cmd_ready cmd_ready cmd_valid cmd_valid cmd_data cmd sdo_ready sdo_data_ready sdo_valid sdo_data_valid sdo_data sdo_data sdi_ready sdi_data_ready sdi_valid sdi_data_valid sdi_data sdi_data sync_ready sync_ready sync_valid sync_valid sync_data sync ctrl_signal_clock ctrl_signal_clock CLK clk ASSOCIATED_BUSIF ctrl ASSOCIATED_RESET resetn ctrl_signal_reset ctrl_signal_reset RST resetn POLARITY ACTIVE_LOW spi sclk sclk sdi sdi sdo sdo sdo_t sdo_t three_wire three_wire cs cs spi_signal_clock spi_signal_clock CLK clk ASSOCIATED_BUSIF spi ASSOCIATED_RESET resetn spi_signal_reset spi_signal_reset RST resetn POLARITY ACTIVE_LOW xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog spi_engine_execution xilinx_anylanguagesynthesis_view_fileset viewChecksum 8ce35280 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog spi_engine_execution xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 8ce35280 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 3d941b35 clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation resetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation active out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cmd_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cmd_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cmd in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdo_data_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sdo_data_ready out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdo_data in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdi_data_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sdi_data_valid out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdi_data out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync_valid out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation echo_sclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false sclk out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdo out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdo_t out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdi in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cs out 0 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation three_wire out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation NUM_OF_CS Num Of Cs 1 DEFAULT_SPI_CFG Default Spi Cfg 0 DEFAULT_CLK_DIV Default Clk Div 0 DATA_WIDTH Data Width 8 NUM_OF_SDI Num Of Sdi 1 SDO_DEFAULT Sdo Default "0" ECHO_SCLK Echo Sclk false SDI_DELAY Sdi Delay false choice_list_b71134be "0" "1" choice_list_dd9ee503 0 1 2 3 xilinx_anylanguagesynthesis_view_fileset spi_engine_execution_constr.ttcl ttcl spi_engine_execution.v verilogSource CHECKSUM_8ce35280 xilinx_anylanguagebehavioralsimulation_view_fileset spi_engine_execution.v verilogSource xilinx_xpgui_view_fileset xgui/spi_engine_execution_v1_0.tcl tclSource CHECKSUM_b2ce64e5 XGUI_VERSION_2 spi_engine_execution_v1_0 NUM_OF_CS Number of CSN lines 1 DEFAULT_SPI_CFG Default SPI mode 0 DEFAULT_CLK_DIV Default SCLK divider 0 DATA_WIDTH Parallel data width 8 NUM_OF_SDI Number of MISO 1 SDO_DEFAULT MOSI default level "0" ECHO_SCLK Echoed SCLK false SDI_DELAY Delay MISO latching false Component_Name spi_engine_execution_v1_0 virtex7 /Analog_Devices spi_engine_execution_v1_0 level_2 package_project Analog Devices https://wiki.analog.com/resources/fpga/peripherals/spi_engine/engine 1 2024-06-06T03:10:29Z 2024.1