analog.com user util_axis_fifo 1.0 s_axis TVALID s_axis_valid TREADY s_axis_ready TDATA s_axis_data TLAST s_axis_tlast TKEEP s_axis_tkeep m_axis TVALID m_axis_valid TREADY m_axis_ready TDATA m_axis_data TLAST m_axis_tlast TKEEP m_axis_tkeep m_axis_signal_clock m_axis_signal_clock CLK m_axis_aclk ASSOCIATED_BUSIF m_axis ASSOCIATED_RESET m_axis_aresetn m_axis_signal_reset m_axis_signal_reset RST m_axis_aresetn POLARITY ACTIVE_LOW s_axis_signal_clock s_axis_signal_clock CLK s_axis_aclk ASSOCIATED_BUSIF s_axis ASSOCIATED_RESET s_axis_aresetn s_axis_signal_reset s_axis_signal_reset RST s_axis_aresetn POLARITY ACTIVE_LOW xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_axis_fifo xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum 2735fcaa xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_axis_fifo xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 2735fcaa xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum fa323617 xilinx_utilityxitfiles Utility XIT/TTCL :vivado.xilinx.com:xit.util xilinx_utilityxitfiles_view_fileset m_axis_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_data out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tkeep out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true m_axis_tlast out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false m_axis_level out 4 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_empty out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_almost_empty out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_data in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axis_tkeep in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true s_axis_tlast in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false s_axis_room out 4 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_full out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_almost_full out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation DATA_WIDTH Data Width 64 ADDRESS_WIDTH Address Width 5 ASYNC_CLK Async Clk 1 M_AXIS_REGISTERED M Axis Registered true ALMOST_EMPTY_THRESHOLD Almost Empty Threshold 16 ALMOST_FULL_THRESHOLD Almost Full Threshold 16 TLAST_EN Tlast En false TKEEP_EN Tkeep En true REMOVE_NULL_BEAT_EN Remove Null Beat En false choice_list_a900bd4b 8 16 32 64 128 256 512 1024 2048 4096 choice_pairs_b09a2f00 0 1 xilinx_anylanguagesynthesis_view_fileset ../common/ad_mem.v verilogSource util_axis_fifo_address_generator.v verilogSource util_axis_fifo.v verilogSource CHECKSUM_f51e4483 xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_mem.v verilogSource util_axis_fifo_address_generator.v verilogSource util_axis_fifo.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/util_axis_fifo_v1_0.tcl tclSource CHECKSUM_d562f032 XGUI_VERSION_2 xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_utilityxitfiles_view_fileset gui/util_axis_fifo_v1_0.gtcl GTCL ADI AXI Stream FIFO DATA_WIDTH Data width 64 ADDRESS_WIDTH Address width 5 ASYNC_CLK Clocking mode 1 M_AXIS_REGISTERED Master AXIS Registered output true ALMOST_EMPTY_THRESHOLD Almost empty threshold 16 ALMOST_FULL_THRESHOLD Almost full threshold 16 TLAST_EN TLAST Enable false TKEEP_EN TKEEP Enable true REMOVE_NULL_BEAT_EN REMOVE_NULL_BEAT_EN Enable false true Component_Name util_axis_fifo_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices ADI AXI Stream FIFO level_2 package_project Analog Devices https://wiki.analog.com/resources/fpga/docs/util_axis_fifo 1 2024-06-06T03:01:48Z 2024.1