analog.com user util_axis_upscale 1.0 s_axis TVALID s_axis_valid TREADY s_axis_ready TDATA s_axis_data s_axis_signal_clock s_axis_signal_clock CLK clk ASSOCIATED_BUSIF s_axis:m_axis ASSOCIATED_RESET resetn s_axis_signal_reset s_axis_signal_reset RST resetn POLARITY ACTIVE_LOW m_axis TVALID m_axis_valid TREADY m_axis_ready TDATA m_axis_data xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_axis_upscale xilinx_anylanguagesynthesis_view_fileset viewChecksum dcedf3e5 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_axis_upscale xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum dcedf3e5 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 690ac9cf clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation resetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_ready out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_data in 95 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_axis_valid out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_data out 127 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dfmt_enable in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dfmt_type in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dfmt_se in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation NUM_OF_CHANNELS Num Of Channels 4 DATA_WIDTH Data Width 24 UDATA_WIDTH Udata Width 32 xilinx_anylanguagesynthesis_view_fileset ../common/util_axis_upscale.v verilogSource CHECKSUM_dcedf3e5 xilinx_anylanguagebehavioralsimulation_view_fileset ../common/util_axis_upscale.v verilogSource xilinx_xpgui_view_fileset xgui/util_axis_upscale_v1_0.tcl tclSource CHECKSUM_690ac9cf XGUI_VERSION_2 util_axis_upscale_v1_0 NUM_OF_CHANNELS Num Of Channels 4 DATA_WIDTH Data Width 24 UDATA_WIDTH Udata Width 32 Component_Name util_axis_upscale_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices util_axis_upscale_v1_0 level_2 package_project Analog Devices http://www.analog.com 1 2024-06-06T03:11:19Z 2024.1