analog.com user axi_tdd 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW clk CLK clk ASSOCIATED_RESET rst rst RST rst POLARITY ACTIVE_HIGH s_axi axi_lite 0 1024 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis SystemVerilog axi_tdd xilinx_anylanguagesynthesis_view_fileset viewChecksum 11c1d0ef xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation SystemVerilog axi_tdd xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 11c1d0ef xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 931062b4 clk in logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation resetn in logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync_in in logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync_out out logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tdd_channel out 7 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 9 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 9 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ID Id 0 CHANNEL_COUNT Channel Count 8 DEFAULT_POLARITY Default Polarity "00000000" REGISTER_WIDTH Register Width 32 BURST_COUNT_WIDTH Burst Count Width 32 SYNC_INTERNAL Sync Internal 1 SYNC_EXTERNAL Sync External 0 SYNC_EXTERNAL_CDC Sync External Cdc 0 SYNC_COUNT_WIDTH Sync Count Width 64 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset axi_tdd_constr.ttcl ttcl ../util_cdc/sync_bits.v verilogSource ../util_cdc/sync_data.v verilogSource ../util_cdc/sync_event.v verilogSource ../common/up_axi.v verilogSource axi_tdd_pkg.sv systemVerilogSource axi_tdd_channel.sv systemVerilogSource axi_tdd_counter.sv systemVerilogSource axi_tdd_regmap.sv systemVerilogSource axi_tdd_sync_gen.sv systemVerilogSource axi_tdd.sv systemVerilogSource CHECKSUM_f31068f0 xilinx_anylanguagebehavioralsimulation_view_fileset ../util_cdc/sync_bits.v verilogSource ../util_cdc/sync_data.v verilogSource ../util_cdc/sync_event.v verilogSource ../common/up_axi.v verilogSource axi_tdd_pkg.sv systemVerilogSource axi_tdd_channel.sv systemVerilogSource axi_tdd_counter.sv systemVerilogSource axi_tdd_regmap.sv systemVerilogSource axi_tdd_sync_gen.sv systemVerilogSource axi_tdd.sv systemVerilogSource xilinx_xpgui_view_fileset xgui/axi_tdd_v1_0.tcl tclSource CHECKSUM_931062b4 XGUI_VERSION_2 ADI AXI TDD Controller ID Id 0 CHANNEL_COUNT Channel Count 8 DEFAULT_POLARITY Default Polarity "00000000" REGISTER_WIDTH Register Width 32 BURST_COUNT_WIDTH Burst Count Width 32 SYNC_INTERNAL Sync Internal 1 SYNC_EXTERNAL Sync External 0 SYNC_EXTERNAL_CDC Sync External Cdc 0 SYNC_COUNT_WIDTH Sync Count Width 64 Component_Name axi_tdd_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices ADI AXI TDD Controller level_2 package_project Analog Devices https://wiki.analog.com/resources/fpga/docs/axi_tdd 1 2024-01-14T03:49:32Z 2023.2.1