analog.com user jesd204_common 1.0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog pipeline_stage xilinx_anylanguagesynthesis_view_fileset viewChecksum 392e3498 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog pipeline_stage xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 392e3498 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum fa2aa10a clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation in in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation out out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation REGISTERED Registered 1 WIDTH Width 1 xilinx_anylanguagesynthesis_view_fileset jesd204_lmfc.v verilogSource jesd204_scrambler.v verilogSource jesd204_scrambler_64b.v verilogSource jesd204_crc12.v verilogSource jesd204_eof_generator.v verilogSource jesd204_frame_mark.v verilogSource jesd204_frame_align_replace.v verilogSource pipeline_stage.v verilogSource CHECKSUM_b063a4fc xilinx_anylanguagebehavioralsimulation_view_fileset jesd204_lmfc.v verilogSource jesd204_scrambler.v verilogSource jesd204_scrambler_64b.v verilogSource jesd204_crc12.v verilogSource jesd204_eof_generator.v verilogSource jesd204_frame_mark.v verilogSource jesd204_frame_align_replace.v verilogSource pipeline_stage.v verilogSource xilinx_xpgui_view_fileset xgui/pipeline_stage_v1_0.tcl tclSource CHECKSUM_fa2aa10a XGUI_VERSION_2 ADI JESD204C Common Library REGISTERED Registered 1 WIDTH Width 1 Component_Name pipeline_stage_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices ADI JESD204C Common Library true level_2 package_project Analog Devices http://www.analog.com 1 2024-01-14T03:51:22Z 2023.2.1