analog.com user axi_dmac 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW m_dest_axi AWID m_dest_axi_awid AWADDR m_dest_axi_awaddr AWLEN m_dest_axi_awlen AWSIZE m_dest_axi_awsize AWBURST m_dest_axi_awburst AWLOCK m_dest_axi_awlock AWCACHE m_dest_axi_awcache AWPROT m_dest_axi_awprot AWVALID m_dest_axi_awvalid AWREADY m_dest_axi_awready WID m_dest_axi_wid WDATA m_dest_axi_wdata WSTRB m_dest_axi_wstrb WLAST m_dest_axi_wlast WVALID m_dest_axi_wvalid WREADY m_dest_axi_wready BID m_dest_axi_bid BRESP m_dest_axi_bresp BVALID m_dest_axi_bvalid BREADY m_dest_axi_bready ARID m_dest_axi_arid ARADDR m_dest_axi_araddr ARLEN m_dest_axi_arlen ARSIZE m_dest_axi_arsize ARBURST m_dest_axi_arburst ARLOCK m_dest_axi_arlock ARCACHE m_dest_axi_arcache ARPROT m_dest_axi_arprot ARVALID m_dest_axi_arvalid ARREADY m_dest_axi_arready RID m_dest_axi_rid RDATA m_dest_axi_rdata RRESP m_dest_axi_rresp RLAST m_dest_axi_rlast RVALID m_dest_axi_rvalid RREADY m_dest_axi_rready SUPPORTS_NARROW_BURST 0 true m_sg_axi AWID m_sg_axi_awid AWADDR m_sg_axi_awaddr AWLEN m_sg_axi_awlen AWSIZE m_sg_axi_awsize AWBURST m_sg_axi_awburst AWLOCK m_sg_axi_awlock AWCACHE m_sg_axi_awcache AWPROT m_sg_axi_awprot AWVALID m_sg_axi_awvalid AWREADY m_sg_axi_awready WID m_sg_axi_wid WDATA m_sg_axi_wdata WSTRB m_sg_axi_wstrb WLAST m_sg_axi_wlast WVALID m_sg_axi_wvalid WREADY m_sg_axi_wready BID m_sg_axi_bid BRESP m_sg_axi_bresp BVALID m_sg_axi_bvalid BREADY m_sg_axi_bready ARID m_sg_axi_arid ARADDR m_sg_axi_araddr ARLEN m_sg_axi_arlen ARSIZE m_sg_axi_arsize ARBURST m_sg_axi_arburst ARLOCK m_sg_axi_arlock ARCACHE m_sg_axi_arcache ARPROT m_sg_axi_arprot ARVALID m_sg_axi_arvalid ARREADY m_sg_axi_arready RID m_sg_axi_rid RDATA m_sg_axi_rdata RRESP m_sg_axi_rresp RLAST m_sg_axi_rlast RVALID m_sg_axi_rvalid RREADY m_sg_axi_rready SUPPORTS_NARROW_BURST 0 false m_src_axi AWID m_src_axi_awid AWADDR m_src_axi_awaddr AWLEN m_src_axi_awlen AWSIZE m_src_axi_awsize AWBURST m_src_axi_awburst AWLOCK m_src_axi_awlock AWCACHE m_src_axi_awcache AWPROT m_src_axi_awprot AWVALID m_src_axi_awvalid AWREADY m_src_axi_awready WID m_src_axi_wid WDATA m_src_axi_wdata WSTRB m_src_axi_wstrb WLAST m_src_axi_wlast WVALID m_src_axi_wvalid WREADY m_src_axi_wready BID m_src_axi_bid BRESP m_src_axi_bresp BVALID m_src_axi_bvalid BREADY m_src_axi_bready ARID m_src_axi_arid ARADDR m_src_axi_araddr ARLEN m_src_axi_arlen ARSIZE m_src_axi_arsize ARBURST m_src_axi_arburst ARLOCK m_src_axi_arlock ARCACHE m_src_axi_arcache ARPROT m_src_axi_arprot ARVALID m_src_axi_arvalid ARREADY m_src_axi_arready RID m_src_axi_rid RDATA m_src_axi_rdata RRESP m_src_axi_rresp RLAST m_src_axi_rlast RVALID m_src_axi_rvalid RREADY m_src_axi_rready SUPPORTS_NARROW_BURST 0 false fifo_rd_clk CLK fifo_rd_clk fifo_wr_clk CLK fifo_wr_clk m_axis_aclk CLK m_axis_aclk m_dest_axi_aclk CLK m_dest_axi_aclk ASSOCIATED_BUSIF m_dest_axi ASSOCIATED_RESET m_dest_axi_aresetn m_sg_axi_aclk CLK m_sg_axi_aclk ASSOCIATED_BUSIF m_sg_axi ASSOCIATED_RESET m_sg_axi_aresetn m_src_axi_aclk CLK m_src_axi_aclk ASSOCIATED_BUSIF m_src_axi ASSOCIATED_RESET m_src_axi_aresetn s_axis_aclk CLK s_axis_aclk m_dest_axi_aresetn RST m_dest_axi_aresetn POLARITY ACTIVE_LOW m_sg_axi_aresetn RST m_sg_axi_aresetn POLARITY ACTIVE_LOW m_src_axi_aresetn RST m_src_axi_aresetn POLARITY ACTIVE_LOW s_axis TREADY s_axis_ready TVALID s_axis_valid TDATA s_axis_data TSTRB s_axis_strb TKEEP s_axis_keep TUSER s_axis_user TID s_axis_id TDEST s_axis_dest TLAST s_axis_last false s_axis_signal_clock s_axis_signal_clock CLK s_axis_aclk ASSOCIATED_BUSIF s_axis m_axis TREADY m_axis_ready TVALID m_axis_valid TDATA m_axis_data TSTRB m_axis_strb TKEEP m_axis_keep TUSER m_axis_user TID m_axis_id TDEST m_axis_dest TLAST m_axis_last false m_axis_signal_clock m_axis_signal_clock CLK m_axis_aclk ASSOCIATED_BUSIF m_axis fifo_wr EN fifo_wr_en DATA fifo_wr_din OVERFLOW fifo_wr_overflow SYNC fifo_wr_sync XFER_REQ fifo_wr_xfer_req true fifo_wr_signal_clock fifo_wr_signal_clock CLK fifo_wr_clk ASSOCIATED_BUSIF fifo_wr fifo_rd EN fifo_rd_en DATA fifo_rd_dout VALID fifo_rd_valid UNDERFLOW fifo_rd_underflow false fifo_rd_signal_clock fifo_rd_signal_clock CLK fifo_rd_clk ASSOCIATED_BUSIF fifo_rd irq INTERRUPT irq SENSITIVITY LEVEL_HIGH m_dest_axi m_dest_axi 0x100000000 64 m_sg_axi m_sg_axi 0x100000000 64 m_src_axi m_src_axi 0x100000000 64 s_axi axi_lite 0 2048 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_dmac xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum 13fa364a xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_dmac xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 13fa364a xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_util_axis_fifo_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum 8b30a977 xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_analog_com_user_util_axis_fifo_1_0__ref_view_fileset xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_blockdiagram_view_fileset xilinx_utilityxitfiles Utility XIT/TTCL :vivado.xilinx.com:xit.util xilinx_utilityxitfiles_view_fileset s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 10 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 10 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation irq out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_dest_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_dest_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_dest_axi_awaddr out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_dest_axi_awlen out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_dest_axi_awsize out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_dest_axi_awburst out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_dest_axi_awprot out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_dest_axi_awcache out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_dest_axi_awvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_dest_axi_awready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_dest_axi_awid out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_dest_axi_awlock out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_dest_axi_wdata out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_dest_axi_wstrb out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_dest_axi_wready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_dest_axi_wvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_dest_axi_wlast out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_dest_axi_wid out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_dest_axi_bvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_dest_axi_bresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_dest_axi_bready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_dest_axi_bid in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_dest_axi_arvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_dest_axi_araddr out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_dest_axi_arlen out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_dest_axi_arsize out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_dest_axi_arburst out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_dest_axi_arcache out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_dest_axi_arprot out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_dest_axi_arready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_dest_axi_rvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_dest_axi_rresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_dest_axi_rdata in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_dest_axi_rready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_dest_axi_arid out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_dest_axi_arlock out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_dest_axi_rid in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_dest_axi_rlast in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_arready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_arvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_araddr out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_arlen out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_arsize out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_arburst out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_arprot out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_arcache out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_arid out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_arlock out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_rdata in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_rready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_rvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_rresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_rid in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_rlast in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_awvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_awaddr out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_awlen out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_awsize out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_awburst out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_awcache out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_awprot out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_awready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_wvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_wdata out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_wstrb out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_wlast out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_wready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_bvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_bresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_bready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_awid out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_awlock out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_wid out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_src_axi_bid in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_arready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_arvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_araddr out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_arlen out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_arsize out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_arburst out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_arprot out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_arcache out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_arid out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_arlock out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_rdata in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_rready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_rvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_rresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_rid in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_rlast in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_awvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_awaddr out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_awlen out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_awsize out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_awburst out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_awcache out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_awprot out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_awready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_wvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_wdata out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_wstrb out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_wlast out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_wready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_bvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_bresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_bready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_awid out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_awlock out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_wid out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_sg_axi_bid in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axis_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axis_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axis_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axis_data in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axis_strb in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axis_keep in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axis_user in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 false s_axis_id in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axis_dest in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axis_last in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axis_xfer_req out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_axis_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_axis_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_axis_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_axis_data out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_axis_strb out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_axis_keep out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_axis_user out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_axis_id out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_axis_dest out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_axis_last out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false m_axis_xfer_req out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true fifo_wr_en in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true fifo_wr_din in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true fifo_wr_overflow out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true fifo_wr_sync in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 true fifo_wr_xfer_req out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true fifo_rd_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_rd_en in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_rd_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_rd_dout out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_rd_underflow out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_rd_xfer_req out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dest_diag_level_bursts out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false ID Id 0 DMA_DATA_WIDTH_SRC Dma Data Width Src 64 DMA_DATA_WIDTH_DEST Dma Data Width Dest 64 DMA_DATA_WIDTH_SG Dma Data Width Sg 64 false DMA_LENGTH_WIDTH Dma Length Width 24 DMA_2D_TRANSFER Dma 2d Transfer false DMA_SG_TRANSFER Dma Sg Transfer false ASYNC_CLK_REQ_SRC Async Clk Req Src true ASYNC_CLK_SRC_DEST Async Clk Src Dest true ASYNC_CLK_DEST_REQ Async Clk Dest Req true ASYNC_CLK_REQ_SG Async Clk Req Sg true ASYNC_CLK_SRC_SG Async Clk Src Sg true ASYNC_CLK_DEST_SG Async Clk Dest Sg true AXI_SLICE_DEST Axi Slice Dest false AXI_SLICE_SRC Axi Slice Src false SYNC_TRANSFER_START Sync Transfer Start false CYCLIC Cyclic false DMA_AXI_PROTOCOL_DEST Dma Axi Protocol Dest 0 DMA_AXI_PROTOCOL_SRC Dma Axi Protocol Src 0 false DMA_AXI_PROTOCOL_SG Dma Axi Protocol Sg 0 false DMA_TYPE_DEST Dma Type Dest 0 DMA_TYPE_SRC Dma Type Src 2 DMA_AXI_ADDR_WIDTH Dma Axi Addr Width 32 MAX_BYTES_PER_BURST Max Bytes Per Burst 128 FIFO_SIZE Fifo Size 8 AXI_ID_WIDTH_SRC Axi Id Width Src 1 AXI_ID_WIDTH_DEST Axi Id Width Dest 1 AXI_ID_WIDTH_SG Axi Id Width Sg 1 DMA_AXIS_ID_W Dma Axis Id W 8 DMA_AXIS_DEST_W Dma Axis Dest W 4 DISABLE_DEBUG_REGISTERS Disable Debug Registers false ENABLE_DIAGNOSTICS_IF Enable Diagnostics If false ALLOW_ASYM_MEM Allow Asym Mem 0 CACHE_COHERENT Cache Coherent false AXI_AXCACHE Axi Axcache "0011" false AXI_AXPROT Axi Axprot "000" false choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_list_7e15dc94 64 choice_list_9a3ef62d 2 4 8 16 32 choice_list_9ca20931 LEVEL_HIGH LEVEL_LOW EDGE_RISING EDGE_FALLING choice_list_a4302b20 16 32 64 128 256 512 1024 2048 choice_pairs_1293c054 0 1 2 choice_pairs_8bd59fa5 1 0 xilinx_anylanguagesynthesis_view_fileset axi_dmac_constr.ttcl ttcl ../common/ad_mem_asym.v verilogSource inc_id.vh verilogSource true address_generator.v verilogSource axi_dmac_burst_memory.v verilogSource axi_dmac_regmap.v verilogSource axi_dmac_regmap_request.v verilogSource axi_dmac_reset_manager.v verilogSource axi_dmac_resize_dest.v verilogSource axi_dmac_resize_src.v verilogSource axi_dmac_response_manager.v verilogSource axi_dmac_transfer.v verilogSource axi_register_slice.v verilogSource data_mover.v verilogSource dest_axi_mm.v verilogSource dest_axi_stream.v verilogSource dest_fifo_inf.v verilogSource dmac_2d_transfer.v verilogSource dmac_sg.v verilogSource request_arb.v verilogSource request_generator.v verilogSource resp.vh verilogSource true response_generator.v verilogSource response_handler.v verilogSource splitter.v verilogSource src_axi_mm.v verilogSource src_axi_stream.v verilogSource src_fifo_inf.v verilogSource ../common/up_axi.v verilogSource bd/bd.tcl tclSource axi_dmac.v verilogSource CHECKSUM_9c4d9b37 xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset axi_dmac_pkg_sv.ttcl ttcl ../common/ad_mem_asym.v verilogSource inc_id.vh verilogSource true address_generator.v verilogSource axi_dmac_burst_memory.v verilogSource axi_dmac_regmap.v verilogSource axi_dmac_regmap_request.v verilogSource axi_dmac_reset_manager.v verilogSource axi_dmac_resize_dest.v verilogSource axi_dmac_resize_src.v verilogSource axi_dmac_response_manager.v verilogSource axi_dmac_transfer.v verilogSource axi_register_slice.v verilogSource data_mover.v verilogSource dest_axi_mm.v verilogSource dest_axi_stream.v verilogSource dest_fifo_inf.v verilogSource dmac_2d_transfer.v verilogSource dmac_sg.v verilogSource request_arb.v verilogSource request_generator.v verilogSource resp.vh verilogSource true response_generator.v verilogSource response_handler.v verilogSource splitter.v verilogSource src_axi_mm.v verilogSource src_axi_stream.v verilogSource src_fifo_inf.v verilogSource ../common/up_axi.v verilogSource bd/bd.tcl tclSource axi_dmac.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/axi_dmac_v1_0.tcl tclSource CHECKSUM_6f5028ec XGUI_VERSION_2 xilinx_xpgui_analog_com_user_util_axis_fifo_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource xilinx_blockdiagram_analog_com_user_util_axis_fifo_1_0__ref_view_fileset xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_utilityxitfiles_view_fileset gui/axi_dmac_v1_0.gtcl GTCL ADI AXI DMA Controller ID Core ID 0 DMA_DATA_WIDTH_SRC Bus Width 64 DMA_DATA_WIDTH_DEST Bus Width 64 DMA_DATA_WIDTH_SG Bus Width 64 false DMA_LENGTH_WIDTH DMA Transfer Length Register Width 24 DMA_2D_TRANSFER 2D Transfer Support false DMA_SG_TRANSFER SG Transfer Support false ASYNC_CLK_REQ_SRC Request and Source Clock Asynchronous true ASYNC_CLK_SRC_DEST Source and Destination Clock Asynchronous true ASYNC_CLK_DEST_REQ Destination and Request Clock Asynchronous true ASYNC_CLK_REQ_SG Request and Scatter-Gather Clock Asynchronous true ASYNC_CLK_SRC_SG Source and Scatter-Gather Clock Asynchronous true ASYNC_CLK_DEST_SG Destination and Scatter-Gather Clock Asynchronous true AXI_SLICE_DEST Insert Register Slice false AXI_SLICE_SRC Insert Register Slice false SYNC_TRANSFER_START Transfer Start Synchronization Support false true CYCLIC Cyclic Transfer Support false DMA_AXI_PROTOCOL_DEST AXI Protocol 0 true DMA_AXI_PROTOCOL_SRC AXI Protocol 0 false DMA_AXI_PROTOCOL_SG AXI Protocol 0 false DMA_TYPE_DEST Type 0 DMA_TYPE_SRC Type 2 DMA_AXI_ADDR_WIDTH DMA AXI Address Width 32 MAX_BYTES_PER_BURST Maximum Bytes per Burst 128 FIFO_SIZE Store-and-Forward Memory Size (In Bursts) 8 AXI_ID_WIDTH_SRC Axi Id Width Src 1 AXI_ID_WIDTH_DEST Axi Id Width Dest 1 AXI_ID_WIDTH_SG Axi Id Width Sg 1 DMA_AXIS_ID_W Dma Axis Id W 8 DMA_AXIS_DEST_W Dma Axis Dest W 4 DISABLE_DEBUG_REGISTERS Disable Debug Registers false ENABLE_DIAGNOSTICS_IF Enable Diagnostics Interface false ALLOW_ASYM_MEM Allow Asym Mem 0 CACHE_COHERENT Cache Coherent false true AXI_AXCACHE ARCACHE/AWCACHE "0011" false AXI_AXPROT ARPROT/AWPROT "000" false Component_Name axi_dmac_v1_0 virtex7 /Analog_Devices ADI AXI DMA Controller level_2 package_project Analog Devices https://wiki.analog.com/resources/fpga/docs/axi_dmac 1 2024-06-06T03:02:18Z 2024.1