analog.com user cn0363_phase_data_sync 1.0 S_AXIS_SAMPLE TVALID s_axis_sample_valid TREADY s_axis_sample_ready TDATA s_axis_sample_data M_AXIS_SAMPLE TVALID m_axis_sample_valid TREADY m_axis_sample_ready TDATA m_axis_sample_data M_AXIS_PHASE TVALID m_axis_phase_valid TREADY m_axis_phase_ready TDATA m_axis_phase_data S_AXIS_SAMPLE_M_AXIS_SAMPLE_M_AXIS_PHASE_signal_clock S_AXIS_SAMPLE_M_AXIS_SAMPLE_M_AXIS_PHASE_signal_clock CLK clk ASSOCIATED_BUSIF S_AXIS_SAMPLE:M_AXIS_SAMPLE:M_AXIS_PHASE ASSOCIATED_RESET resetn S_AXIS_SAMPLE_M_AXIS_SAMPLE_M_AXIS_PHASE_signal_reset S_AXIS_SAMPLE_M_AXIS_SAMPLE_M_AXIS_PHASE_signal_reset RST resetn POLARITY ACTIVE_LOW xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog cn0363_phase_data_sync xilinx_anylanguagesynthesis_view_fileset viewChecksum c791119f xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog cn0363_phase_data_sync xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum c791119f xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f92e9879 clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation resetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation processing_resetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_sample_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_sample_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_sample_data in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sample_has_stat in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation conv_done in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation phase in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_sample_valid out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_sample_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_sample_data out 23 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_phase_valid out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_phase_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_phase_data out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation overflow out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation xilinx_anylanguagesynthesis_view_fileset cn0363_phase_data_sync.v verilogSource CHECKSUM_c791119f xilinx_anylanguagebehavioralsimulation_view_fileset cn0363_phase_data_sync.v verilogSource xilinx_xpgui_view_fileset xgui/cn0363_phase_data_sync_v1_0.tcl tclSource CHECKSUM_f92e9879 XGUI_VERSION_2 cn0363_phase_data_sync_v1_0 Component_Name cn0363_phase_data_sync_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /Analog_Devices cn0363_phase_data_sync_v1_0 level_2 package_project Analog Devices http://www.analog.com 1 2024-06-06T03:06:36Z 2024.1